Design of a Sonar Data Acquisition System Based on Zynq ARM+FPGA

Currently, the development of sonar data acquisition systems generally involves selecting microprocessors or microcontrollers, Field Programmable Gate Arrays (FPGAs), or Digital Signal Processors (DSPs) as the main control chips. Wang Min et al. [8] used a DSP running the VxWorks operating system to implement a Transmission Control Protocol/Internet Protocol (TCP/IP) network protocol stack, capable of real-time transmission of sonar system acquired data and computation results back to a computer. Zhang Yanpin [9] designed an underwater acoustic signal acquisition and processing platform based on the OMAP-L138 chip, which achieved continuous acquisition, processing, storage, and transmission of underwater acoustic signals, and enabled the upload of underwater acoustic data stored on a secure digital card via a Light Weight IP (LwIP) network protocol stack. Rong Zhiyuan [10] combined the high-speed parallel processing capabilities of FPGAs with the flexible process control capabilities of Advanced RISC Machine (ARM) processors to design an FPGA+ARM-based sonar data acquisition and transmission system, meeting the requirements for high precision and real-time performance in acquisition systems. Jing Boyuan et al. [11] used an Artix-7 series FPGA chip to control data acquisition and storage for multi-channel data acquisition, and transmitted vector hydrophone data to the host computer via a Universal Serial Bus 2.0 interface. Shi Pengteng [12] utilized an Ethernet IP core to implement the User Datagram Protocol (UDP) for high-speed transmission of multi-channel sonar acquisition data, and developed a communication protocol at the application layer for interaction with the host computer and packet loss handling, thereby overcoming issues such as data errors and loss inherent in unreliable, connectionless protocols like UDP.

In the aforementioned literature, the design of sonar data acquisition systems primarily focused on using single-architecture chips like DSPs or FPGAs, failing to simultaneously leverage the convenience of serial processors like microprocessors and DSPs for implementing complex control logic such as network protocol stacks, and the powerful parallel processing advantages of FPGAs. However, using a DSP+FPGA architecture also presents a series of problems [13-14]: Firstly, the routing work is relatively complex, requiring more hardware design effort. Secondly, integration is low, occupying a larger area, and costs are higher. In terms of power consumption and heat dissipation, this solution generates higher power consumption under computation-intensive tasks, requiring better heat dissipation and power supply solutions. Currently, designs for sonar data acquisition systems rarely feature online program update functionality under watertight conditions or considerations for data framing when using the TCP transmission protocol for data transfer.

Addressing the miniaturization, high integration, and low power consumption design of UUV-mounted forward-looking active sonar, as well as the need for program updates under underwater enclosed operating conditions, this paper selects the Xilinx Zynq7020 chip to build an active sonar data acquisition platform. This chip adopts an advanced dual-core heterogeneous architecture [15-17], integrating Programmable Logic (PL) and Processing System (PS) units into a single chip, balancing the parallel computing advantages of FPGAs with the flexibility of processor system software development, overcoming the limitations of inter-chip communication bandwidth and processing speed bottlenecks in traditional dual-chip architectures, offering high integration and low power consumption. On the PL side, data acquisition control and signal pre-processing tasks such as digital down-conversion are completed to meet the system's real-time requirements. In conjunction with the developed host computer software, the LwIP network protocol stack runs on the ARM processor of the PS side to process TCP data streams in real-time, thereby fully leveraging the advantages of the Zynq7020 heterogeneous architecture. Regarding the choice of data acquisition and transmission scheme, considering real-time transmission speed, bandwidth, and reliability requirements, the system designed in this paper uses Ethernet to achieve data interaction between the active sonar and the host computer software, and to ensure data transmission reliability, this system uses the TCP/IP protocol as the data transmission protocol, combined with a custom application layer frame protocol, to establish a connection between the slave device and the host computer via Ethernet [18]. For the choice of data storage medium, the system selected a high-capacity, high-speed read/write embedded multimedia card (eMMC) [19-20] chip, ensuring the integrity and reliability of data recording. Regarding the choice of FPGA program update method, the system uses TCP Ethernet to achieve online program updates and developed corresponding host computer software, which can avoid complex wiring operations while ensuring the integrity of the UUV's watertight structure, enabling convenient and controllable updates of the system's FPGA program.

1 System Hardware Design

The system described in this paper mainly consists of host computer software located on the PC side and active sonar transmit and receive circuits located inside the UUV (wet end). The overall structure of the system is shown in Figure 1.

4 Test Results and Analysis

4.1 Data Acquisition Function Verification

To test whether the data acquisition function of the system meets the expected design, one acquisition channel was selected, and a continuous sine wave signal was generated using a signal generator and directly input to the ADC input of the data acquisition module. The input signal frequency was 13.2 kHz, and the amplitude was 1 V. The host computer's data acquisition control parameter configuration interface is shown in Figure 12. The acquisition signal length was set to 3 s, the center frequency for digital down-conversion was 12 kHz. Clicking the "Start Acquisition" button sends the acquisition parameters to the slave device via Ethernet and simultaneously notifies the slave device's data acquisition module to start acquiring data. After data acquisition is complete, clicking the "Save Data" button notifies the slave device to upload the acquired data to the host computer and save it as a .txt file.

5 Conclusion

This paper designed a stable and reliable data acquisition and storage system based on the Zynq7020 heterogeneous platform, combining the parallel computing advantages of FPGAs with the flexibility of processor system software development. It runs the LwIP network protocol stack on the Zynq7020 PS side to implement the TCP protocol, achieving data interaction between the active sonar and the host computer via Ethernet. Simultaneously, by using a custom application layer frame format, it fully leverages the high reliability advantages of the TCP protocol while avoiding data packet "stickiness" issues, integrating real-time acquisition, storage, and transmission of active sonar system data, as well as online program update functionality, offering advantages such as strong scalability, good flexibility, and high integration. The designed online program update function avoids damaging the UUV's watertight structure, and its update speed has a significant advantage over JTAG interface update methods, greatly improving experimental testing efficiency.

Experimental verification has shown that the system designed in this paper can operate stably for extended periods, the acquired and stored data is authentic and usable, closely matching actual requirements, providing effective data support for subsequent theoretical algorithm verification, scheme improvement, and equipment debugging in the project.