[Domestic Virtual Instruments] High-Speed Data Acquisition FPGA EnDat Design for Semiconductor Motion Stages Based on DSP+FPGA (Part 3)

Implementation of the EnDat Bidirectional Serial Communication Protocol

Semiconductor motion stages demand absolute position feedback with sub-micron repeatability and deterministic latency. This post covers Part 3 of a DSP+FPGA design series focused on implementing the EnDat 2.2 bidirectional serial communication protocol in an FPGA, including line delay compensation, mode command framing, CRC verification, and the full data-request pipeline driven by a DSP top-level controller.

Protocol Overview and Physical Layer

Data — whether measured position values, encoder parameters, or diagnostic information — flows bidirectionally between the position encoder and the EnDat protocol core. The physical layer uses RS-485 differential signaling, which provides excellent common-mode noise rejection suited to the electrically noisy environment of a semiconductor fab. All data transfers are synchronous: the clock pulses are generated by the servo control system on the DSP side and propagated to the encoder, which samples incoming mode-command bits on each rising edge and drives position data back in lock-step.

The EnDat interface was designed by HEIDENHAIN to give machine-tool and motion-control systems a high-performance, low-cost digital encoder link. Its key advantages over analog sin/cos interfaces include deterministic timing, built-in error detection, and a rich command set for reading encoder metadata and health diagnostics [42-44].

Termination Network

To match the characteristic impedance of the differential lines and prevent signal reflections, a 120 Ω termination resistor is placed at the far end of each differential pair (DATA+ / DATA− and CLK+ / CLK−). A 330 pF capacitor is placed in parallel with each line to attenuate high-frequency noise. Without correct termination, reflections at the cable endpoints corrupt edges and force the designer to run at lower clock frequencies than the cable would otherwise support.

EnDat 2.2 vs. 2.1

EnDat 2.2 is a strict superset of EnDat 2.1: every mode command defined in 2.1 is valid in 2.2, so 2.2 masters can communicate with 2.1 encoders without modification. The 2.2 revision brings four practical improvements:

1. Higher maximum clock frequency — enabling faster position-update rates
2. Shorter encoder calculation time — reduces the dead-time between command and response
3. Shorter recovery time — allows tighter inter-frame gaps
4. Wider supply voltage range — simplifies power rail design in mixed-voltage systems

Line Transmission Delay Compensation

Why Delay Matters

The EnDat clock frequency is software-configurable by the DSP application layer anywhere from 100 kHz to 16 MHz. The usable frequency depends on cable length: as the cable gets longer, or the clock gets faster, the round-trip propagation delay becomes a non-negligible fraction of a clock period. Without delay compensation, there is no way to distinguish "data arrived late" from "no data arrived," so the uncompensated maximum clock frequency is limited to 2 MHz [43].

With active delay compensation, the maximum clock frequency rises to 16 MHz, enabling the high-speed position acquisition needed by semiconductor lithography and die-bonding stages.

Automatic Compensation Procedure

Because delay is a property of the physical cable — not the encoder — it must be remeasured whenever the cable or connector is changed. To keep the system self-calibrating, the EnDat protocol core performs automatic delay measurement on every power-up, before the first normal data transfer. The procedure is:

1. The EnDat core issues the mode command "encoder transmits position value without additional information" at a reduced clock frequency of 100 kHz (chosen to ensure the propagation delay is a small, measurable fraction of the clock period).
2. The core records the timestamp of every rising edge of the clock.
3. The interval between the last detected rising edge and the start flag bit is defined as the transmission delay t_D.
4. Steps 1–3 are repeated three times; the average of the three measurements is used as the compensation value.
5. As a sanity check, the three individual measurements must not differ by more than one-eighth of a clock period at the measurement frequency — if they do, the measurement is flagged as unreliable.

The internal time reference used for the delay measurement must run at a frequency at least eight times the data-transfer clock frequency to achieve sufficient resolution.

This compensation loop runs entirely inside the EnDat protocol core without DSP intervention and is transparent to the application layer.

Data Types and Mode Commands

EnDat defines three categories of payload data:

| Type | Content | |---|---| | Position value | Absolute encoder position (LSB first, MSB last) | | Additional information | Diagnostics, temperature, reference-mark data | | Parameters | Encoder configuration, metadata, and health registers |

Mode commands are 3-bit fields. The core transmits each bit on the falling edge of the transfer clock; the encoder latches each bit on the rising edge. To guard against single-bit upsets, each mode-command bit is sent either inverted or repeated. With line-delay compensation active, the very first clock of every transfer must remain low for at least 2 µs before transitioning, giving the encoder time to detect the start of frame regardless of propagation delay [43].

The full mode-command table (Table 4.2 in the original thesis) confirms that every EnDat 2.1 command code is a member of the EnDat 2.2 command set.

Position Value Transmission Format and CRC

Frame Structure

A position-value transfer cycle begins on the first falling clock edge. After two clock periods (2T), the core transmits the mode command 000111. Once the encoder successfully receives the command, it begins streaming the response:

1. Start flag — marks the beginning of the encoder's reply
2. ERR1 / ERR2 — error indicator bits, set if a fault condition exists in the encoder
3. Position data — transmitted LSB-first, MSB-last; the total bit count is determined by the encoder's resolution parameter, which can be queried at runtime
4. 5-bit CRC — appended immediately after the position data

After the last CRC bit, the data line is driven high and held idle until the next request.

When additional information is requested, the frame extends with two additional fields — Additional Information 1 and Additional Information 2 — each followed by its own 5-bit CRC, as shown in Figure 4.22 of the source design.

CRC Generation

The 5-bit Cyclic Redundancy Check catches all single-bit transmission errors. The encoder generates the CRC in hardware using a fixed polynomial (specified by HEIDENHAIN in Figure 4.23 of the EnDat standard [43]). The FPGA implementation of the EnDat core must use the identical polynomial and shift-register topology — implemented in Verilog HDL as a small network of XOR gates and D flip-flops — so that the locally regenerated CRC matches the received CRC for error-free frames. A mismatch sets the error flag in the status register and can trigger an interrupt to the DSP.

FPGA Implementation of the EnDat Protocol Core

Core Architecture

The EnDat protocol core (Figure 4.24) is composed of six sub-modules:

| Sub-module | Function | |---|---| | Timing control | Master state machine; sequences all TX/RX operations | | Transmit module | Parallel-to-serial conversion of mode commands | | Receive module | Serial-to-parallel conversion of encoder responses | | Clock generation | Produces the configurable-frequency differential clock | | Register file | TX register, mode-command register, configuration register, status register, interrupt register | | Fiber-optic interface | Parallel bus bridge to the fiber-optic communication core |

The left-hand interface of the core connects to the RS-485 physical layer: separate TX, RX, and CLK differential pairs each with their own enable signals. The right-hand interface is a parallel bus connecting to the fiber-optic communication core: an 8-bit address bus (limiting the number of addressable data words to 255, matching the maximum packet payload) and a 32-bit data bus, along with control and interrupt lines.

Register File Operation

The TX register, mode-command register, and configuration register hold the outgoing payload. On a transfer trigger:

• The timing controller activates the transmit module, which serializes the register contents and drives them to the encoder in sync with the generated clock.
• Simultaneously, the clock generation module produces exactly the right number of clock pulses for the selected mode command.
• The receive module captures the incoming serial stream, performs serial-to-parallel conversion, and distributes the decoded fields across three receive registers according to their meaning (position value, additional information 1, additional information 2).
• The status register is updated with the CRC result and any ERR flags; the interrupt register is set; and an interrupt or trigger signal is sent to the fiber-optic core [50].

Position Value Data Request and Transmission Pipeline

The DSP is the top-level controller for all data transfers. Transfers are classified by direction:

• Downstream process: DSP → EnDat core (configuration writes, parameter updates)
• Upstream process: DSP requests a position value; the encoder responds

The upstream flow operates as follows (Figure 4.25):

1. The DSP issues a "request position data" command.
2. Fiber-optic core A (co-located with the DSP) receives the trigger and transmits the special 8b/10b character K28.2 (a TTC-class comma character) over the high-speed optical link.
3. Fiber-optic core B (co-located with the encoder and FPGA) detects K28.2 and immediately activates the EnDat core, which launches the encoder position-request sequence.
4. On completion, core B packages the position data and status information into the defined packet format and sends it back over the fiber link to core A.
5. Core A receives the packet and asserts an interrupt, waking the DSP to read and process the fresh position value.

This fiber-isolated, interrupt-driven architecture decouples the electrically sensitive encoder-side FPGA from the DSP compute node, eliminates ground-loop issues common in precision motion systems, and allows the optical link to span distances that RS-485 alone could not cover reliably at multi-MHz clock rates.

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Sienovo provides a production-ready FPGA implementation of the EnDat protocol core described in this series, suitable for direct integration into DSP+FPGA motion-control platforms targeting semiconductor equipment applications.