# Sienovo International — Full Content > Exclusive global distributor for intelligent edge AI computing solutions. > Website: https://intl.sienovo.cn ## Company Overview Sienovo is a technology company headquartered in San Francisco, CA. We specialize in intelligent edge AI computing hardware and industrial embedded solutions. As the exclusive global distributor for advanced edge AI devices, we serve industries including smart city infrastructure, industrial automation, transportation, and security. ### Core Product: INT-AIBOX-P-8 The INT-AIBOX-P-8 is an Intelligent Edge AI Analytics Box featuring: - **Processor**: Domestic TPU CV186AH - **AI Performance**: 7.2 TOPS INT8 - **Video Channels**: 8-channel HD video analytics - **AI Algorithms**: 40+ built-in algorithms including object detection, face recognition, behavior analysis, vehicle analytics - **Connectivity**: Ethernet, RS485, GPIO, USB, HDMI - **Power**: Low-power design suitable for edge deployment - **Use Cases**: Smart city, industrial inspection, traffic monitoring, perimeter security, retail analytics ### Application Scenarios - Traffic management and vehicle analytics - Factory floor monitoring and safety compliance - Perimeter intrusion detection - Retail footfall and behavior analysis - Smart campus and building management - Agricultural monitoring ## Contact Information - Email: collin.liu@sienovo.cn - WhatsApp: +86 187 1868 8532 - Demo: https://calendly.com/sienovo - Address: 600 California St, San Francisco, CA 94108 --- # Blog Articles (1638 total) ## Design of an Ultra-HD Real-Time Image Acquisition and Compression System Based on ZYNQ MPSoC ARM+FPGA - URL: https://intl.sienovo.cn/blog/161368361 - Date: 2026-05-24 - Tags: #ARMDev, #FPGADev, #Server, #DevOps, #AI, #EmbeddedHardware, #Linux 3.1 Overview of Overall Hardware Solution Based on the analysis of system architecture and方案 in Sections 2.1 and 2.2, this chapter provides a detailed introduction to the system's hardware design. The hardware block diagram of the high-performance real-time video acquisition and compression platform described in this paper is shown in Figure 3-1. The system consists of a core processing module, a video capture module, an off-chip data storage module, a video compression data output module, a power module, a clock and reset module, and other MPSoC peripheral interfaces. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/161368361/01_3a6c5caf2a2e44dc912d87059d98e52b.png) The board's video capture module features four HDMI 2.0 receiver ports capable of supporting 4K (3840×2160) resolution video input at a 60Hz refresh rate. High-speed differential video signals are passed through de-jittering and level-shifting chips before being transmitted to the system's core—the ZYNQ MPS --- ## Overall Design Scheme for ZYNQ MPSoC-Based Image Acquisition and Compression System - URL: https://intl.sienovo.cn/blog/161368097 - Date: 2026-05-24 - Tags: #FPGADev, #ARMDev, #AI, #EmbeddedHardware, #Linux 2.1 Introduction In flight missions, high-definition video data has become a critical basis for analyzing flight status and evaluating system performance. However, the massive data volume generated by 4K ultra-high-definition video poses significant challenges to acquisition, processing, and storage systems. An uncompressed 4K@60Hz video stream produces approximately 12 Gbit of data per second. Without effective compression, such data becomes difficult to transmit in real time or store long-term. Therefore, based on mission requirements, this paper presents the design of an image processing system capable of acquiring and compressing multiple high-definition video streams. The system must support real-time acquisition, processing, H.265 compression, and multi-path output of 4K@60Hz video, along with precise timestamp watermarking functionality. 2.2 Requirement Analysis and Technical Specifications According to the mission specifications, the image acquisition and compressi --- ## Design and Implementation of an MPSoC-Based Hardware Platform for Autonomous Driving Multi-Sensor Fusion Localization - URL: https://intl.sienovo.cn/blog/161366456 - Date: 2026-05-24 - Tags: #AI, #ARMDev, #EmbeddedHardware, #FPGADev ## ### 1. Introduction High-precision localization is a core prerequisite for environmental perception, path planning, and vehicle motion control in autonomous driving. The accuracy and timing synchronization performance of localization directly determine the reliability and safety of autonomous driving systems. Currently, mainstream localization solutions mostly adopt a **discrete multi-module architecture**: multi-sensor data acquisition relies on independent hardware boards, while positioning computation and algorithm acceleration depend on industrial PCs, GPUs, or high-end CPUs. This separated architecture has several engineering drawbacks: hardware interconnection among multiple modules results in low system integration and bulky structure; inter-board communication introduces transmission latency, making it difficult to achieve microsecond-level time synchronization across sensors; general-purpose computing platforms tend to have high power consumption and heat dissipation, --- ## Architecture Design and Engineering Practice of Multi-Axis Servo Motor Drivers Based on ZYNQ MPSoC - URL: https://intl.sienovo.cn/blog/161366275 - Date: 2026-05-24 - Tags: #FPGADev, #EmbeddedHardware, #ARMDev, #AI, #SpeechRecognition ## ### 1. Introduction In high-precision industrial applications such as **industrial robots, CNC machine tools, missile actuators, phased array antennas, and automated production lines**, the core requirement is **independent control + high-precision synchronization** of multi-axis servo motors. Currently, two mainstream traditional solutions both face clear bottlenecks: 1. **Pure DSP Software Approach**: Serial interrupt execution limits performance; single DSP computing power is insufficient for high-precision multi-axis control. Multi-DSP parallel configurations are costly, have low integration, and suffer from inter-axis desynchronization. 2. **Pure FPGA Hardware Approach**: Offers strong parallel real-time performance, but speed and position loop algorithms are hard-coded into hardware, resulting in poor versatility and inflexible parameter configuration or algorithm iteration. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/161366275/01_e6c4babe6a1340d29e --- ## RK3568 + CODESYS + Real-Time Motion Controller PLC with AI Vision Object Detection, Predictive Maintenance, Hybrid Multi-System Deployment, and Multi-Channel Analog Acquisition - URL: https://intl.sienovo.cn/blog/161292822 - Date: 2026-05-21 - Tags: #AI, #EmbeddedHardware, #ARMDev, #FPGADev XM3503 is a mid-to-large-sized controller designed for process automation applications, balancing performance, expandability, and cost-efficiency. It supports AI-based vision object detection, predictive maintenance, containerized resource isolation and management, as well as hybrid multi-system deployment. The XM3503 offers flexible communication options and hot-swappable local I/O expansion capabilities, making it an ideal solution that strikes the optimal balance between reliability and cost across packaging, logistics, machine tools, and process control applications. As a stable and flexible solution for mainstream manufacturing, the XM3503 enables users to achieve high cost-performance and future expansion during automation upgrades. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/161292822/01_7cf24a41f00d4aefbf56f49f395a21aa.png) General Information Engineering Configuration Software CODESYS SP19 or later (compliant with IEC 61131-3 and IEC 61499 standards) P --- ## Power Equipment with RK3568/RK3576 + FPGA: Multi-System Hybrid Deployment of Linux + RTOS RT-Thread for Strong Real-Time Performance - URL: https://intl.sienovo.cn/blog/161186239 - Date: 2026-05-20 - Tags: #Linux, #DevOps, #Server, #AI, #EmbeddedHardware, #FPGADev Core Value of RTOS Real-Time Kernel for Relay Protection Devices The RTOS real-time kernel delivers a foundational technology platform tailored to power grid security requirements, leveraging hard real-time performance, strong isolation, and high reliability. It addresses key industry challenges across four dimensions—fault response, operational safety, environmental adaptability, and cost control—while synergizing with Linux to maximize the efficiency of multi-system hybrid deployment. This makes RTOS a critical enabler for technological advancement and domestic localization of relay protection devices. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/161186239/01_ac1c7a81b52240ef8189fbfd640ace72.jpeg) 1. Microsecond-Level Hard Real-Time Response Ensures Timely Fault Handling RTOS employs a preemptive scheduling mechanism, keeping interrupt latency and task switching within microseconds, with predictable and precise execution timing. This completely eliminates the --- ## FPGA-based Single-Board Miniaturized Digital Interference Source, Capable of Generating Arbitrary IF Frequency Output from 500MHz to 3000MHz - URL: https://intl.sienovo.cn/blog/160851415 - Date: 2026-05-07 - Tags: #FPGADev, #AI, #ObjectDetection, #ComputerVision, #SignalProcessing, #EdgeComputing The XM250M3G is a single-board miniaturized digital interference source designed for electronic countermeasure (ECM) applications. Built around an FPGA signal-processing core, it generates arbitrary intermediate-frequency (IF) output anywhere in the 500 MHz–3000 MHz band and supports selectable instantaneous bandwidths up to 250 MHz — all within a compact module the size of a credit card. This post covers the board's architecture, key specifications, and the practical engineering trade-offs that make it useful in airborne, vehicle-mounted, and ground-based jamming systems. ## What Is a Digital Interference Source? Traditional analog jammers generate noise or tone signals using VCO/PLL chains and analog noise sources. A *digital* interference source replaces that analog back-end with an FPGA (or DSP+FPGA combination) that synthesizes the interference waveform in the digital domain, then converts it to the analog IF through a high-speed DAC. This approach offers several concrete advant --- ## Data Acquisition Solution for Safety Monitoring and Management Systems of Large Cranes and Construction Machinery - URL: https://intl.sienovo.cn/blog/160827561 - Date: 2026-05-06 - Tags: #FPGADev, #ARMDev, #AI, #EmbeddedHardware #### **Data Acquisition for Safety Monitoring and Management Systems of Large Cranes and Construction Machinery** Construction machinery has always been paramount for the execution of large-scale projects, a history spanning 10 years from 2016 to the present. Previously, perhaps due to less advanced machinery, there were fewer ECU (Electronic Control Unit) control units, making it difficult to acquire much of the data needed for project safety monitoring and management. With the deepening implementation of the Belt and Road Initiative, construction machinery has become increasingly advanced, and electrification and intelligence have profoundly impacted the field. Equipment such as excavators, loaders, bulldozers, road rollers, pavers, cranes, tower cranes, concrete pump trucks, mixer trucks, rotary drilling rigs, tunnel boring machines, graders, milling machines, crushers, aerial work platforms, piling machines, scrapers, and dump trucks have largely achieved digitalization and inte --- ## Design of a ZYNQ-based Marine Data Analyzer - URL: https://intl.sienovo.cn/blog/160559313 - Date: 2026-04-27 - Tags: #SpeechRecognition, #AI, #ARMDev, #EmbeddedHardware, #FPGADev ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/160559313/01_6bb7ebb7267947afa64a2155cc262f85.png) **1、 Application Background** The shipborne black box is a common name for a Voyage Data Recorder (VDR) or Simplified Voyage Data Recorder (SVDR), abbreviated as VDR or SVDR. It is designed to assist in subsequent accident investigations by safely and recoverably preserving all navigational information for a period before and after a maritime incident. The volume of this navigational data is very large, creating an urgent need for large-capacity data storage solutions. Traditional storage solutions based on USB drives, hard drives, and SD/MMC cards, while capable of large-capacity data storage, are unsatisfactory in terms of system size, cost, power consumption, reliability, and ease of use. Therefore, there is an urgent need for a large-capacity, high-reliability data storage solution that offers lower cost, power consumption, and size. ![](https://pub-048dcb96257f476697 --- ## ZYNQ MPSOC-based Multi-channel Sound and Vibration Acquisition Solution, Replacing NI9234 and B&K - URL: https://intl.sienovo.cn/blog/160532851 - Date: 2026-04-26 - Tags: #AI, #FPGADev, #EmbeddedHardware, #ARMDev Real-time, high-speed, and accurate acquisition of ship noise signals is the starting point and most fundamental step for ship vibration and noise reduction, as well as fault diagnosis. To address the three different types of noise encountered in ships—airborne noise, underwater noise, and vibration noise—corresponding sensors can be selected for precise measurement. Specifically, microphones can be used to measure airborne noise, accelerometers are suitable for capturing noise generated by vibration, and hydrophones are specifically designed to detect underwater noise. By utilizing these three specialized sensors, various types of ship noise can be effectively measured and analyzed in detail [4]. Subsequently, an acquisition system is designed to convert these electrical signals, after conditioning, acquisition, quantization, and encoding, into computer-recognizable digital signals. ZYNQ series chips integrate two core components: the Processor System (PS) and the Programmable Logic --- ## RK3588-based Ultra-Small, Lightweight, Long-Endurance Drone AI Module with Video Tracking Support - URL: https://intl.sienovo.cn/blog/160495950 - Date: 2026-04-25 - Tags: #Drone, #AI, #EmbeddedHardware, #ARMDev, #FPGADev An RK3588-based ultra-small drone AI module, measuring **45×45mm and weighing 24.5g**, with a **6TOPS NPU**, natively supporting **visible light / infrared video tracking**, with a latency of < 100ms, suitable for drone narrowband transmission and lightweight payload requirements. I. Core Hardware (RK3588) CPU: Octa-core (4×A76@2.4GHz + 4×A55@1.8GHz) NPU: 6TOPS, supports tracking models such as YOLO/SSD/DeepSORT Process / Power Consumption: 8nm LP, entire board \*\*≤6W\*\*, suitable for airborne low-power scenarios Dimensions / Weight: 45×45×5mm, 24.5g (40g with casing) II. Video Tracking Capabilities (Drone-Specific) Input: 2×MIPI‑CSI (up to 4K@30fps), analog / digital interfaces, compatible with visible light / infrared cameras Algorithm: Self-developed KCF/DSST + deep learning, supports multi-target detection, locking, and continuous tracking Accuracy / Metrics: Tracking accuracy \*\*≤1 pixel\*\*, minimum target 3×3 pixels, strong resistance to occlusion / interference Latency: En --- ## High-Performance Multi-Axis Servo Design Solution Based on ARM+FPGA MPSoC - URL: https://intl.sienovo.cn/blog/160399587 - Date: 2026-04-22 - Tags: #FPGADev, #ARMDev, #AI, #EmbeddedHardware, #Architecture Permanent magnet synchronous motors (PMSMs) eliminate the need for rotor excitation devices and excitation current, offering advantages such as simple structure and small size. They have broad prospects, especially in applications with limited space requiring precise multi-axis servo control, such as industrial robots, CNC machine tools, missile actuators, and phased array antennas [1-2]. Currently, multi-axis servo control systems primarily include software solutions based on digital signal processors (DSPs) and hardware solutions based on field-programmable gate arrays (FPGAs). DSP software solutions are inexpensive, highly flexible, and can implement various control algorithms, thus finding widespread application. In recent years, companies like TI have introduced DSP control chips specifically for motors, offering powerful computational performance and incorporating many peripheral units required for actual motor control, becoming mainstream servo control products in the market. --- ## STM32 + FPGA-Based Design and Implementation of a Marine Power Station Controller - URL: https://intl.sienovo.cn/blog/159354629 - Date: 2026-03-22 - Tags: #FPGADev, #ARMDev, #AI, #EmbeddedHardware, #Architecture, #STM32 In recent years, with the rapid development of semiconductor technology, microcontrollers (MCUs) based on ARM architecture and Field-Programmable Gate Arrays (FPGAs) have been widely applied in industrial field control due to their excellent performance, comprehensive functionality, stable supply, and lower costs [1]. Their application in marine engine room automation is also continuously deepening, showing broad application prospects. Previous marine power station controllers typically centered around PLC devices, requiring corresponding basic modules such as power transducers, synchronization and paralleling modules, and digital input/output modules. Therefore, previous single generator set control units were built upon PLC-centric marine power station controllers. Such power station control systems had extremely complex networking and required significant installation space, greatly limiting their application prospects in modern vessels, especially in all-electric propulsion vesse --- ## ARM+FPGA+AI-based Smart Ship Condition Monitoring System (Part 2): Hardware and Software Design, Analog and Temperature Data Acquisition and Analysis - URL: https://intl.sienovo.cn/blog/159322922 - Date: 2026-03-21 - Tags: #FPGADev, #ARMDev, #AI, #ObjectDetection Based on the overall equipment design, the hardware board set has been determined to consist of one core board and three functional boards. The core board is procured externally, while the three functional boards are self-developed. The core board for this project primarily includes the ZYNQ main control chip, among others. The specific chip model needs to be further determined. Based on project requirements and detailed analysis, the main requirements for selecting the core board are as follows: (1) Since this design involves multi-channel vibration signal, temperature signal, analog voltage, and current data acquisition, as well as the design of multiple communication interfaces, there is a significant demand for resources such as the main control chip's pins. Furthermore, as these functionalities are implemented on the FPGA, substantial FPGA logic resources are also required. Additionally, for data storage using solid-state drives, the main control chip needs to possess high-speed --- ## ARM+FPGA+AI-based Smart Ship Condition Monitoring System (Part 1) Overall Design - URL: https://intl.sienovo.cn/blog/159322870 - Date: 2026-03-21 - Tags: #Networking, #AI, #FPGADev, #AutonomousDriving, #MachineLearning, #ARMDev This article provides an in-depth analysis of the system requirements, specifications, and overall design for ship engine room monitoring equipment. First, by thoroughly analyzing the system's functions and design characteristics, the design goals and requirements are clearly defined. Second, based on these needs and requirements, hardware and software system design solutions are proposed to achieve precise, reliable, and efficient performance. This in-depth exposition of the system's overall design provides a solid foundation for subsequent detailed design and implementation. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/159322870/01_af75368044404a00992682fb3721af10.png) 2.1 Device Functional Requirements Analysis The overall objective of this project is to develop a complete set of ship engine room monitoring equipment for collecting various information about the ship's own equipment and its surrounding environment, performing data monitoring, transmission, and re --- ## ZYNQ MPSOC-Based Ship Data Acquisition Instrument Design (Part 3): Vibration, Flow, Power Consumption, EMC, and Reliability Testing - URL: https://intl.sienovo.cn/blog/159319171 - Date: 2026-03-21 - Tags: #EmbeddedHardware, #ARMDev, #AI, #FPGADev 5.3.1 Vibration Signal Acquisition Channel Performance Testing To ensure the vibration signal acquisition channel can filter out high-frequency noise, an anti-aliasing low-pass filter circuit was designed in this paper. Simulation tests were performed using Multisim software. The simulation schematic is shown in Figure 5-2 a), and the amplitude-frequency characteristic curve is shown in Figure 5-2 b). When the gain is -3dB, the cutoff frequency is approximately 11kHz, which meets the design specifications. Next, to verify the AD7768's acquisition performance for different analog vibration signals at a 128 kHz sampling rate, a signal generator was first used to output 2.5 V signals of various frequencies. Each frequency signal was tested 20 times, and the sampled voltage was compared with the actual 2.5 V. The summarized test data is shown in Table 5-3. AD7768 vibration signal acquisition monitoring is shown in Figure 5-3. Online monitoring was performed using the Logic Analyzer (IL --- ## ZYNQ MPSOC-based Ship Data Acquisition Instrument Design (Part 2): EMC Reliability Design - URL: https://intl.sienovo.cn/blog/159319057 - Date: 2026-03-21 - Tags: #fpga开发, #嵌入式硬件, #人工智能, #arm开发 Main Control Board Circuit Design The main control board circuit design is shown in Figure 3-1, primarily including the peripheral circuits of the main control chip and the design of some functional circuits. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/159319057/01_0d38ee685088457ca493e384fb2fab38.png) 3.5 Electromagnetic Compatibility Design for Cabin Environment Electromagnetic interference in a ship environment is complex and variable. To ensure stable and reliable operation of the data acquisition and recording device, electromagnetic compatibility (EMC) design must be emphasized in hardware design. This design adopted the following EMC measures: (1) Hardware Circuit Electromagnetic Compatibility Design: In the circuit design of this system, particular attention was paid to power quality and signal integrity: ① Each power node is configured with decoupling capacitor filtering, using 10μF and 0.1μF capacitors in parallel to filter out low-frequency and high- --- ## Design of a ZYNQ MPSoC-Based Marine Data Acquisition Instrument (Part 1): Overall Design Scheme, Including Parameters such as Vibration, Pressure, Temperature, and Flow - URL: https://intl.sienovo.cn/blog/159318881 - Date: 2026-03-21 - Tags: #FPGADev, #ARMDev, #AI, #EmbeddedHardware This article analyzes the hardware platform performance and software logic design of the device based on the centralized data acquisition and record management requirements within ship cabins, and accordingly formulates the overall scheme. The hardware platform is based on the ZYNQ MPSoC (XCZU5EV) processor, which integrates ARM and FPGA architectures. To meet the centralized multi-parameter data acquisition needs in cabins, a multi-channel high-precision analog acquisition circuit and a multi-protocol communication interface circuit are designed. By completing the driver logic design for the AD chips of various analog acquisition channels on the PL (Programmable Logic) side of the XCZU5EV, a total of 44 channels of high-precision analog acquisition functions for vibration, temperature, pressure, etc., are realized. Simultaneously, driver logic for UART and CAN bus communication protocols is designed to enable data transmission and reception, frame parsing, and timestamping functions --- ## ZYNQ ARM+FPGA+AI Multi-channel Ship Noise Acquisition System: High Precision, High Real-time, Supporting Edge AI Analysis - URL: https://intl.sienovo.cn/blog/159242148 - Date: 2026-03-19 - Tags: #FPGADev, #ARMDev, #AI With the advancement of electronic communication and automation technologies across various sectors, ships, while ensuring fundamental maritime safety and transportation security, are increasingly emphasizing providing a more comfortable and healthier navigation environment for crew and passengers. Against this backdrop, effective acquisition and control of ship noise have become essential for addressing these concerns. This paper proposes a multi-channel ship noise acquisition system based on the ZYNQ platform, tailored to the demands of ship automation and intelligence. The ZYNQ architecture, with its synergistic soft-core and hard-core capabilities, high-speed data processing, compact size, and low power consumption, is highly suitable for such applications. This system enables real-time, high-speed, and accurate acquisition of ship noise, thereby providing reliable data support for subsequent noise processing and control, enhancing navigation safety, and improving passenger comfor --- ## RK3588 8-USB Industrial Control Solution for Machine Vision, Industrial IoT, and More - URL: https://intl.sienovo.cn/blog/158313877 - Date: 2026-02-23 - Tags: #ARMDev, #AI, #FPGADev The RK3588 is a high-performance ARM-architecture processor, widely used in industrial control, edge computing, multimedia processing, and other fields. Designing an industrial control solution for the RK3588 platform that supports 8 USB interfaces typically requires combining hardware design with system software configuration to achieve stable data transmission and device management.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/158313877/01_09344d581ceb4f8787e9a19236ff4e8c.jpeg) Key aspects of this solution include: 1. **Hardware Design**: * Utilize the RK3588 chip as the main control unit, extending multiple USB interfaces via USB Hub controllers. * A multi-stage Hub topology can be adopted; for instance, using two 4-port Hub chips connected to the RK3588's two USB 3.0 interfaces, thereby achieving a total of 8 USB interfaces. * Ensure the power management module provides stable power to all USB devices. Overcurrent protection and hot-swap su --- ## PC-based Control Technology + EtherCAT + Linux Real-time System Powers Scalable Tracking Label Production, Supporting Domestic Solutions - URL: https://intl.sienovo.cn/blog/157653091 - Date: 2026-02-02 - Tags: #EmbeddedHardware, #ARMDev, #AI, #YOLO, #FPGADev Reelables founder Brian Krejcarek's entrepreneurial inspiration stemmed from a particular moment: while hiking, he suddenly realized he had forgotten his lip balm. This idea gradually evolved into a grander vision: what if there was a way to actively track items, so you'd know what you'd left behind before heading out? Reelables' initial business-to-consumer (B2C) model eventually shifted to a business-to-business (B2B) model, as they recognized greater opportunities in freight forwarding, logistics, and warehousing. The company's goal is to create an extremely low-cost, scalable tracking label that can be attached to virtually any item, ultimately replacing traditional barcodes or QR codes with active trackers that continuously broadcast location information. **Reelables currently produces two types of smart labels:** * **Bluetooth Tracking Labels:** Suitable for asset tracking across various industries, especially in high-value logistics scenarios where delays incur significant --- ## Jetson AGX Orin+FPGA+GMSL+AI Embodied Intelligence Machine Vision Solution, Customizable - URL: https://intl.sienovo.cn/blog/155968807 - Date: 2025-12-16 - Tags: #AI Jetson AGX Orin+FPGA+GMSL+AI Machine Vision Solution ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/155968807/01_55a45b946a3d4e30bfe20a6fa08a3450.png) The new Jetson AGX Orin Vision Development Kit features a triple upgrade in hardware architecture, synchronization capabilities, and driver framework, significantly enhancing the development efficiency and performance of visual perception modules for edge AI devices: **|** **Hardware Architecture Upgrade — Simple and Easy to Use** The kit features Sienovo's proprietary carrier board and sub-board architecture, supporting **up to 8-channel GMSL1/2 camera access** with the capability to **expand to 16 channels**. The sub-board can flexibly adapt to various types of deserializer chips, such as MAX9296, 96712, 96724, etc., and can be extended to support protocols like FPD-LINK/V-by-One. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/155968807/02_017d348361624aa38ccd8065c091e890.png) **The kit features a sid --- ## High-Bandwidth, Low-Latency Machine Vision Solution Based on JETSON ORIN + FPGA + GMSL + AI - URL: https://intl.sienovo.cn/blog/155714869 - Date: 2025-12-08 - Tags: #Networking, #ObjectDetection, #AI, #ComputerVision, #FPGADev, #AutonomousDriving GMSL High-Bandwidth Access Leveraging the GMSL 2 protocol, it offers excellent anti-interference performance and long-distance transmission capabilities, effectively solving the challenge of long-distance deployment between robot controllers and cameras. Through GMSL and MIPI-CSI VC multi-channel merging technology, it can efficiently integrate data from multiple cameras, significantly reducing the number of cables. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/155714869/01_293574d658e2422bac913d005f493023.jpeg) Low-Latency Data Access To address the high-bandwidth data transmission challenges posed by parallel access from multiple cameras, an optimized transmission protocol ensures that data is directly transferred from the driver layer via DMA to application memory after acquisition, bypassing kernel buffering and copying. This significantly reduces latency and CPU utilization. Concurrently, high-bandwidth transmission is achieved via a high-speed PCIe interface, me --- ## AI Vision Perception Solution for Agricultural Robots Leveraging JETSON/RK3588 and FPGA - URL: https://intl.sienovo.cn/blog/155714799 - Date: 2025-12-08 - Tags: #AI, #Robotics, #FPGADev, #ComputerVision Crop Row Visual Navigation System Scenario Requirement: A crop row visual navigation system is a critical technology for agricultural machinery to achieve autonomous navigation in the field. By using front and rear cameras to capture crop row images in real-time, and leveraging visual algorithms to quickly identify and track the centerline of crop rows, agricultural machinery can be guided to move precisely and autonomously along the crop direction. This is suitable for precision agriculture applications. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/155714799/01_d09bbe77f6894c9cb9b75d94db59ac62.jpeg) Product Application: Sienovo's Machine Vision GMSL Series builds cost-effective GMSL vision solutions with a lightweight design that can operate efficiently even on low-power embedded devices, ensuring uninterrupted signal transmission. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/155714799/02_8b3052183928483896329044c2f00d95.jpeg) Agricultural Picking --- ## JETSON/RK3588+FPGA+AI-based Commercial Autonomous Mowing Robot Solution - URL: https://intl.sienovo.cn/blog/155714747 - Date: 2025-12-08 - Tags: #AI, #Robotics, #FPGADev, #ObjectDetection, #ComputerVision Scenario Requirements: Currently, comprehensive solutions for commercial autonomous mowing robots are still in the preliminary research phase. For research teams and developers, the core demand centers on a visual perception solution tailored for mowing scenarios: This solution needs to efficiently handle complex environments such as varying lighting, diverse obstacles, and ambiguous boundaries in unstructured lawns. It must be cost-effective, open, and easy to develop, supporting intensive algorithm iteration and ground truth validation. Furthermore, it must reliably achieve three core capabilities: real-time semantic segmentation, obstacle recognition, and precise boundary determination, thereby accelerating the transition from laboratory prototypes to stable products.     ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/155714747/01_c6a57b115ed24028ac85a8413074c0af.jpeg) Product Application: The robotic stereo camera integrates a global shutter, 720P resolution, and st --- ## JETSON/RK3588+FPGA+AI+GMSL Embodied AI Visual Perception - URL: https://intl.sienovo.cn/blog/155714620 - Date: 2025-12-08 - Tags: #AI, #FPGADev, #AutonomousDriving, #MachineLearning Scenario Requirements: Embodied AI faces challenges in dynamic and complex real-world environments, simultaneously achieving "precise understanding of 3D space," "real-time correlation with body movements," and "flexible adaptation to scene changes." Currently, mainstream vision solutions are distributed in the robot's head and wrist. Head vision requires global perception to achieve environment modeling, object recognition, and interaction understanding; while wrist vision requires close-range fine perception to support grasping and positioning, operational precision control, and object state judgment. The two work together to meet the demands of global decision-making and local fine manipulation. Robot Stereo Camera: ■ Supports 5MP high-definition resolution, 60fps frame rate, with an observation range covering 0.25m-10m, suitable for robot head-mounted observation; ■ Equipped with an industrial-grade image sensor, offering stronger environmental adaptability and anti-interference --- ## JETSON Orin + FPGA + GMSL + AI Visual Perception for Collaborative Robots - URL: https://intl.sienovo.cn/blog/155714512 - Date: 2025-12-08 - Tags: #Networking, #FPGADev, #EmbeddedHardware, #ARMDev, #AI, #Robotics Scenario Requirements: Collaborative robots often require "real-time, stable, and precise" visual feedback in high-precision, highly flexible operations. They also need to adapt to complex, dynamic industrial environments with electromagnetic interference, while demanding flexible system deployment and controllable costs. Traditional vision solutions are often limited by transmission bandwidth, distance, anti-interference capabilities, and wiring complexity. Product Application: Sienovo Machine Vision GMSL series GMSL cameras, with their advantages such as low latency, high bandwidth, long distance, anti-interference, simplified integration, and high reliability, can effectively address the core pain points of collaborative robots in terms of visual perception. ■ Multi-resolution output, high frame rate: 1MP (1280H x 960V) resolution and 2MP (1920H x 1200V) resolution optional, with 30-60fps frame rate optional. ■ GMSL 2 Transmission: Uses GMSL 2 communication protocol for data tran --- ## RK3588+Zynq7045 ARM+FPGA+AI Solution, Supporting Fudan Microelectronics' Full Localization for Applications in Intelligent Robots and Other Fields - URL: https://intl.sienovo.cn/blog/155498450 - Date: 2025-12-02 - Tags: #FPGADev, #ARMDev, #AI RK3588 +Zynq7045 ARM+FPGA+AI Solution, supporting Fudan Microelectronics' full localization and applied in intelligent robots and other fields. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/155498450/01_7229fe49ef48442b970a93775f2917b8.png) #### Core Architecture Design * ‌**RK3588**: 8nm process, quad-core A76 + quad-core A55 architecture, integrated 6TOPS NPU, supporting 8K video encoding/decoding and multi-channel camera input‌1. * ‌**ZYNQ7045**: Interconnected with RK3588 via PCIe 3.0, enabling hardware-level signal pre-processing (e.g., DMA acceleration, image enhancement)‌12. * ‌**Domestic Alternatives**: Supports domestic FPGAs such as Unigroup Guoxin Titan-2 PG2T390H, compatible with domestic operating systems like Galaxy Kylin‌7. #### Real-time Performance and AI Capabilities * ‌**Real-time Optimization**: Adopts AMP architecture, with the main core running Linux and the slave core running RTOS, and FPGA achieving 4μs-level inter-core communication --- ## RK3588 Rugged 10-inch Industrial Tablet with Android, HarmonyOS, IP67 - URL: https://intl.sienovo.cn/blog/155455517 - Date: 2025-12-01 - Tags: #Computer * ‌**RK3588 Processor**‌: Octa-core 2.4GHz, supports 8K video decoding, built-in NPU with 6 TOPS computing power, powerful performance. For example, the rugged 10-inch tablet uses the RK3588S processor and supports 5G networks. * ‌**IP67 Protection**‌: Dustproof and waterproof, can be submerged in 1 meter of water for 1 hour, suitable for harsh industrial environments‌2. The Yanwei YW10R rugged tablet is IP67 certified and has strong drop resistance‌3. Key Parameters and Protection Level ‌IP67 Protection‌: Completely dustproof, can be submerged in 1 meter of water for 30 minutes, suitable for humid and dusty industrial environments‌ 6. ‌System Support‌: Compatible with Android 14/15 and HarmonyOS, some models support dual-system switching (e.g., Yanwei YW80R)‌ 3. ‌Processor‌: Equipped with RK3588 octa-core chip (4×A76+4×A55), computing power up to 6 TOPS, supports complex AI tasks‌ #### Application Scenarios * ‌**Extreme Environments**‌: Wide operating temperature range from --- ## Royole Flexible Displays + X86, ARM Display Solutions, In Stock - URL: https://intl.sienovo.cn/blog/155420726 - Date: 2025-11-30 - Tags: #ARMDev, #AI, #FPGADev Royole flexible display X86 and ARM display solutions exhibit significant differences in architecture compatibility, performance, and application scenarios: #### X86 Architecture Solutions * **Performance Advantages**: Suitable for high-load scenarios such as multi-system access and complex data processing, capable of maintaining smooth display refresh rates‌1. * **Compatibility**: Supports traditional industrial software and full operating systems, with a wide range of driver compatibility‌16. * **Thermal Design**: Requires enhanced thermal structures to handle high power consumption, suitable for high-temperature environments‌1. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/155420726/01_abedaa06ade44eb4bd99e49fded99200.png) #### ARM Architecture Solutions * **Low Power Consumption**: Lightweight design with low heat generation, suitable for embedded installations and quiet environments‌12. * **Flexible Deployment**: Supports Android/Linux systems, suita --- ## x86 and ARM-based EtherCAT Motion Controllers, Supporting up to 32 Axes, CODESYS, and Real-time System Optimization - URL: https://intl.sienovo.cn/blog/155416448 - Date: 2025-11-30 - Tags: #EmbeddedHardware, #ARMDev, #AI, #YOLO ARM Platform: Ultra-compact EtherCAT Motion Controller, developed based on ARM architecture, configured with a dual-core ARM processor, featuring 1 x LAN, 1 x EtherCAT, 1 x MicroSD, and Slice IO expansion. * ARM-based EtherCAT Motion Controller supporting up to 32 axes * Dual-core ARM processor * 1 x Ethernet LAN, 1 x EtherCAT, 1 x MicroSD * Supports Modbus TCP, TCP/IP communication * Provides a low-code software development environment - MotionNavi Designer * Provides Advantech BASIC programming language for multi-task development * Retain memory (FRAM) * Supports PTP, linear and circular interpolation, path tables x86 Platform: Ultra-compact EtherCAT Motion Controller, developed based on PC architecture, configured with an Intel Atom processor, featuring 64GB eMMC, 2 x LAN, 2 x USB, and Slice IO expansion. PC-based EtherCAT Motion Controller supporting up to 32 axes. Intel® Atom® Quad-core x6413E Processor. 4 GB DDR4 RAM. 64GB eMMC storage. Equipped with 2 x GbE, --- ## [AI Server Expansion Card] FPGA-based NVMe Storage Array Expansion Card, Supporting Domestic Solutions - URL: https://intl.sienovo.cn/blog/155024880 - Date: 2025-11-19 - Tags: #EmbeddedHardware, #FPGADev, #Energy, #ARMDev ## FPGA-based NVMe Storage Array Expansion Card: A Cost-Effective Solution for Data Centers In the pursuit of reducing data center storage costs, footprint, and power consumption, edge-AI and industrial computing companies are continually exploring innovative solutions. One such approach is the use of FPGA-based NVMe storage array expansion cards, which offer a reliable and high-throughput way to transmit NVMe frames. In this article, we will delve into the concept of directly connected accelerators and NVM-over-Fabric, and explore how this technology can be used to create remote, tiered storage or Ethernet Just a Bunch of Flash (EJBOF). ### Success Stories FPGA-based NVMe storage array expansion cards have emerged as an ideal choice for NVMe storage arrays due to their ability to provide low latency and high throughput. By leveraging this technology, data centers can significantly reduce storage costs, footprint, and power consumption. The use of directly connected accelerators and --- ## FPGA AI GPU Smart Acceleration Card, Supporting Domestic Production - URL: https://intl.sienovo.cn/blog/155024436 - Date: 2025-11-19 - Tags: #FPGADev, #ARMDev, #Energy, #EmbeddedHardware The smart storage acceleration card is based on XILINX VERSALâ ACAP MPSOC. The EP side provides a 1-lane PCIe Gen4 x16 interface, while the RP side supports up to 2-lane PCIe Gen4 x8 or 4-lane PCIe Gen4 x4. It features onboard DDR4-3200MHz cache, offering advantages such as low latency, high performance, low power consumption, low cost, and customizability. It is the preferred acceleration platform for server computing acceleration and storage services, including instance storage, SSD hardware virtualization, storage encryption/decryption, erasure coding, compression/decompression, high-speed data processing, and application offloading.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/155024436/01_115e39f78c054c83a257d3033727126d.png) Virtualization Application Feature Specifications: Ø  256 virtual NVMe PCIe Functions (4PF + 252 VF) Ø  Hardware implements 512 IO queues, each virtual NVMe supports up to 64 IO queues Ø  Direct connection mode, supports 4 * PCIe NVMe SSD --- ## AI Accelerator Card: FPGA GPU Solution with HBM for AI Servers, Supporting Localization - URL: https://intl.sienovo.cn/blog/155023282 - Date: 2025-11-19 - Tags: #FPGADev, #ARMDev, #AI, #Distributed ## FPGA-Based AI Accelerator with HBM2: A High-Bandwidth Solution for Memory-Bound Workloads As AI inference and high-performance computing workloads grow more demanding, the bottleneck increasingly shifts from raw compute to memory bandwidth. Traditional GPU and CPU architectures often struggle when data movement eclipses arithmetic throughput — a regime where FPGA-based accelerators with High Bandwidth Memory (HBM) can offer a compelling edge. This post examines an FPGA accelerator card built around the Xilinx VU37P and integrated HBM2 memory, and explains why this combination is particularly well-suited for memory-latency-constrained applications in AI servers and industrial edge deployments. ## The Core Architecture: Xilinx VU37P and HBM2 The Xilinx UltraScale+ VU37P is one of the largest FPGAs in the Virtex UltraScale+ family. With approximately 2.8 million logic cells (LCs), it provides enormous reconfigurable fabric for implementing custom dataflow pipelines — whether that me --- ## Industrial Touch Panel PC for Energy Storage Power EMS - URL: https://intl.sienovo.cn/blog/154637873 - Date: 2025-11-10 - Tags: #Computer, #YOLO, #AI, #ARMDev, #FPGADev The Energy Storage Energy Management System (EMS) offers comprehensive energy storage monitoring and management functions, covering detailed information on energy storage system equipment (PCS, BMS, electricity meters, fire protection, air conditioning, etc.). It achieves data acquisition, data processing, data storage, data query and analysis, visualized monitoring, alarm management, statistical reports, and other functions. For advanced applications, it supports energy dispatch, providing control functions such as scheduled curves, peak shaving and valley filling, demand control, and backup power. The system performs real-time monitoring and historical data analysis of battery pack performance, and based on the analysis results, it employs an intelligent allocation strategy for charge and discharge control of the battery packs, optimizing battery performance and extending battery life.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/154637873/01_8bf873273f3f4acea1af09bef --- ## Design of an ARM+FPGA-Based Microgrid Coordinated Controller - URL: https://intl.sienovo.cn/blog/154637364 - Date: 2025-11-10 - Tags: #EmbeddedHardware, #ARMDevelopment, #AI, #YOLO #### Brief Description: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/154637364/01_04df2074ab2141b6b40ffeac2d7a5049.jpeg) A microgrid coordinated controller is an intelligent coordinated controller applied in microgrids, distributed generation, energy storage, and other fields. The device supports the integration of equipment such as photovoltaic systems, wind power generation, energy storage systems, and charging stations. By performing 24/7 data acquisition and analysis on the microgrid system, it monitors the operational status and health of PV, wind, energy storage systems, and charging stations. Based on this, with the goal of safe and economically optimized operation, it derives optimal control strategies to regulate the microgrid. This achieves real-time dynamic adjustment of distributed energy resources, energy storage systems, and loads within the microgrid, promoting local consumption of new energy, enhancing grid operational stability, and compensating for --- ## RK3576+FPGA Energy Storage Coordination Controller for PV, Wind, and Energy Storage - URL: https://intl.sienovo.cn/blog/153816162 - Date: 2025-10-24 - Tags: #EmbeddedHardware, #FPGADev, #Energy, #ARMDev, #ProgrammersDay The Energy Storage Coordination Controller is a versatile control device with flexible and customizable logic. It can be tailored with specific control logic according to actual application environment requirements, offering a wide range of applications. It can serve as a coordination controller for new energy stations (photovoltaic, wind power, energy storage), or as a microgrid controller or integrated controller. Product Features 1. Supports a graphical logic configuration tool for on-site visual configuration of device interface signals, processing logic, output control, and fault alarms, as well as program upgrades. Functions can be flexibly customized according to on-site requirements; 2. Features multi-channel signal acquisition and multi-channel control output; 3. Equipped with various communication interfaces, offering powerful and fast communication capabilities, and fully supporting the IEC61850 standard (including GOOSE); 4. The device adopts an integrated design wit --- ## Optimized Design of a ZYNQ-based Hardware Accelerator for Object Detection Algorithms - URL: https://intl.sienovo.cn/blog/153576588 - Date: 2025-10-19 - Tags: #ObjectDetection, #AI, #ComputerVision, #AutonomousDriving, #FPGADev Hardware accelerators for object detection algorithms are core computational modules of a system, playing a critical role in achieving efficient inference and meeting real-time processing demands. To enable efficient algorithm deployment, this chapter employs High-Level Synthesis (HLS) technology to map object detection algorithms onto hardware platforms, and integrates optimization strategies such as fixed-point quantization, operator fusion, and loop unrolling to enhance accelerator performance and algorithmic efficiency. Building upon this, a YOLOv4-tiny hardware accelerated inference module, including key operators like convolution and pooling, has been designed and implemented. 4.1 Introduction to Hardware Acceleration Tools 4.1.1 Principles of High-Level Synthesis Technology![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153576588/01_0c358bf9be5a4e8f8f753fd3387039.png) The abstraction levels in FPGA design can be categorized into four levels from low to high: str --- ## Hardware-Software Co-design Architecture for Zynq-based Object Detection Systems (Part 1) - URL: https://intl.sienovo.cn/blog/153576231 - Date: 2025-10-19 - Tags: #ObjectDetection, #AI, #ComputerVision In today's rapidly advancing era of artificial intelligence, object detection has emerged as a crucial task in the field of computer vision, profoundly transforming human society's production and lifestyle. From environmental perception in autonomous vehicles [1, 2] to defect recognition in industrial quality inspection [3, 4], from surface monitoring in satellite remote sensing [5, 6] to lesion analysis in medical imaging [7], object detection technology has become a vital engine driving the development of artificial intelligence.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153576231/01_8f6f86907ea34490a305974cf7f29e1d.png) However, with the evolution of deep learning technology, object detection algorithms based on Convolutional Neural Networks (CNNs) have shown an exponential increase in network layers, making their computational processes increasingly complex and their parameters exceeding tens of millions. While an increase in network layers improves model detect --- ## Design of JETSON+FPGA+GMSL+AI In-Vehicle Video Acquisition and Storage System (Part 2) System Testing - URL: https://intl.sienovo.cn/blog/153571037 - Date: 2025-10-19 - Tags: #AI, #FPGADev, #AudioVideo 5.1 System Testing and Experimental Platform Setup According to the project requirements, this system needs to acquire high-resolution HD images and output them via a GMSL interface. Therefore, the Sony IMX490-GMSL camera was selected as the image sensor for raw video acquisition. The image sensor model is shown in Figure 5.1. The IMX490 is a CMOS image sensor that supports a maximum output resolution of 2896×1876, approximately 5.4 million effective pixels. Utilizing Gigabit Multimedia Serial Link (GMSL) serializer and deserializer technology, it supports image data output with GMSL interface timing. Furthermore, this GMSL camera can compensate for acquired video images, supporting basic processing such as gamma correction, white balance, saturation, and chroma. Register parameters can be configured for different resolutions, allowing the frame rate of the video images output by the GMSL camera to be adjustable within the 30-60 fps range. The camera's actual power consumption typical --- ## Design of an In-Vehicle Video Acquisition and Storage System Based on JETSON+FPGA+GMSL+AI - URL: https://intl.sienovo.cn/blog/153558722 - Date: 2025-10-19 - Tags: #FPGADev, #AI, #AudioVideo ## Overview Designing a reliable in-vehicle video acquisition and storage system demands careful orchestration of high-speed serial video links, real-time embedded processing, and precise timestamp synchronization. This post walks through the hardware architecture of a GMSL-based system built around a Xilinx Spartan-6 FPGA, the TI DM8168 heterogeneous SoC, Maxim GMSL serializer/deserializer pairs, and a Sony IMX490 image sensor — covering component selection rationale, signal flow, and circuit-level design decisions. ## System Architecture The system is organized into four functional modules that together form a pipeline from raw camera capture to compressed network delivery and raw-data archival: 1. **GMSL Video Acquisition and Conversion Unit** — serializer, deserializer, FPGA controller, DDR3 buffer, and interface timing conversion logic 2. **DM8168 Embedded Digital Video Acquisition Unit** — the main processing SoC, SATA storage, DDR3 buffer, and Gigabit Ethernet output 3. **GP --- ## Design of a GMSL-based In-Vehicle Video Acquisition and Storage System (Part 1) - URL: https://intl.sienovo.cn/blog/153558538 - Date: 2025-10-19 - Tags: #ARMDev, #FPGADev, #Energy 2.1 Introduction to GMSL Interface Technology Currently, for the problem of transmitting large amounts of data in complex in-vehicle platforms, common design methods typically involve increasing parallel buses to boost bandwidth or raise frequency. However, as data volume increases, this places immense pressure on bus data transmission, and the drawbacks of parallel buses become apparent. Data transmission using buses requires strict timing consistency. Traditional parallel buses achieve high-speed, high-bandwidth data transmission by increasing frequency. However, excessively high frequencies can make it difficult for the data transmission frequency to match and remain consistent with the clock frequency. Furthermore, variations in layout and routing can affect the clock, making synchronization difficult, and excessively high frequencies can also cause mutual interference between signals. However, serial transmission can solve this problem because it uses only one signal line, elimin --- ## 【JETSON+FPGA+GMSL+AI】Why Are More Mobile Robots Choosing GMSL Cameras? - URL: https://intl.sienovo.cn/blog/153411691 - Date: 2025-10-16 - Tags: #FPGADev, #AI, #AutonomousDriving, #MachineLearning, #DigitalCameras, #Robotics As the autonomous mobile robot (AMR) market expands, application scenarios are extending from indoor warehousing and logistics to outdoor port freight, unmanned mining trucks, and other fields, continuously raising the performance requirements for their vision systems. In outdoor scenarios, such as automated guided vehicles (AGVs) for port freight, unmanned mining trucks, and smart agricultural machinery, these robots often face harsh and complex working environments, long-distance operations, and high demands for stability and reliability. In indoor environments, such as logistics warehouses, production workshops, and home services, robots need to perform more complex tasks, requiring higher real-time performance and high-resolution images from their vision systems. Traditional USB cameras, limited by transmission latency, noise immunity, and transmission distance, can no longer meet these requirements. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153411691/01_ad --- ## 【JETSON+FPGA+GMSL+AI】How to Achieve High-Precision Time Synchronization for Cameras in Autonomous Driving and Mobile Robots? - URL: https://intl.sienovo.cn/blog/153411071 - Date: 2025-10-16 - Tags: #FPGADev, #AutonomousDriving, #AI, #CNN, #Networking, #MachineLearning ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153411071/01_0b96fa0a1335084a34e8db56562ff3d2.png) RGB Point Cloud Map _(Source: Internet)_ In fields such as autonomous driving and machine vision, multi-sensor collaborative perception is crucial for reliable system operation. Whether for localization and navigation, mapping, or obstacle detection, data fusion from cameras and other sensors (such as LiDAR, IMU, etc.) is essential. Time synchronization plays a critical role in data fusion, especially in high-speed motion scenarios like autonomous driving and mobile robots, where synchronization requirements are even higher, typically demanding sub-millisecond (ms, 1e-3s) precision. NVIDIA Jetson AGX Orin, with its high computing power and flexible scalability, has become a mainstream computing platform in autonomous driving, mobile robotics, and other domains. However, achieving high-precision synchronization for cameras connected to the Orin platform remains a key cha --- ## [JETSON+FPGA+GMSL] Multifunctional Image Acquisition Card: Addressing Industrial Vision Challenges with High Integration and Multi-Channel Solutions - URL: https://intl.sienovo.cn/blog/153410845 - Date: 2025-10-16 - Tags: #FPGADev, #AutonomousDriving, #AI, #MachineLearning Sienovo specializes in autonomous driving, industrial automation, and other fields, dedicated to providing professional image vision products and solutions. Based on customer feedback and industry pain points, and after meticulous R&D and refinement by our team, **Sienovo is launching the new "Ruilong" series of multifunctional image acquisition cards, specifically designed for multi-channel image acquisition applications in the industrial sector.** These cards offer comprehensive capabilities including multi-channel input, high synchronization, and powerful processing, providing flexible, stable, and reliable integrated video acquisition solutions for the industry. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153410845/01_4891996c31a54b74ac212429ea8a1f03.png) **Product Features:** 1. **Multi-Channel Acquisition:** Supports up to 16 channels of video signal input, flexibly adapting to various acquisition needs. 2. **Integrated Encoding, Decoding, and Processing:** --- ## 【JETSON+FPGA+GMSL】Real-world Test Sharing | How to Achieve High-Precision Time Synchronization Between LiDAR and Cameras? - URL: https://intl.sienovo.cn/blog/153410623 - Date: 2025-10-16 - Tags: #fpga开发, #数码相机, #人工智能, #机器人, #自动驾驶, #机器学习 **Foreword** In modern industrial and scientific research fields, the collaborative operation of multi-sensor systems has become the norm. Whether it's the perception systems of autonomous driving vehicles, industrial quality inspection platforms, or scientific data acquisition devices, multiple sensors (such as cameras, LiDAR, etc.) need to operate under strict time synchronization. Currently, multi-sensor systems still face significant synchronization challenges during the data acquisition phase. In distributed systems, different sensors have independent clock bases. Ensuring that devices at different physical locations can operate based on the same time reference is a complex technical problem that urgently needs to be solved. Sienovo, leveraging its technical expertise in visual sensing and autonomous driving, innovatively proposes a "hardware trigger + protocol timing" combined strategy. Based on its self-developed CS300 GPS-Time/Trigger Synchronization Box, Sienovo has create --- ## Jetson AGX Orin+GMSL+AI Vision Development Kit, Supporting Applications such as Autonomous Driving, Robotics, and Industrial Vision - URL: https://intl.sienovo.cn/blog/153410378 - Date: 2025-10-16 - Tags: #Robotics, #AI, #FPGADev, #AutonomousDriving, #MachineLearning ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153410378/01_4050f3e5e8504bfa9b990fc01bafe473.png) The new Jetson AGX Orin Vision Development Kit features a triple upgrade in hardware architecture, synchronization capabilities, and driver framework, significantly enhancing the development efficiency and performance of vision perception modules for edge AI devices: **|** **Hardware Architecture Upgrade – Simple and User-Friendly** The kit adopts a unique carrier board and sub-board architecture, supporting **up to 8 channels of GMSL1/2 camera input** with the capability to **expand to 16 channels**. The sub-board can flexibly adapt to various types of deserializer chips, such as MAX9296, 96712, 96724, etc., and can be extended to support protocols like FPD-LINK/V-by-One. **The kit features a side-exit cable design**, precisely compatible with the Jetson AGX Orin Developer Kit. This design significantly enhances the convenience of kit assembly and ensures neat and order --- ## JETSON+FPGA+GMSL Cameras vs. Traditional Industrial Cameras: How High Dynamic Range and Low Latency are Reshaping Machine Perception Vision? - URL: https://intl.sienovo.cn/blog/153410115 - Date: 2025-10-16 - Tags: #DigitalCamera, #AI, #AutonomousDriving, #MachineLearning As industrial manufacturing strives for "micrometer-level precision and millisecond-level response," traditional industrial cameras have become a bottleneck in many high-end application scenarios. GMSL cameras, originating from the automotive sector, are redefining industrial vision standards with their high dynamic range, clear imaging in low light, and low motion latency. As an innovator in this field, Sienovo GMSL cameras introduce automotive-grade reliability into industrial environments, demonstrating excellent performance in high-speed inspection, robot navigation, and precision measurement. This article will delve into the technical differences between GMSL cameras and traditional industrial cameras, and analyze the core advantages of the product. **I. Technical Comparison of GMSL Cameras and Traditional Industrial Cameras** ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153410115/20_5eea40218ca9990b4973459d31e34daf.png) **1. Architectural Differences: Simpl --- ## EV Charger Fast Charging CAN Simulation and GBT27930 Fast Charging CAN Test - URL: https://intl.sienovo.cn/blog/153330657 - Date: 2025-10-15 - Tags: #AI, #ARMDev, #Distributed, #FPGADev **Background of Power Battery Fast Charging CAN Test** During the charging process, new energy electric vehicle power batteries need to communicate interactively with the charging pile. Through handshake protocols and information exchange, they coordinate information such as the required charging voltage and current, as well as handling measures for errors or severe faults that may occur during charging. To standardize the market, the National Standardization Administration Committee has issued a series of national standard documents. Among these, the interactive communication protocol between the Battery Management System (BMS) of electric vehicles and DC fast charging piles (Chargers) is regulated by the national standard GBT-27930. National standard GB27930 stipulates that the communication bus for power battery fast charging protocol is a standard CAN bus, with an I/O mode of CAN2.0 and a baud rate of 250kbit/s. Communication handshake and information exchange must comply with a --- ## NI Test Solution: ARM+FPGA-based Vehicle Simulation and Battery Calibration - URL: https://intl.sienovo.cn/blog/153330299 - Date: 2025-10-15 - Tags: #AI, #YOLO, #ARMDev, #FPGADev With the popularization of electric vehicles, users have higher demands for the safety performance and range accuracy of new energy vehicle batteries. Data interaction and communication between the power battery and the entire vehicle is a crucial link to ensure safety and accuracy, and related testing is highly valued. To achieve stability and accuracy in bus communication for power battery packs (complete packs or standalone BMS), software is needed to simulate vehicle bus communication data. This, combined with a communication interface card, interacts with the power battery pack to complete the simulation and monitoring of electric vehicle driving conditions. During this process, it's necessary to simulate the CAN bus environment of various ECU nodes in the vehicle, respond to various logical conditions and abnormal faults, and monitor various messages and signal changes from the power battery pack. For power battery packs still in the sample stage, it often also requires monitori --- ## Battery Swelling and Internal Pressure Testing Solution - URL: https://intl.sienovo.cn/blog/153330226 - Date: 2025-10-15 - Tags: #安全, #嵌入式硬件, #arm开发, #人工智能 ## Battery Swelling Internal Pressure Testing During charge-discharge cycles, lithium-ion batteries release gases internally, leading to battery swelling and changes in internal and external pressure. To study the swelling characteristics of batteries, the hydraulic/pneumatic pressure of the electrolyte inside the cell can be directly measured. The Battery Internal Pressure Data Logger is a device independently developed by Sienovo for monitoring changes in the internal gas/liquid pressure of lithium-ion batteries. This device utilizes gas/liquid pressure sensors, and in conjunction with the logger, it can convert gas/liquid pressure into digital signals for storage and upload. This device supports simultaneous measurement and display for 10 or 60 battery samples. It offers both desktop and rack-mount options, with various measurement ranges available, making it suitable for different types of battery cells and various application scenarios. The device's built-in software supports se --- ## NI Data Acquisition Card-Based Battery Swelling Deformation Test System - URL: https://intl.sienovo.cn/blog/153329980 - Date: 2025-10-15 - Tags: #EmbeddedHardware, #FPGADev, #Energy **Lithium Battery Swelling Characteristics** During normal use of lithium batteries, swelling and shrinking are inevitable due to electrochemical reactions, thermal expansion and contraction, liquefaction/vaporization, and other factors, leading to bulging after prolonged accumulation. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153329980/01_5eeca9e19aedc66bb9a9e4f9a5eaa61d.png) _↑Fig: Swollen mobile phone lithium battery packs_   Lithium battery swelling is a characteristic that significantly impacts battery performance and safety, including reversible swelling during rapid charging and discharging, and systemic irreversible swelling after long-term use. Swelling during charging and discharging, if exceeding certain limits, can significantly affect battery performance and even pose risks such as fire and explosion. Irreversible swelling caused by long-term use can affect battery lifespan or lead to risks such like electrolyte leakage. The impact of swelling is p --- ## ARM+FPGA-based Drone Data Acquisition Card with 6-Channel, 24-bit Acquisition - URL: https://intl.sienovo.cn/blog/153191641 - Date: 2025-10-13 - Tags: #Drone, #ARMDev, #FPGADev, #Energy, #EmbeddedHardware In today's rapidly advancing drone technology, the accuracy, real-time performance, and stability of data acquisition have become critical. This data acquisition card is a high-performance data acquisition device specifically designed for drone applications. With advanced technology and exceptional design, it meets the demand for efficient acquisition of various data types by drones in diverse complex environments, providing robust data support for aerial surveying and mapping, agricultural monitoring, environmental inspection, power line inspection, and other fields.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153191641/01_d420ffa367e64c2abeb0c4e0cedc4e48.png) Having undergone rigorous quality inspection and reliability testing, it boasts excellent anti-interference capabilities and stability, enabling reliable operation in various complex environments and reducing data loss and errors. We have meticulously developed this acquisition card to address issues such as low --- ## Industrial Stereo Vision Perception Solution Based on JETSON ORIN+FPGA+GMSL AI Camera - URL: https://intl.sienovo.cn/blog/153133980 - Date: 2025-10-12 - Tags: #Networking, #FPGADev, #CNN **Solution Overview** The industrial stereo vision perception solution integrates high-precision depth perception, high-resolution imaging, high dynamic range, and industrial-grade protection. Combined with deep learning algorithms, it achieves efficient object tracking, scene reconstruction, and spatial semantic understanding, providing stable and reliable visual support for industrial applications. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153133980/01_b56164ec396cfed4eaa22437236592b3.jpeg) **Solution Advantages** ■ High-Precision Depth Perception: By integrating dual-camera image data, it deeply perceives the surrounding visual environment, forming a stereo vision image, enabling high-precision ranging, and providing accurate depth information for industrial scenarios. ■ Excellent Image Quality: Utilizes high-resolution image sensors, combined with excellent distortion correction technology and edge reprojection calibration, ensuring image clarity and accurac --- ## Industrial High Dynamic Range Vision Perception Solution Based on Jetson+GMSL AI Cameras - URL: https://intl.sienovo.cn/blog/153133721 - Date: 2025-10-12 - Tags: #自动驾驶, #人工智能, #机器学习, #fpga开发 **Solution Overview** Sienovo's Industrial High Dynamic Range Vision Perception Solution features an ultra-wide dynamic range, adapts to complex lighting conditions, integrates deep learning algorithms, supports object tracking and scene understanding, and is compatible with mainstream AI platforms, providing an efficient and precise solution for industrial vision. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153133721/01_4ebbb7b9ef478e96f0e2a4c621fba839.jpeg) **Solution Advantages** ■ High Dynamic Range Imaging: Features an ultra-wide dynamic range, adapting to complex and variable industrial lighting environments, ensuring stable imaging under various conditions such as strong light and low light. ■ Deep Learning Integration: Integrates deep learning algorithms, supporting dynamic object tracking, 3D scene reconstruction, and spatial semantic understanding to achieve intelligent vision capabilities. ■ USB Interface Convenience: Utilizes a USB interface, offering --- ## Based on JETSON ORIN/RK3588 + AI Camera: Robotics - Multi-Channel Vision Edge Computing Solution - URL: https://intl.sienovo.cn/blog/153123403 - Date: 2025-10-12 - Tags: #AI, #DigitalCamera, #Robotics **Solution Introduction** The Robotics - Multi-Channel Vision Edge Computing Solution leverages the "Lijian" series cameras from Sienovo, with features such as high resolution, low latency, multiple interfaces, and wide dynamic range. This enables adaptation to various lighting conditions and scenarios, providing robots with multi-dimensional visual information. Based on a high-performance edge computing platform, it achieves real-time processing and analysis of multi-channel visual data, equipping robots with powerful visual perception and real-time decision-making capabilities. It can be widely applied in high-precision real-time perception fields such as intelligent monitoring, industrial automation, and logistics warehousing, providing robots with integrated "perception-decision-control" edge intelligence support.![](https://pub-048dcb96257f476697b113fcb5939cb8.r2.dev/blog/153123403/01_4d84fce512e84d9ebfe79f376e865d0e.png) **Solution Advantages** **High Dynamic Vision** Propri --- ## JETSON/RK3588-Based High Dynamic Range Stereo Vision System Solution for Robotics - URL: https://intl.sienovo.cn/blog/153123200 - Date: 2025-10-12 - Tags: #Robotics, #AI, #FPGADev, #AutonomousDriving, #MachineLearning **Solution Overview** The high dynamic range stereo vision system leverages the exceptional dynamic range of its stereo cameras to adapt to complex lighting conditions, providing stable visual perception for mobile robots. It is compatible with embedded platforms and integrates deep learning algorithms, supporting dynamic object tracking, 3D reconstruction, and semantic understanding. Its industrial-grade protection design (IP67 waterproof, shock-resistant, temperature-tolerant) ensures long-term reliable operation in harsh outdoor and industrial environments. **Solution Advantages** **High Dynamic Vision** Proprietary technology adapts to complex lighting environments, including strong and weak light, ensuring stable and precise visual output. Supports >120dB HDR high dynamic imaging CMOS low-light enhancement ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/153123200/01_f20ac0ef7131d30e8024d627fb335ad9.png) **GMSL Transmission** Utilizes ultra-low latency, high- --- ## GPS/PTP/gPTP-Based Data Synchronization and Timing Solution for Autonomous Driving - URL: https://intl.sienovo.cn/blog/152907753 - Date: 2025-10-10 - Tags: #AutonomousDriving, #AI, #MachineLearning **Solution Introduction** Time synchronization solutions are high-precision time synchronization technologies with wide applications in various fields, including telecommunications, power systems, transportation, and finance. Time synchronization solutions utilize various communication protocols (such as PTP/gPTP) to ensure that devices, systems, or sensors within a network share a unified time standard. This enables precise collaborative work and data synchronization between devices in various fields, including industrial automation, smart manufacturing, and communication networks.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/152907753/01_6ab328b508f94e7f89930ab3eb025bdf.png) **Solution Advantages** The time synchronization solution offers features such as stability, reliability, ease of use, and broad compatibility. By integrating GPS access, it achieves high-precision time synchronization. ■ GPS Precision Navigation System: Compatible with PPS/GPRMC signals, cap --- ## 5G Remote Driving Cockpit Latency Verification Solution Based on JETSON/x86+FPGA+AI - URL: https://intl.sienovo.cn/blog/152907293 - Date: 2025-10-10 - Tags: #fpga开发, #cnn, #人工智能 **Solution Overview** 5G tele-operated driving is a crucial application of connected autonomous driving, providing redundant safety measures for vehicle operation, overcoming challenges such as difficult operations in hazardous environments, and effectively improving operational efficiency. Sienovo's 5G Remote Driving Cockpit Latency Verification Solution efficiently collects vehicle-side sensor data and utilizes 5G communication technology to push data in real-time to the remote cockpit. This solution precisely verifies the system latency from sensor data streams to cockpit display, meeting the latency verification requirements of 5G remote driving cockpits in practical applications, ensuring immediate response for remote driving operations, and enhancing operational efficiency and safety. ![](https://pub-048dcb96257f476697b113fcb5939cb3.r2.dev/blog/152907293/01_2f95e6b86bbabf38d24c13eeee0586df.jpeg) **Solution Advantages** ■ Full-Link Time Synchronization: The acquisition syste --- ## X86+FPGA+GPU-Based Autonomous Driving Data Replay Test Solution - URL: https://intl.sienovo.cn/blog/152906567 - Date: 2025-10-10 - Tags: #AutonomousDriving, #AI, #MachineLearning **Solution Introduction** In Hardware-in-the-Loop (HIL) testing, data replay can directly input real sensor data into in-vehicle hardware to test the performance of perception modules, evaluate the hardware's real-time processing capabilities, and verify the stability of hardware-software co-operation. The autonomous driving data replay test solution is a comprehensive testing solution specifically designed for the autonomous driving domain. It provides full-process support, from road scene data acquisition and sensor data replay to function activation verification, ensuring efficient execution of the testing process, reliable system operation, and helping to improve the R&D efficiency of intelligent driving systems.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/152906567/01_894edf55b3924043ba2fba7e291679cf.png) **Solution Advantages** ■ Multi-sensor data compatibility: Supports various types of sensors (e.g., LiDAR, cameras, millimeter-wave radar, etc.) and data rep --- ## Autonomous Driving Data Acquisition Solution Based on Jetson+FPGA+GMSL+AI - URL: https://intl.sienovo.cn/blog/152904790 - Date: 2025-10-10 - Tags: #AutonomousDriving, #AI, #MachineLearning **Solution Introduction** To develop more complex and advanced autonomous driving systems, extensive sensor data and ground truth data must be collected through road tests to validate sensor functionality and train autonomous driving algorithms. Accurately and efficiently collecting, storing, and transferring data generated by various high-bandwidth sensors on vehicles requires a data acquisition system with multi-sensor acquisition capabilities and powerful computing performance. Such a system must ensure stable device performance, offer flexible configuration and expansion, and provide flexible software-level configuration and data processing to enhance the efficiency and quality of data collection. Addressing the extensive sensor data acquisition and validation needs during the development and testing phases of autonomous driving systems, Sienovo introduces a specialized autonomous driving data acquisition solution. This solution includes the necessary hardware, software, and cu --- ## Hardware-in-the-Loop Injection Testing for Autonomous Driving Leveraging NVIDIA ORIN, FPGA, and AI - URL: https://intl.sienovo.cn/blog/152902438 - Date: 2025-10-10 - Tags: #人工智能, #fpga开发, #自动驾驶, #机器人 **Solution Overview** In the field of autonomous driving, validating the algorithms of domain controllers is a critical step to ensure that autonomous driving technology can be safely and reliably deployed to the market. Hardware-in-the-loop (HIL) injection testing is one of the important testing methods in the development process of autonomous driving systems. By means of simulation or data playback, it tests the performance of autonomous driving systems in various complex scenarios, maximizing the coverage of laboratory tests, reducing the number of field road test items, and improving R&D efficiency. Addressing the challenges of autonomous driving domain controller algorithm validation, Sienovo introduces a hardware-in-the-loop injection testing solution, which covers hardware, software, and customized services, provides a unified toolchain, meets multi-scenario testing needs in a one-stop manner, significantly reduces testing costs, and helps improve R&D efficiency. ![](https: --- ## Vision-Radar Multimodal AI Perception and Positioning System Based on x86 + NVIDIA GPU + FPGA Vision - URL: https://intl.sienovo.cn/blog/152901842 - Date: 2025-10-10 - Tags: #人工智能, #fpga开发, #RK3588, #linux, #rk3568 **Solution Introduction** Introducing a vision-radar multimodal perception system that integrates the spatial modeling capabilities of binocular stereo vision with the high penetration detection advantages of radar to build real-time multimodal environmental perception capabilities. Based on a deep learning algorithm engine, it uses neural networks to achieve high-precision visual relocalization, obstacle detection, map construction, and other functions, enabling autonomous positioning without reliance on GPS. It can be applied in intelligent rail transit and auxiliary safety and navigation systems for mobile unmanned vehicles. **Solution Advantages** The Vision-Radar Multimodal AI Perception and Positioning System integrates multi-source data and achieves precise perception and positioning through deep learning algorithms, providing high-precision, high-reliability positioning solutions for rail transit. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/152901842/01_98 --- ## RK3588 + AI Compute Card as an Alternative to NVIDIA Jetson Solutions: High Compute Power, Supports FPGA Custom Expansion - URL: https://intl.sienovo.cn/blog/152799073 - Date: 2025-10-09 - Tags: #人工智能, #arm开发, #分布式, #fpga开发 #### Technical Comparison and Implementation Path for RK3588 + AI Compute Card as an Alternative to NVIDIA Jetson Solutions ##### 1\. ‌**Hardware Performance and Compute Power Configuration**‌ * ‌**RK3588 Core Advantages**‌: Utilizes 8nm process technology, integrates a 6TOPS NPU, supports INT4/INT8 mixed-precision computation, and can be expanded with AI accelerator cards like Hailo-8 via a PCIe 3.0 interface, achieving a total compute power of 32TOPS‌12. * ‌**Jetson Thor Comparison**‌: NVIDIA's new generation platform offers 2070 FP4 TFLOPS of compute power (approx. 5168 TOPS), which is 160 times that of the RK3588 + expansion solution, but its power consumption is as high as 130W, far exceeding RK3588's typical power consumption of 5W‌34.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/152799073/01_0acabb80ed814fc49662093f36355529.jpeg) ##### 2\. ‌**Edge AI Scenario Adaptability**‌ * ‌**Real-time Requirements**‌: RK3588 exhibits latency below 50ms in 1080P vid --- ## Design of a Convolutional Neural Network Accelerator Based on ZYNQ FPGA+AI+ARM - URL: https://intl.sienovo.cn/blog/152732727 - Date: 2025-10-08 - Tags: #fpga开发, #cnn, #人工智能, #无人机, #RK3588 Research on FPGA-based Convolutional Neural Network Accelerators With the rapid development of deep learning, Convolutional Neural Networks (CNNs) have achieved remarkable results in tasks such as image classification and object detection. However, traditional hardware implementations of CNNs face issues such as insufficient computational power, high energy consumption, and large latency. Field-Programmable Gate Arrays (FPGAs) possess high programmability and parallel processing capabilities, allowing for optimized hardware architectures for specific applications, which can significantly improve CNN inference speed and energy efficiency. Existing FPGA accelerators suffer from problems such as low resource utilization, high design complexity, and data transfer latency bottlenecks, which limit the further practical application of CNNs. Therefore, this paper conducts research from the perspectives of CNN architecture and IP design, aiming to design a high-efficiency, low-power, and prac --- ## Research on a Power Grid Suspension Insulator Defect Detection System Based on ZYNQ ARM+FPGA+AI YOLOv4 - URL: https://intl.sienovo.cn/blog/152732362 - Date: 2025-10-08 - Tags: #人工智能, #YOLO, #arm开发, #fpga开发, #嵌入式硬件 With the rapid development of power systems, insulators, as critical components in power systems, their stability directly affects the normal operation of power equipment. Traditional insulator defect detection methods rely on manual inspection, which is labor-intensive and inefficient, often leading to missed or false detections. Therefore, deep learning-based defect detection technology has gradually become a research hotspot, with significant application prospects in the maintenance of power equipment. This paper primarily focuses on insulator defect detection based on the YOLOv4-Tiny algorithm, and through algorithm optimization and FPGA hardware deployment, it aims to meet the demand for efficient detection in power systems. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/152732362/01_cc41ce078c244e05b0666e0c70c7c48c.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/152732362/02_bd71e2c7dfcb441ba36cbde2930cd908.png) YOLOv4-Tiny\[50\] is a lightweig --- ## Design and Implementation of a Domestic Secure Intelligent Interactive Terminal for EV Charging Piles Based on RK3568+AI, Supporting Complex Interactive Functions and Real-time Data Processing - URL: https://intl.sienovo.cn/blog/152731518 - Date: 2025-10-08 - Tags: #安全, #嵌入式硬件, #arm开发, #人工智能 To meet the demands of multi-party secure collaborative computing, ensure data confidentiality and integrity, and prevent data leakage and tampering, this article designs a secure intelligent interactive terminal suitable for EV charging piles (stations) based on the Rockchip RK3568 chip, adopting a method that combines a domestic operating system with a domestic processor. The terminal supports various complex interactive functions and real-time data processing requirements, which can enhance system stability and security, reduce international reliance, and provide a secure and user-friendly interactive environment at the charging pile (station) side [1-2].![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/152731518/01_50f065ca6fca412cbf54503175b98c6e.png) 1 Embedded Processor RK3568 The RK3568 is a mid-to-high-end, high-performance, low-power quad-core application processor chip. This processor features a quad-core CPU based on the Cortex-A55 architecture, a Mali-G52 GPU --- ## Communication Management Unit for Power Industry, Featuring Domestic CPU, Rich Multi-Network and Multi-Serial Communication Interfaces, Compatible with Domestic OS such as Kylin and Neokylin - URL: https://intl.sienovo.cn/blog/152085998 - Date: 2025-09-25 - Tags: #Energy, #FPGADev, #EmbeddedHardware, #ARMDev A communication management unit specifically designed for the power industry, equipped with a domestic CPU. It offers a wealth of communication interfaces, including multiple network ports and serial ports, meeting the requirements for comprehensive substation monitoring. Compatible with domestic operating systems such as Kylin and Neokylin, it has passed high-level EMC tests and is designed to meet the stringent on-site usage requirements of power and energy environments. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/152085998/01_a4bdc525e9884f26a1aea644d4037ad7.jpeg) Based on Phytium 4-core/8-core processors, this highly localized ARM communication management platform offers 8 Gigabit Ethernet ports and 8 isolated serial ports. * Phytium FT-2000/4-core or D2000/8-core processor, main frequency 2.3~2.6GHz * 8 Gigabit Ethernet ports, 8 full-featured isolated serial ports * HDMI+VGA dual display interfaces * 3 USB2.0, 2 USB3.0 * Supports 2 sets of SATA hard --- ## ZYNQ-based ARM+FPGA+YOLO AI Real-time Fire Monitoring and Recognition System - URL: https://intl.sienovo.cn/blog/152049219 - Date: 2025-09-24 - Tags: #arm开发, #fpga开发, #YOLO 2.1 Overall System Design Flow This paper studies a monitoring system, which requires image acquisition. The system should be able to connect to cameras or other image sensors to acquire image data in real time. Next, logical design is performed on the FPGA to achieve real-time image preprocessing [27-28], including denoising, Gaussian filtering, and histogram equalization, to improve the accuracy of subsequent processing. To meet the system's scalability requirements, a Linux operating system [29-30] is ported to the ARM, and an Ethernet connection is configured to facilitate peripheral expansion. To achieve hardware acceleration, Xilinx's DPU module is called to improve the efficiency and performance of image processing. Furthermore, the system should possess long-term stability. Figure 2.1 shows the schematic diagram of the overall solution.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/152049219/01_8381eae3658a4486aa1a2399af6ebc6f.png)2.2 Monitoring System Hardware D --- ## Design and Implementation of a Four-Channel Ultrasonic Flowmeter Based on the ZYNQ Platform - URL: https://intl.sienovo.cn/blog/152048939 - Date: 2025-09-24 - Tags: #fpga开发, #人工智能, #arm开发, #分布式, #运维 **0 Introduction** In modern industrial production, the precise measurement of fluid flow is a critical link in ensuring efficient, safe, and reliable production processes. Whether in petrochemicals, natural gas transportation, or daily water management, high-precision, high-reliability flow measurement equipment is required. Ultrasonic flowmeters, with advantages such as non-invasive measurement, high precision, and wide turndown ratio, have been widely applied in the field of fluid flow monitoring and are gradually replacing traditional electromagnetic, differential pressure, and impeller flowmeters, becoming a key and hot research topic for flowmeters both domestically and internationally \[1–4\]. However, traditional ultrasonic flowmeter systems, such as solutions based on microcontrollers or combinations of microcontrollers and Field Programmable Gate Arrays (FPGAs), expose limitations such as insufficient data processing capability, restricted real-time performance, and complex --- ## RK3568+FPGA Real-time Control and Precision Data Acquisition Solution - URL: https://intl.sienovo.cn/blog/151997454 - Date: 2025-09-23 - Tags: #fpga开发 The RK3568 + FPGA solution demonstrates significant technical advantages in real-time control and precision data acquisition. Its core capabilities and typical applications are as follows: #### I. Real-time Control Technology 1. ‌**Low-Latency Architecture**‌ Adopts an Asymmetric Multi-Processing (AMP) architecture, where the main core runs a Linux system for global scheduling, and slave cores handle urgent tasks via RTOS/bare-metal programs. End-to-end communication latency is as low as 4μs, suitable for demanding scenarios such as robotic arm control13. FPGA achieves hardware-level response through GPIO interrupts and DMA technology, reducing CPU load and improving multi-channel AD acquisition efficiency13. 2. ‌**Heterogeneous Computing Optimization**‌ FPGA interacts directly with RK3568 memory via DMA, supporting real-time processing of high-precision sensor data, with multi-channel AD synchronous sampling accuracy reaching 16-bit/1MSPS13. Combined with the RK3 --- ## RK3588+MCU Robot Controller Solution - URL: https://intl.sienovo.cn/blog/151997311 - Date: 2025-09-23 - Tags: #单片机, #机器人, #嵌入式硬件 The following is a detailed analysis of a robot controller solution based on RK3588 + MCU, combining high-performance computing with real-time control requirements: #### I. Core Hardware Architecture 1. ‌**RK3588 Main Control Unit**‌ * Features a big.LITTLE architecture with 4x Cortex-A76 (2.4GHz) + 4x Cortex-A55 (2.0GHz) cores, equipped with 6TOPS NPU computing power, supporting real-time inference for AI models like YOLOv5s (49fps@1080p)‌1. * Integrates a Mali-G610 GPU, supporting 4K@120fps display output to meet complex HMI interaction requirements‌2.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/151997311/01_04277d360a854744878a228dc2b19e92.jpeg) 2. ‌**MCU Collaborative Control**‌ * Connects to industrial-grade MCUs like STM32H7 via SPI/I2C interfaces, achieving microsecond-level real-time control (e.g., servo motor PWM output), forming an AMP heterogeneous computing architecture with RK3588‌3. * Typical application: MCU processe --- ## Industrial Automation Control Board Solution Based on RK3576+MCU+FPGA - URL: https://intl.sienovo.cn/blog/151997245 - Date: 2025-09-23 - Tags: #fpga开发 The following is a comprehensive analysis of the industrial automation control board solution based on RK3576+MCU+FPGA, combining heterogeneous computing architecture with real-time control technology:![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/151997245/01_3091736df95b4f3ab96ba31978690c11.jpeg) #### I. Hardware Architecture Design 1. **Heterogeneous Computing Core** * **RK3576 Main Controller**: Quad-core Cortex-A72 (2.3GHz) handles path planning and AI vision tasks; Quad-core Cortex-A53 (2.2GHz) runs multi-sensor fusion algorithms (e.g., IMU/GPS data synchronization); built-in Cortex-M0 hard real-time core achieves microsecond-level PID control (20μs cycle)‌12. * **FPGA Expansion**: Connects FPGA (e.g., Anlogic PGL25G) via PCIe x4 or FlexBus interface to achieve hardware acceleration tasks (e.g., LiDAR point cloud filtering, encoder signal decoding), with a data exchange rate of up to 280MB/s‌34. 2. **Industrial Interface Configuration** --- ## RK3568+MCU Real-time Robotics Solution - URL: https://intl.sienovo.cn/blog/151997143 - Date: 2025-09-23 - Tags: #fpga开发, #arm开发, #人工智能, #嵌入式硬件 The RK3568+MCU robotics solution is a hardware architecture that combines a high-performance processor with a real-time control unit, primarily applied in industrial automation, service robots, and edge computing scenarios. Here are its core features and application analysis: #### I. Hardware Architecture and Performance Advantages 1. **RK3568 Main Control Chip** * Features a quad-core Cortex-A55 architecture (22nm process, 2.0GHz main frequency), integrates Mali-G52 GPU and 0.8TOPS NPU, supporting 4K video encoding/decoding and lightweight AI inference‌1. * Offers rich interface expansion capabilities, including dual Gigabit Ethernet ports, SATA 3.0, PCIe 3.0, etc., to meet multi-sensor access requirements‌12. 2. **MCU Collaborative Control** * Achieves Linux and RTOS/bare-metal collaboration via AMP (Asymmetric Multi-Processing) architecture, where the main core handles complex task scheduling, and the MCU responds to real-time control tasks via GPIO --- ## UAV Flight Control System Design Based on RK3576+FPGA - URL: https://intl.sienovo.cn/blog/151825375 - Date: 2025-09-18 - Tags: #fpga开发, #RK3588, #linux, #rk3568, #无人机 #### UAV Flight Control System Design Based on RK3576+FPGA This solution utilizes a collaborative architecture of the Rockchip RK3576 processor and FPGA, combining heterogeneous computing and real-time control technologies to meet the high dynamic response, multi-sensor fusion, and AI vision processing requirements of UAVs. Here are the core design points:![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/151825375/01_a14b25289d6747fabae4b334ed51f23c.png) * * * #### 1\. ‌**Hardware Architecture Design**‌ * ‌**Heterogeneous Computing Core**‌ * ‌**RK3576**‌: Quad-core Cortex-A72 (2.3GHz) runs path planning algorithms (e.g., A\*, RRT\*), and quad-core Cortex-A53 (2.2GHz) processes IMU/GPS/vision multi-sensor fusion (sampling rate 1kHz)12. * ‌**FPGA Expansion**‌: Connects to FPGA via PCIe x4 or FlexBus interface (e.g., Anlogic, Gowin, or Unisoc series) to achieve hardware acceleration tasks such as LiDAR point cloud filtering and encoder signal decoding (d --- ## RK3588+FPGA-based Drone Flight Control System, Featuring AI Computing Power, FPGA Real-time Capabilities, Powerful Image Processing, and Full Domestic Localization - URL: https://intl.sienovo.cn/blog/151825184 - Date: 2025-09-18 - Tags: #人工智能, #fpga开发, #无人机 The RK3588+FPGA-based drone flight control system combines the AI computing power of ARM processors with the real-time hardware acceleration capabilities of FPGAs, offering significant advantages in flight control, image processing, and communication transmission. Below are the core technical features and application implementations of this solution:![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/151825184/01_b58a3ab39d694acab27ae2effe94899f.png) #### I. Hardware Architecture Design 1. ‌**Main Control Chip Collaboration**‌ * ‌**RK3588**‌: Utilizes an 8nm process with a quad-core A76 + quad-core A55 architecture, integrating 6TOPS NPU computing power. It supports 8K video encoding/decoding and multi-camera input, meeting the demands for flight control computation and AI tasks‌12. * ‌**FPGA**‌: Interconnected with RK3588 via PCIe 3.0, it enables hardware-level signal pre-processing (e.g., DMA acceleration, image stabilization compensation), reducing the --- ## ARM+FPGA+AI Real-time System Solution Based on RK3588 and ZYNQ7045 - URL: https://intl.sienovo.cn/blog/151825054 - Date: 2025-09-18 - Tags: #嵌入式硬件, #arm开发, #人工智能, #fpga开发 The ARM+FPGA+AI real-time system solution based on RK3588 and ZYNQ7045 combines the high computing power of Rockchip's flagship processor with the hardware acceleration capabilities of FPGA, making it suitable for industrial control, edge computing, and other scenarios. Below are the core architecture and technical features: #### I. Hardware Architecture Design 1. ‌**Main Control Chip Combination**‌ * ‌**RK3588**‌: Utilizes an 8nm process, quad-core A76 + quad-core A55 architecture, integrates a 6TOPS NPU, supports 8K video encoding/decoding and multi-channel camera access13. * ‌**ZYNQ7045**‌: Interconnected with RK3588 via PCIe 3.0, enabling hardware-level signal preprocessing (e.g., DMA acceleration, image enhancement) and reducing the main controller's load24.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/151825054/01_4689830912c744108487838233da2a23.jpeg) 1. ‌**Interface Expansion Capabilities**‌ * Supports industrial interfaces such as USB3.0, RS --- ## RK3588+Fudan Micro JFM7K325T Industrial Control Solution - URL: https://intl.sienovo.cn/blog/151824632 - Date: 2025-09-18 - Tags: #fpga开发 The industrial control board solution, based on the Rockchip RK3588 processor and Fudan Micro JFM7K325T FPGA, combines the high-performance computing of ARM with the real-time processing capabilities of FPGA. It is suitable for industrial applications such as data acquisition, image processing, and AI inference. This solution supports 100% domestic localization, featuring high scalability and low latency. **Core Hardware Configuration** Processor and FPGA Collaborative Architecture‌ RK3588J‌: 8nm process, quad-core Cortex-A76 + quad-core Cortex-A55, 2.0GHz main frequency, built-in 6TOPS NPU, supports 8K video encoding/decoding and multi-channel AI algorithm acceleration. JFM7K325T FPGA‌: Fudan Micro domestic FPGA, compatible with Xilinx XC7K325T, provides 326K logic cells, supports high-speed parallel processing and hardware acceleration.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/151824632/01_0dc0d9f9ca204673879ba8698690e030.jpeg) Interfaces and Expandability‌ C --- ## RK3568-based "Quad-Ethernet Dual-CAN" Industrial Gateway, Empowering Industrial Digital Transformation - URL: https://intl.sienovo.cn/blog/151332145 - Date: 2025-09-08 - Tags: #RK3588, #linux, #Codesys, #RK3568 In the context of growing demands for Industrial Internet of Things (IIoT) and edge computing, stable and reliable network connectivity and fieldbus communication capabilities are the core value of industrial gateways. Incons Industrial Control, a company deeply rooted in industrial computing for many years, continuously optimizes its product line to meet the demanding requirements of industrial scenarios. Breaking through the network bottlenecks of traditional gateways, it provides **four independent Gigabit Ethernet ports** (each with Speed/Link LED indicators). This not only significantly enhances data throughput and meets the needs of multi-device, high-bandwidth parallel access, but also allows for flexible deployment of complex topologies such as network redundancy and VLAN partitioning, ensuring uninterrupted critical business communication.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/151332145/01_d28b0533a9664039a602f2dc5b56f773.png) **02** **2 Isolated CAN --- ## High-Performance Real-time Industrial PC with 6 LAN, 8 Serial, 16 I/O, Empowering Comprehensive Upgrades for Industrial Automation/Energy Storage, Supporting Passive and Active Cooling - URL: https://intl.sienovo.cn/blog/151331745 - Date: 2025-09-08 - Tags: #自动化, #运维 The rapid development in fields such as industrial automation, smart energy storage, and robotic systems places higher demands on edge computing devices: powerful computing capability, rich connectivity interfaces, excellent stability, and efficient heat dissipation are all indispensable. **01** **Powerful Core, Stable Support** Equipped with **Intel® 11th Gen Tiger Lake Core Processors**, adopting a System-on-Chip (SoC) design, providing powerful data processing capabilities. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/151331745/01_ef60ffe3c793415f93b0697f6a2d93c6.jpeg) **02** **Enhanced Multi-tasking Efficiency** **Dual-channel DDR4 memory architecture** supports capacity expansion via SODIMM slots, significantly enhancing the fluidity of multi-tasking and large application operation, easily handling complex computing tasks such as industrial robot path planning, real-time monitoring of automation systems, or energy storage power station data analysis. Equip --- ## x86-based Six-Port Network, Eight-USB High-Precision Machine Vision System - URL: https://intl.sienovo.cn/blog/151331421 - Date: 2025-09-08 - Tags: #数码相机, #fpga开发, #rk3568, #codesys, #RK3588, #linux In the precision inspection segment of automated production lines, machine vision systems place extremely high demands on the core industrial PC: **high-speed data processing, stable multi-device connectivity, and adaptability to harsh environments**. **I. Application Requirements for Precision Manufacturing Vision Inspection Systems** ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/151331421/01_e43413898e1f44eecdac80bb8b542be6.jpeg) 1 **Core Requirements** **·** High-speed processing of images simultaneously acquired by multiple high-resolution industrial cameras. **·** Running complex algorithms (e.g., dimension measurement, surface scratch/stain detection, character recognition) and precisely identifying defects. **·** 7x24 continuous operation in high or low temperature environments, and metal dust/oil contamination environments. **·** Real-time aggregation of inspection results and upload to the system, supporting rapid switching for mixed-model product ins --- ## RK3568/RK3588-Based Power Gateway with Fully Isolated Serial Ports and Multi-Power Protocol Access for Monitoring and O&M of New Energy Power Stations (Solar PV, Wind Power, etc.) - URL: https://intl.sienovo.cn/blog/151330935 - Date: 2025-09-08 - Tags: #分布式, #运维 Driven by the "Dual Carbon" strategy, the scale of distributed photovoltaic (PV) applications continues to expand. Efficient, stable, and intelligent operation and maintenance (O&M) management is crucial for ensuring both revenue and safety. RK3568 Version: **·****Wide Operating Temperature Range (-20°C ~ 70°C)****:** Easily handles harsh environments such as outdoor cabinets and rooftops, ensuring 24/7 uninterrupted data acquisition. **·****4 Isolated Serial Ports**** (RS232/485 optional, with isolation)****:** Flexibly adapts to Modbus RTU/Modbus TCP protocols of various inverter brands, as well as serial communication for smart meters and temperature/humidity sensors. **·****4 Isolated Digital Inputs (DI):** Accurately collects critical switch signals, such as combiner box circuit breaker status and access control switch signals. **·****2 Isolated Digital Outputs (DO):** Enables remote control (e.g., starting/stopping ventilation equipment, emergency disconnection of faulty eq --- ## Applications of RK3568-based Multi-Network, Multi-Serial (6 Network + 6 Serial + 2 Optical) 1U/2U Rackmount Server in Energy Storage and Electric Power - URL: https://intl.sienovo.cn/blog/151330820 - Date: 2025-09-08 - Tags: #网络, #fpga开发, #RK3588, #linux, #rk3568 As global energy transition accelerates, energy storage power stations and substations, as critical nodes in power systems, are rapidly evolving towards intelligence and digitalization. These scenarios place extremely high demands on the computing performance, communication capabilities, and reliability of underlying hardware devices. **Equipped with 6 Gigabit Ethernet ports (RJ45 form factor)**, it provides ample physical interfaces for the multi-layer network architectures of energy storage power stations and substations. In typical applications, these network ports can be used for: **·** Connecting intelligent devices such as station protection devices and measurement and control devices for real-time data acquisition; **·** Accessing the dispatch data network and station control layer network to achieve data interaction with the control center; **·** Building redundant network links to enhance system communication reliability. **The multi-port design avoids the cost and space --- ## Application of RK3568/RK3588+FPGA Power Gateway in Environmental Monitoring and Energy Storage Energy Management Systems - URL: https://intl.sienovo.cn/blog/150555658 - Date: 2025-08-20 - Tags: #fpga开发, #RK3588, #linux Serial servers play a crucial role in industrial data acquisition by connecting traditional devices to IP networks. This article will introduce the physical interface configuration of a serial server based on the Rockchip RK3588 processor (8nm, 4xA76+4xA55) and objectively discuss its applicable scenarios in Energy Storage Management Systems (EMS) and Environmental Monitoring.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150555658/01_b4ae0d8fcc304bb0a2e6685106d0c6f1.jpeg) I. Core Hardware Specifications Overview Processor: Rockchip RK3588 Operating System: Optional Open-source EulerOS, Kylin, KylinSec, Ubuntu Memory/Storage: 8GB / 128GB eMMC NPU: 6TOPS computing power (supports multiple precisions) II. Configuration and Application The interface design of this serial server is mainly divided into front and rear sections: Front Interfaces (Device Access Side): Serial Ports: 16-channel RS485 (each with an indicator light). Digital I/O (DIO): 12-channel DI (Input) --- ## RK3568-based Solution for Energy Storage and Environmental Monitoring Controllers - URL: https://intl.sienovo.cn/blog/150555556 - Date: 2025-08-20 - Tags: #arm开发, #fpga开发, #人工智能 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150555556/01_b6666b43fd444e7ca23a79c6ac308497.png) Energy Storage and Environmental Monitoring Controllers are primarily applied in various power/new energy scenarios such as power equipment monitoring, photovoltaics, energy storage, charging piles, wind power generation systems, microgrid scenarios, and virtual power plants.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150555556/02_1bb8b4cc43034d20a1543dedd8eaac10.png) Features 1. Multi-interface Support: The device is equipped with 4 external RJ45 network ports, featuring switch functionality and supporting network communication. Additionally, it provides multiple DI inputs, DO dry contact outputs, AI inputs, and AO outputs to meet the connection requirements of various devices. 2. Strong Communication Capability: This controller has a built-in 4G communication module, with an optional 5G module. 3. Multiple Storage Methods: To ensure data security a --- ## Energy Storage EMS IoT Platform + Energy Storage Coordination Controller Solution - URL: https://intl.sienovo.cn/blog/150555297 - Date: 2025-08-20 - Tags: #fpga开发, #arm开发, #人工智能, #嵌入式硬件 **Background** Energy is a vital support for modern society. However, the finite nature of traditional energy resources and their environmental impact have sparked widespread attention to renewable energy. Renewable energy sources (such as solar and wind power) are characterized by volatility and intermittency, which necessitates an effective energy storage technology to balance energy supply and demand and improve energy utilization efficiency. Energy Storage EMS emerged as a response, an energy management system based on advanced technology, designed to optimize and manage energy storage equipment to achieve efficient energy storage and release.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150555297/01_013492c5b113427783953365ee3ac6f3.jpeg)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150555297/02_1146042579e647d29aa59dd09119f253.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150555297/03_c5a660a7da104b98a15bf41383d14241.jpeg) **En --- ## RK3568/J6412-based EMU Multi-port Control Host, Empowering Energy Storage Industrial Interconnection Management and O&M - URL: https://intl.sienovo.cn/blog/150552283 - Date: 2025-08-20 - Tags: #运维, #嵌入式硬件, #arm开发, #人工智能, #fpga开发 In the construction of China's new power system, the installed capacity of renewable energy generation has been increasing year by year. However, the volatile and intermittent nature of new energy sources like solar and wind power poses challenges to the stable supply of electricity to the grid. To promote the integration of new energy generation and ensure the safe operation of the power grid, energy storage has become a crucial component. 1. Customer Application Requirements Distributed energy storage technology is increasingly applied in the industrial and commercial sectors, playing a significant role in smoothing renewable energy output, peak shaving and valley filling, balancing grid load, improving energy utilization efficiency, and reducing energy consumption. A certain energy technology company in Shenzhen needs to build a photovoltaic (PV) integrated energy storage project, specifically a 100KW/200KWh accompanying energy storage system, in a certain location. The EMS (Ener --- ## Power Communication Gateway based on RK3568 and LikwiseOS - URL: https://intl.sienovo.cn/blog/150552161 - Date: 2025-08-20 - Tags: #rk3568, #codesys The power communication gateway solution built on the RK3568 processor and LikwiseOS needs to be designed by combining hardware capabilities and system characteristics. The following is a comprehensive feasible solution framework (‌**Note**‌: Search results do not explicitly mention official support for RK3568 by LikwiseOS. This solution is based on RK3568's compatibility with mainstream Linux systems, assuming LikwiseOS can be adapted):![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150552161/01_0a5ceb4b45534e5888d41407ede8a2e9.jpeg) * * * #### ‌**I. Core Hardware Configuration**‌ As the main control chip, RK3568 provides the following capabilities: * ‌**Processor Performance**‌: Quad-core Cortex-A55 architecture, clock speed up to 2.0GHz, integrated Mali-G52 GPU and 0.8 TOPS NPU, supporting edge computing and lightweight AI inference58. * ‌**Interface Expansion**‌: * ‌**Networking**‌: Dual Gigabit Ethernet ports + Dual Fast Ethernet ports, supporting 4G/5G --- ## Predictive Maintenance + Intelligent Optimization: RK3568+FPGA Solution in Energy Storage Applications - URL: https://intl.sienovo.cn/blog/150549484 - Date: 2025-08-20 - Tags: #fpga开发, #rk3568, #codesys In the energy storage industry, the RK3568 + FPGA solution significantly enhances system reliability and economic efficiency through predictive maintenance and intelligent optimization technologies. This solution adopts a heterogeneous architecture (FPGA handles high-speed signal acquisition, while RK3568 is responsible for strategy computation and communication management), achieving microsecond-level response and precise control.‌26 #### I. Predictive Maintenance Applications * ‌**Health State Modeling**‌: Builds a digital twin model of equipment based on LSTM neural networks, predicting battery degradation trends (error <3%) and component failures (localization accuracy >95%), implementing a multi-level threshold early warning mechanism (Normal/Warning/Fault).‌2 * ‌**Fault Diagnosis and Protection**‌: Supports shadow detection, combiner box arc fault early warning, etc., combined with historical data analysis, extends equipment lifespan by 35% and reduces fault response time --- ## RK3568-Based Energy Storage EMU, Energy Storage Coordination Controller Solution - URL: https://intl.sienovo.cn/blog/150548894 - Date: 2025-08-20 - Tags: #fpga开发, #rk3568 Professionally designed for energy management scenarios in energy storage and microgrids, this solution integrates Ethernet ports, CAN, RS485, RS232, and DI/DO. It fully meets the data acquisition and I/O control requirements for BMS, PCS, diesel generators, and PV inverters. Meanwhile, the software layer integrates standard acquisition protocols and is compatible with interfaces from various mainstream equipment manufacturers, making it widely applicable in industrial and commercial energy storage, residential energy storage, and microgrid control scenarios.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150548894/01_7f5ff301534f46d49f861c80ade2fd04.png) Scenario Introduction The EMU Energy Management and Monitoring Controller is an innovative technology with outstanding advantages, specifically tailored for energy storage and microgrid scenarios. Compared to multiple traditional devices such as 4G routers, 5G routers, and PLC controllers, the EMU enables integrated ma --- ## RK3588-based Microgrid Coordination Controller: Enabling Intelligent Regulation and Optimized Operation of Distributed Energy Resources - URL: https://intl.sienovo.cn/blog/150470961 - Date: 2025-08-17 - Tags: #分布式, #能源, #性能优化, #fpga开发 The Microgrid Coordination Controller solution achieves intelligent coordination and optimized operation of distributed energy resources (DERs) such as photovoltaic (PV), energy storage, and wind power equipment by integrating advanced algorithms and real-time data technology. Key features include: * ‌**Coordinated Optimization Scheduling**‌: Utilizes Model Predictive Control (MPC) to dynamically adjust PV output, energy storage charge/discharge strategies, and load demand. Scheduling is optimized based on electricity price signals and real-time data to maximize renewable energy consumption and reduce electricity costs‌2. * ‌**Anti-Reverse Power Flow Control and Local Consumption**‌: PV power prioritizes meeting local loads, with surplus power mandatorily allocated to energy storage charging or adjustable loads to prevent grid feed-in and curtailment. Combined with time-of-use (TOU) electricity pricing mechanisms (e.g., a two-charge, two-discharge strategy), it improves system s --- ## Microgrid Intelligent PV-Storage Coordinated Controller Solution - URL: https://intl.sienovo.cn/blog/150470906 - Date: 2025-08-17 - Tags: #人工智能, #服务器, #运维 #### Details of the Microgrid Intelligent PV-Storage Coordinated Project The Microgrid Intelligent PV-Storage Coordinated Project integrates photovoltaic, energy storage, and intelligent control technologies to achieve efficient energy dispatch and stable grid support. The key details are as follows: * ‌**System Architecture and Components**‌: The project typically includes distributed PV (e.g., rooftop or carport PV), energy storage battery systems (e.g., liquid-cooled or containerized energy storage), and charging facilities. For example, one case adopted a 200kW rooftop PV system paired with a 100kW/200kWh containerized energy storage system, which uses an intelligent strategy server (e.g., CET-7320) to coordinate equipment operation, achieving integrated management of source, grid, load, and storage. The platform supports real-time monitoring of PV generation, energy storage charge/discharge status, and charging pile data, ensuring local consumption of electricity and reducing --- ## Energy Storage Coordinated Controller Solution Based on DSP+ARM+FPGA Architecture, Supporting Full Domestic Localization - URL: https://intl.sienovo.cn/blog/150470757 - Date: 2025-08-17 - Tags: #arm开发, #fpga开发, #架构 The Energy Storage Coordinated Controller Solution, based on a DSP+ARM+FPGA architecture, achieves high-performance control and real-time response through the collaborative operation of multi-core heterogeneous processors. Its core design and functions are as follows: * * * #### I. Hardware Architecture Design 1. **Multi-core Heterogeneous Division of Labor** * **ARM**: Runs the Linux system, responsible for strategy computation (e.g., charge/discharge scheduling, economic optimization) and communication protocol stack management‌13. * **DSP**: Processes fast control algorithms (e.g., primary frequency regulation/dynamic reactive power voltage regulation), achieving microsecond-level response (frequency regulation action time ≤20ms)‌35. * **FPGA**: Executes high-speed signal acquisition (1MSPS sampling rate) and real-time logic control, supporting optocoupler-isolated signal channels with anti-interference capability up to 4kV/2kV (common mode/differential m --- ## FPGA-based Thermocouple Temperature Measurement Data Acquisition System, a Replacement for NI Products (Part 3) Testing - URL: https://intl.sienovo.cn/blog/150225285 - Date: 2025-08-11 - Tags: #fpga开发, #arm开发, #人工智能, #嵌入式硬件 High-speed Modular Data Acquisition System Lower-level Machine Function Testing 4.2.1 Experimental Platform Setup Since the system is designed with modularity, it is necessary to verify the functionality of each module before conducting the overall experiment. The feasibility of the lower-level machine software was tested in the previous section. As introduced in previous sections, the system is also equipped with a front-end signal processing module, which is divided into two parts: power supply and amplification-filtering. To verify correct functionality, the signal processing module needs to be tested. Testing the power supply module is to verify whether the power supply module generates voltage correctly; testing the amplification-filtering is to ensure that the designed functions can be correctly implemented. Finally, this part of the test is connected with the previous section and connected to the host PC for packet capture and overall testing, to verify the overall functiona --- ## FPGA-based Thermocouple Temperature Measurement Data Acquisition System, an Alternative to NI Products (Part 2) Overall Design Scheme - URL: https://intl.sienovo.cn/blog/150225081 - Date: 2025-08-11 - Tags: #fpga开发, #嵌入式硬件, #arm开发, #人工智能 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150225081/01_d6f6f8bb62984d5eaa4b422c8b04f7c0.png)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/150225081/02_5dab1f24065848dbbdbbe51d4f0091d0.png) In 2024, Ren Yongfeng et al. from North University of China addressed the requirements for equipment temperature measurement in flight tests and designed a high-precision multi-channel temperature acquisition device suitable for flight tests. The system block diagram is shown in Figure 1.18 \[32\]. The system uses an FPGA to build the signal acquisition and processing system, employs AD8227 and AD590 for signal conditioning and cold junction compensation, and uses AD7667 to sample the thermocouple signals. The system transmits 16 channels of temperature signals via the standard RS422 protocol and applies nonlinear correction to the output through linear fitting, thereby improving the system's accuracy and stability. Test results indicate that the temperature measur --- ## FPGA-Based Thermocouple Temperature Measurement Data Acquisition System, Replacing NI Products (Part 1) Current Status of FPGA Temperature Measurement Research - URL: https://intl.sienovo.cn/blog/150224930 - Date: 2025-08-11 - Tags: #网络, #运维, #性能优化, #fpga开发 Thin-film thermocouples, as sensors widely used in temperature measurement, have found extensive applications in the measurement field due to their superior performance and stability. With the rapid development of industrial automation and precision measurement technologies, the demand for high-speed data acquisition systems in various engineering applications is continuously increasing. The main drawback of existing solutions lies in their long sampling periods, making them unsuitable for capturing transient temperature data from thin-film thermocouples. Given that thin-film thermocouples have response times in the nanosecond range, existing data acquisition instruments (cards) cannot meet the sampling requirements for rapidly changing temperature signals. To address the need for high-speed temperature data acquisition, this paper designs a high-speed modular data acquisition system for thin-film thermocouples based on Field Programmable Gate Arrays (FPGAs). This system can efficient --- ## Design of a Sonar Data Acquisition System Based on Zynq ARM+FPGA - URL: https://intl.sienovo.cn/blog/149945363 - Date: 2025-08-05 - Tags: #arm开发, #RK3568, #Codesys Currently, the development of sonar data acquisition systems generally involves selecting microprocessors or microcontrollers, Field Programmable Gate Arrays (FPGAs), or Digital Signal Processors (DSPs) as the main control chips. Wang Min et al. \[8\] used a DSP running the VxWorks operating system to implement a Transmission Control Protocol/Internet Protocol (TCP/IP) network protocol stack, capable of real-time transmission of sonar system acquired data and computation results back to a computer. Zhang Yanpin \[9\] designed an underwater acoustic signal acquisition and processing platform based on the OMAP-L138 chip, which achieved continuous acquisition, processing, storage, and transmission of underwater acoustic signals, and enabled the upload of underwater acoustic data stored on a secure digital card via a Light Weight IP (LwIP) network protocol stack. Rong Zhiyuan \[10\] combined the high-speed parallel processing capabilities of FPGAs with the flexible process control capabil --- ## Design of an ARM+FPGA-based Multi-channel Ultrasonic Signal Acquisition and Transmission System - URL: https://intl.sienovo.cn/blog/149944719 - Date: 2025-08-05 - Tags: #fpga开发, #RK3588, #linux Addressing the challenges faced by ultrasonic signal acquisition systems in multi-channel synchronous acquisition and high-speed data transmission, an 8-channel ultrasonic signal synchronous acquisition and transmission system based on FPGA was designed and implemented. The system uses an FPGA as the main control chip, ADI's AD9279 as the analog front-end and analog-to-digital converter chip for 8-channel ultrasonic signal synchronous acquisition, and achieves data buffering and high-speed data transmission via DDR3 SDRAM and USB 3.0. Experimental results show that the system performs well in multi-channel ultrasonic signal synchronous acquisition, data buffering, and high-speed data transmission, providing a reliable hardware platform for synchronous acquisition and high-speed transmission of multi-channel ultrasonic signals. 0 Introduction In recent years, ultrasonic testing technology has been widely applied in fields such as medical diagnosis, industrial non-destructive testing, --- ## Design of a PXIe Bus-Based Multi-Channel Parallel Data Acquisition System - URL: https://intl.sienovo.cn/blog/149944495 - Date: 2025-08-05 - Tags: #stm32, #codesys, #rk3568, #A40I, #人工智能 Addressing the limitations and shortcomings of traditional data acquisition cards in terms of channel count, parallel data processing capability, and system real-time response, a PXIe bus-based multi-channel parallel data acquisition system was designed, using Xilinx's XC7A100T FPGA chip as the core processor. This system includes a data acquisition circuit, PXIe interface signal module, FIFO storage module, and power conversion circuit, among others. Tested results show that the system achieves a 200 KS/s sampling rate and multi-channel parallel data acquisition capabilities. It can upload data in real-time to the host computer for display via the PXIe bus. This system has high practical value and is significant for realizing the domestic production of low-cost PXIe acquisition cards.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/149944495/01_38baa7bcb4ba44e5bffea31ec406bb8d.jpeg) Data acquisition technology is a key technology in the field of information technology, i --- ## Design of an ARM+FPGA-Based Grating Data Acquisition Card - URL: https://intl.sienovo.cn/blog/149944396 - Date: 2025-08-05 - Tags: #fpga开发, #stm32, #rk3568 To ensure the accuracy of rotational inertia measurement, this paper designs a novel and advanced grating data acquisition card system using an FPGA chip and the Verilog HDL programming language. First, based on the overall system architecture design, multiple circuits such as the grating signal pre-processing circuit, FIFO data buffer circuit, and FPGA functional circuit are designed. Second, after completing the system's fabrication and debugging, equidistant and isochronous experiments are conducted on the system's grating signals. The results show that the FPGA-based grating data acquisition card designed in this paper features high accuracy, high stability, fast response speed, and stable and normal equidistant and isochronous sampling functions, ensuring the integrity and security of grating data, and meeting safe and reliable design standards. This research can provide important system support for precise rotational inertia measurement in the future. As a new type of sensor, g --- ## Design of a ZYNQ-based Four-Channel Data Acquisition System - URL: https://intl.sienovo.cn/blog/149935742 - Date: 2025-08-05 - Tags: #网络, #人工智能, #服务器, #运维 Addressing the common issues of high cost and insufficient integration in existing receiver equipment, a low-cost, highly integrated four-channel ADS-B receiver is designed. This device is the first in the industry to integrate low-cost real-time signal acquisition, on-board multi-band ADS-B real-time decoding, and other functions into a single four-channel miniature RF receiver. The device uses a ZYNQ-7000 series chip as the main control chip, and the design includes an RF front-end receiver circuit module, a signal acquisition circuit module, a high-speed, large-capacity data storage module, etc., to achieve high-speed sampling and processing of target signals such as ADS-B. Test results show that the receiver can successfully receive and demodulate ADS-B long message signals, providing a low-cost, low-power overall solution for high-performance data acquisition and real-time signal processing. Introduction With the rapid development of the aviation industry, the issue of airspace --- ## ZYNQ + ADC-based Multi-channel Ship Noise Acquisition System - URL: https://intl.sienovo.cn/blog/149935632 - Date: 2025-08-05 - Tags: #fpga开发, #人工智能, #arm开发, #嵌入式硬件 With the advancement of electronic communications and automation technologies across various sectors, ships, while ensuring fundamental maritime safety and transportation security, are increasingly emphasizing the provision of a more comfortable and healthier navigation environment for crew and passengers. Against this backdrop, effective acquisition and control of ship noise have become an indispensable path to address these concerns. This paper proposes a multi-channel ship noise acquisition system based on the ZYNQ platform, tailored to the demands of ship automation and intelligence. The ZYNQ architecture, combining the collaborative capabilities of its soft and hard cores, high-speed data processing, compact size, and low power consumption, is highly suitable for such applications. This system can achieve real-time, high-speed, and accurate acquisition of ship noise, thereby providing reliable data support for subsequent noise processing and control, enhancing ship navigation safe --- ## ZYNQ-based Strain and Temperature Synchronous Acquisition System for Engine and Gas Turbine Testing (Part 2): Acquisition System Software and Hardware Design - URL: https://intl.sienovo.cn/blog/149902159 - Date: 2025-08-04 - Tags: #fpga开发, #arm开发, #人工智能 Acquisition System Hardware Design 3.1 Control Board Circuit Design 3.1.1 Main Control Chip Selection When selecting the main control chip for the acquisition system, the following factors should be comprehensively considered to ensure it meets system requirements: (1) Processing Capability and Performance: Based on task requirements, the main control chip needs to possess sufficient computing resources to handle the processing load and computational demands of the data acquisition system. To meet these needs, factors such as the number and type of processor cores, clock speed, and instruction set must be fully considered during selection. Given potential future system upgrade and expansion requirements, choosing a high-performance processor can prevent performance bottlenecks when adding new features or processing more data. (2) Interface Compatibility: The main control chip needs to support various physical and logical interfaces required for connection and communication, ensur --- ## ZYNQ-Based Strain and Temperature Synchronous Acquisition System for Engine and Gas Turbine Testing (Part 1) Hardware System Design - URL: https://intl.sienovo.cn/blog/149901451 - Date: 2025-08-04 - Tags: #单片机, #嵌入式硬件 Aero-engines and gas turbines hold extremely important positions in the industrial sector. As one of the critical components of aero-engines and gas turbines, turbine blades face harsh environments such as high temperatures, strong airflow, and intense vibrations during operation. These conditions can easily lead to problems like fatigue fracture, thermal damage, and wear. However, in high-speed rotating equipment, traditional contact-based measurement can no longer meet the requirements. Therefore, to ensure the safe operation and performance optimization of the equipment, developing a wireless strain/temperature acquisition system suitable for rotating environments is crucial. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/149901451/01_50cd725749844862bfc3cc052536cd3c.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/149901451/02_38c006ae047a4045b9b61629c2874837.png) A synchronous acquisition system for strain and temperature parameters is specifical --- ## Rockchip RK3568J +FPGA Edge AI System and Energy Storage Gateway - URL: https://intl.sienovo.cn/blog/149835296 - Date: 2025-08-01 - Tags: #服务器, #运维, #性能优化, #fpga开发 Here is an analysis of the core technical solutions and applications for the Rockchip RK3568J Edge AI System and Energy Storage Gateway: #### I. Hardware Architecture and Performance Characteristics 1. ‌**Processor Configuration**‌ Equipped with a quad-core Cortex-A55 CPU@2.0GHz, integrated Mali-G52 GPU, and a 1TOPS NPU unit, supporting localized deployment of deep learning models23. 2. ‌**Industrial-Grade Reliability**‌ Undergoes rigorous EMC/EMI testing, supports wide temperature operation from -40℃ to 85℃, meeting the demands of harsh environments such as outdoor energy storage cabinets37. 3. ‌**Interface Expansion Capability**‌ * Communication Interfaces: Standard configuration includes 3× Gigabit Ethernet ports (supporting TSN), 8× isolated RS485, CAN bus, 4G/5G module slots35 * Control Interfaces: Supports multiple PWM outputs and high-speed pulse counting, compatible with industrial sensors and actuators3 Technical Specifications: * --- ## Application Scenarios for Power Communication Management Units Based on RK3568/RK3588/ J6412/Phytium FT2000? - URL: https://intl.sienovo.cn/blog/149769428 - Date: 2025-07-30 - Tags: #网络, #人工智能 A Power Communication Management Unit (also known as a Communication Management Unit or DPU) is a core communication hub device in power systems and related fields. Its typical application scenarios include: #### ⚡ I. Core Scenarios in Power Systems 1. ‌**Substations**‌ * Serves as a data relay hub between on-site monitoring equipment (such as relay protection devices, smart meters, RTUs) and the upper-level dispatch center, enabling remote signaling, remote measurement, remote control, and remote adjustment functions, supporting fault location in seconds and remote control of circuit breaker operations‌12. * In unmanned substations, it independently completes data acquisition and forwards it to the dispatch center via dual channels, ensuring stable operation of remote sites‌58. 2. ‌**Power Plants and Centralized Control Stations**‌ * Applied in thermal power, hydropower, and photovoltaic power stations, integrating data from generation units into the m --- ## Hardware and Software Composition and Solutions for Energy Coordination Controllers - URL: https://intl.sienovo.cn/blog/149549120 - Date: 2025-07-22 - Tags: #fpga开发, #人工智能, #arm开发, #嵌入式硬件 The hardware and software composition of an energy storage coordination controller is as follows: * * * #### I. Hardware Composition 1. **Core Processor Unit** * **Multi-core Heterogeneous Architecture**: Utilizes a combination of ARM (for strategic computation) + FPGA (for real-time signal processing) + DSP/ADC (for high-precision sampling), supporting millisecond-level response and parallel computing‌12. * **Domestic Solution**: Supports fully domestic chips (e.g., ARM Cortex-A55 multi-core processors) to ensure supply chain security‌12. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/149549120/01_e8ab0f5c1a4a4a1f83761cfb892d7ac9.jpeg) 2. **Data Acquisition Module** * **High-Precision Sampling Circuit**: 16-bit AD acquisition chip (sampling rate ≥1MSPS), voltage/current measurement error <0.5%, supporting 24 AC channels and 16 DC channels‌12. * **Isolation and Protection Design**: Key signal channels use optocoupler isolation (in --- ## How to Integrate Grating Sensors into an FPGA+ARM System? - URL: https://intl.sienovo.cn/blog/149329727 - Date: 2025-07-14 - Tags: #fpga开发, #arm开发, #人工智能, #嵌入式硬件, #服务器 Integrating grating sensors into an FPGA+ARM system requires hardware co-design and software architecture optimization to achieve high-precision real-time measurement. The core process is as follows: * * * #### 🔌 ‌**I. Hardware Interface Design**‌ 1. ‌**Signal Conditioning Circuit**‌ * Grating sensors output quadrature pulses (A/B phases) or four-channel sine signals. Differential receiver circuits must be designed to suppress common-mode noise, and shielded twisted-pair cables should be used for transmission to reduce electromagnetic interference. * For sine signals, configure high-speed ADCs like AD9280 (125MSPS) to digitize the signals via FPGA. 2. ‌**FPGA Decoding Module**‌ * Deploy hardware decoding logic in the FPGA: * Quadrature frequency multiplication subdivision module: Resolution is increased by 4 times through dual-edge triggering (e.g., 0.5μm → 0.125μm). * Direction determination circuit: Samples the B-phase level on t --- ## Grating Sensor, FPGA, and ARM-Based Measurement and Control Solution - URL: https://intl.sienovo.cn/blog/149329606 - Date: 2025-07-14 - Tags: #fpga开发, #arm开发, #人工智能, #嵌入式硬件 A measurement and control solution combining grating sensors with FPGA and ARM achieves high precision, real-time performance, and multi-scenario adaptability through hardware collaborative division of labor:![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/149329606/01_16caef4cae41494b9f59bf6353c452d5.jpeg) * * * #### ⚙️ ‌**I. System Architecture and Division of Labor**‌ 1. ‌**Sensing Layer (Grating Sensor)**‌ * Utilizes grating scales to output quadrature pulse signals, achieving a resolution of 0.5μm and an accuracy of ±1μm. It supports non-contact measurement, offers strong electromagnetic interference resistance, and is suitable for high-speed motion scenarios17. * Supports multi-channel synchronous acquisition (e.g., X/Y dual-axis or circular arrangement), realizing displacement-to-electrical signal conversion based on the Moiré fringe principle28. 2. ‌**Signal Processing Layer (FPGA)**‌ * ‌**Real-time Decoding**‌: Performs quadrature frequency --- ## PCIe 5.0 Switch Board Solution, Supporting Hygon, Loongson, and More, as a Broadcom Alternative - URL: https://intl.sienovo.cn/blog/149193840 - Date: 2025-07-08 - Tags: #服务器, #运维, #性能优化, #fpga开发 * ****Physical Product Image**** * ****Core Hardware Configuration**** ****1. Controller Chip****‌ * Utilizes the domestic Zhongxingwei 63104 controller chip, supporting PCIe transfer rates of 2.5GT/s, 5GT/s, 8GT/s, 16GT/s, and 32GT/s, with support for 96+8 lanes. It supports 6 x16 groups and 1 x8 group, with each group supporting 1 to 8 ports. The x16 groups support x16, x8, x4, x2 ports; the x8 group supports x8, x4, x2, x1 ports. * Basic Mode: Extends PCIe interfaces and supports multi-level expansion, as shown in the figure below. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/149193840/01_d6faeef9a6684508b95f981a771f4c98.jpeg) * NT Mode: Multiple PCIe domains are interconnected, supporting NTB and DMA features, as shown in the figure below. * ‌P2P Mode: Supports data transfer between any DPs, effectively increasing transmission bandwidth and reducing transmission latency. * Supports non-blocking crossbar architecture. * Integrates SM2/SM3/SM4 e --- ## Domestic Replacement for 89104 PCIe Switch Chip - High-Performance PCIe 5.0 Domestic AI Server Expansion, Supporting Hygon/Loongson/Phytium, etc. - URL: https://intl.sienovo.cn/blog/149191934 - Date: 2025-07-08 - Tags: #人工智能 Below is a detailed analysis of the high-performance PCIe 5.0 AI server expansion solution for the domestic replacement of the 89104 PCIe Switch chip: * * * #### I. Core Domestic Replacement Chip: TL63104 Controller 1. ‌**Technical Specifications**‌ * Supports full PCIe 5.0 speed (32 GT/s), offering 96+8 Lanes configuration, with an aggregated bidirectional bandwidth of up to 128GB/s (x16 mode)1. * Supports multi-mode topologies: * ‌**Basic Mode**‌: Expands PCIe interfaces, supporting multi-level cascading; * ‌**NT Mode**‌: Enables multi-PCIe domain interconnection, supporting NTB and DMA features; * ‌**P2P Mode**‌: Direct transmission between any ports, reducing latency and improving bandwidth utilization19. * Integrates SM2/SM3/SM4 national cryptographic algorithm engines, meeting domestic security requirements1. 2. ‌**Interface Expansion Capability**‌ * Upstream Interface: PCIe 5.0 x16 (gold finger); * Downs --- ## Ultra-Low Power Consumption + Ultra-Small RK3576 Wireless Video Transmission and Ad-Hoc Networking Solution - URL: https://intl.sienovo.cn/blog/149172044 - Date: 2025-07-07 - Tags: #fpga开发, #人工智能, #arm开发, #嵌入式硬件 5G Infrared Thermal Imaging Video Transmission Special Operations Ballistic Helmet / Firefighter Helmet / Traffic Police Helmet / Rescue Helmet 1) 5G All-Network Connectivity – 1080P Transmission 2) HD Night Vision – SONY IMX 385 Image Sensor; Infrared Thermal Imaging – Resolution: 640/384 (optional) 3) Supports RJ-45 Wired Network Port for RTSP Video Output 4) Supports National Standard GB/T28181-2016 Protocol 5) BeiDou / GPS / GLONASS Multi-mode RTD Sub-meter Level Positioning 6) PTT Digital Trunking Intercom for Mutual Communication Among Team Members 7) TF Card Supports Hot-Swapping, Supports 256G Capacity 8) 18650 Replaceable Battery, 8 Hours of Continuous Operation 9) Operating Temperature: -40℃ to 60℃ 10) Broadband Ad-Hoc Networking Base Stations and Terminals, Firefighter Individual Reconnaissance System, Backpack-mounted Visual System, Individual Video Transmission, Rapid Deployment Camera, Dual-Spectrum Fusion Video Transmission Terminal, Wrist-worn Visual Display Terminal, --- ## 【Precision Measurement】ARM+FPGA-based Multi-channel Grating Signal Acquisition Solution - URL: https://intl.sienovo.cn/blog/149149244 - Date: 2025-07-06 - Tags: #fpga开发, #arm开发, #人工智能, #嵌入式硬件, #服务器 Grating sensors, as effective tools for precision mechanical measurement, are widely used in engineering measurements such as linear displacement, angular displacement, velocity, and acceleration. In length measurement, grating micro-displacement sensors can achieve μm-level measurement accuracy and dynamically acquire changes in length, thereby accurately calculating motion velocity and even acceleration. In surface measurement, compared to traditional coordinate measuring machines (CMMs) and profilometers, grating sensors also offer advantages such as dynamic detection of surface shape changes, high precision, and real-time output of surface shape data. Multiplexing technology is widely used in data acquisition. In some distributed systems, using multiplexing technology can reduce the number of I/O ports and improve system integration. Specifically, a multiplexer switch is used to gate multiple signals, connecting the output of the multiplexer switch to the I/O port of the acquisit --- ## RK3588S-based UAV Flight Control Board, Supporting Wireless Video Transmission, Gimbals, and More - URL: https://intl.sienovo.cn/blog/149030715 - Date: 2025-06-30 - Tags: #无人机 The RK3588S-based UAV flight control board offers the following core technical advantages in terms of wireless video transmission and gimbal support: #### I. Hardware Performance Support 1. ‌**Eight-core Processor Architecture**‌ Equipped with 4x Cortex-A76 cores (up to 2.4GHz) + 4x Cortex-A55 cores (up to 1.8GHz), providing real-time flight control computing power to meet multi-task collaborative processing requirements. 2. ‌**6TOPS NPU Computing Power**‌ Integrates a dedicated AI acceleration module, supporting frameworks like TensorFlow/PyTorch, capable of directly running gimbal vision algorithms such as object recognition and tracking. 3. ‌**8K Video Encoding and Decoding Capability**‌ Supports H.265 hardware encoding, enabling low-power processing of high-definition video streams, laying the foundation for the video transmission system. #### II. Key Technologies for Wireless Video Transmission 1. ‌**Ultra-low Latency Transmission**‌ Encoding and decoding --- ## RK3588 Cluster Server Performance Optimization Cases: Power Grid Inspection, Cloud Phone, and Industrial Quality Inspection Clusters - URL: https://intl.sienovo.cn/blog/149000591 - Date: 2025-06-29 - Tags: #服务器, #性能优化, #运维 The following are real-world RK3588 cluster performance optimization cases and technical solutions, covering three major fields—industrial quality inspection, power grid inspection, and cloud phones—all achieving significant performance improvements: * * * #### 🏭 ‌**I. Industrial Quality Inspection Cluster Optimization (Semiconductor Defect Detection)**‌ * ‌**Scenario Pain Points**‌: Traditional Celeron solutions offered micro-defect recognition accuracy of only 0.1mm² and a detection speed of 80 times/second, failing to meet the demands of precision electronics production lines5. * ‌**Optimization Scheme**‌: * ‌**Heterogeneous Collaborative Scheduling**‌: The CPU handles sensor data acquisition, while the NPU is dedicated to running the quantized YOLOv5 model (INT8 precision), achieving 0.01mm² micro-solder joint defect recognition57. * ‌**Zero-Copy Pipeline**‌: By using the `rknn_set_io_mem` API, camera data is directly streamed to the NPU, avoiding CPU overhead --- ## RK3588 Audio and Video Encoding and Decoding Applications in Edge Server Clusters - URL: https://intl.sienovo.cn/blog/149000433 - Date: 2025-06-29 - Tags: #人工智能, #fpga开发, #arm开发, #嵌入式硬件 The application of RK3588 audio and video encoding and decoding in edge server clusters is primarily reflected in three aspects: high-performance parallel processing, low-latency transmission, and multi-scenario adaptability. The specific technical implementation is as follows: * * * #### 🚀 ‌**I. Ultra-Scale Video Stream Parallel Processing**‌ 1. ‌**Cluster-Level Encoding and Decoding Throughput**‌ * A single node (equipped with 80 RK3588 chips) can concurrently decode 640 channels of 4K@30FPS H.265 video streams, supporting 8K@60fps hardware decoding and 8K@30fps encoding, meeting the massive video analysis demands of smart cities, traffic monitoring, and other applications.57 * The entire machine's AI computing power reaches 480TOPs, supporting real-time recognition and feature extraction of video stream content.5 2. ‌**Dynamic Bitrate Adaptation**‌ * Supports multi-channel video transmission over narrow bandwidths of 500Kbps~2Mbps, with real-time bitrate adj --- ## What are the advantages of FPGA in AI Inference Acceleration? - URL: https://intl.sienovo.cn/blog/148993861 - Date: 2025-06-29 - Tags: #fpga开发, #人工智能 FPGA offers the following core advantages in AI inference acceleration, making it particularly suitable for specific scenario requirements: * * * #### 🔋 I. **Energy Efficiency Advantages** * **Power Consumption Optimization**: FPGA's hardware-level customized computing units avoid the general architectural redundancy of GPUs. For the same performance, power consumption can be reduced to 1/3 to 1/2 of that of GPUs, significantly lowering data center operating costs 69. * **Sparse Computation Acceleration**: For compressed models such as pruning and low-bit quantization (e.g., Int6/binary networks), FPGAs dynamically shut down invalid computing units through zero-skipping hardware logic, achieving an energy efficiency ratio improvement of over 3 times compared to GPUs 610. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148993861/01_ab78235355804f61b343794a0c554b8f.png) * * * #### ⚡ II. **Low Latency Characteristics** * **Nanosecond-level Response**: FPGA hard --- ## Solutions for Implementing NVIDIA GPU Functionality Using FPGAs - URL: https://intl.sienovo.cn/blog/148993611 - Date: 2025-06-29 - Tags: #fpga开发, #arm开发, #人工智能 Implementing the core functionalities of NVIDIA GPUs using FPGAs is technically feasible, but requires balancing performance, development difficulty, and application scenarios. Here's a key analysis: #### 1. ‌**Architectural Differences and Implementation Challenges**‌ * ‌**Parallelism Model**‌: GPUs employ a SIMD architecture (e.g., CUDA cores), suitable for large-scale data parallelism; FPGAs achieve flexible parallelism through hardware-level circuit reconfiguration, but routing resources occupy 70-90% of the silicon area, limiting computational density38. * ‌**Development Complexity**‌: GPU programming relies on high-level frameworks like CUDA, whereas FPGAs require hardware description languages (e.g., Verilog) or OpenCL, leading to longer development cycles and requiring specialized hardware knowledge28. * ‌**Performance Bottlenecks**‌: FPGA clock frequencies are limited by programmable interconnect structures, typically lower than GPUs; video memory bandwidth (GB/s leve --- ## x86-based Industrial PC with Multiple Ethernet and Serial Ports, Supporting IP67 Water Resistance - URL: https://intl.sienovo.cn/blog/148898746 - Date: 2025-06-25 - Tags: #网络, #arm开发, #嵌入式硬件, #人工智能, #物联网 * * * #### **I. Core Configuration Solutions** 1. **Waterproof Enclosure Design** * 304 stainless steel fully sealed structure, IP66/IP67 certified, capable of withstanding high-pressure water jet cleaning and chemical detergent corrosion2. * Interfaces use M12/M20 waterproof aviation connectors (Ethernet ports, serial ports, power terminals), eliminating the risk of liquid ingress26. 2. **Multi-Ethernet and Multi-Serial Port Support** * Basic configuration: **8 independent Gigabit Ethernet ports** (Intel I210AT chip) + **8 isolated RS-232/485 serial ports**6. * Expansion capability: Via PCIe or modular slots, upgradable to a **10 serial port + 6 Ethernet port** combination (custom backplane required)56. 3. **Industrial-Grade Processor Platform** * Low-power solution: Intel Atom® x7433RE/x7835RE, supporting -40℃~75℃ wide-temperature operation2. * High-performance solution: Intel® Celeron J1900 quad-core processor (2.0GHz), fanless cooling desig --- ## X86-based Industrial PC for Acoustic Monitoring and Analysis - URL: https://intl.sienovo.cn/blog/148898455 - Date: 2025-06-25 - Tags: #人工智能, #fpga开发, #arm开发 An X86-based industrial PC dedicated to acoustic monitoring and analysis must be designed to combine industrial reliability, high-performance computing, and professional acoustic processing requirements. Below are its key features and application highlights: #### **I. Core Hardware Configuration Requirements** 1. **High-Performance Processor** Utilizes multi-core Intel Core i5/i7 or equivalent processors (e.g., 13th/14th Gen), supporting real-time operation of complex acoustic algorithms (such as noise spectrum analysis, sound source localization) 511. 2. **Large-Capacity Memory and High-Speed Storage** * DDR5 memory (≥32GB), supporting parallel processing of multi-channel acoustic data 811. * NVMe SSD (PCIe 4.0 interface), ensuring high-speed data read/write (e.g., 6GB/s image/audio stream caching) 78. 3. **Professional Expansion Interfaces** * Multiple PCIe slots: supporting acoustic acquisition cards, GPU accelerator cards (for AI voiceprint recognition) --- ## ARM+FPGA+ADC-based Energy Storage Coordinated Controller/EMS, Supporting Fully Domestic Production and Real-time Systems - URL: https://intl.sienovo.cn/blog/148870626 - Date: 2025-06-24 - Tags: #人工智能, #网络, #fpga开发, #arm开发 The Coordinated Controller is a versatile control device with flexible and customizable logic, allowing control logic to be tailored to specific application environment requirements. It has a wide range of applications, serving as a coordinated controller for new energy stations (photovoltaic, wind power, energy storage), or as a microgrid controller or integrated controller.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148870626/01_47d20fc53cc64606b715eb9bc650bc27.jpeg) Product Features 1. Supports graphical logic configuration tools for on-site visual configuration of device interface signals, processing logic, output control, and fault alarms, as well as program upgrades, allowing flexible customization of functions according to on-site requirements. 2. Features multi-channel signal acquisition and multi-channel control output. 3. Equipped with various communication interfaces, possessing powerful and fast communication capabilities, and fully supporting the IEC --- ## [Domestic AI Server] Fully Domestic PCIe 5.0 Switch Board, Replaces Broadcom 89104/89144, Supports Hygon, Loongson, and Other Platforms - URL: https://intl.sienovo.cn/blog/148793340 - Date: 2025-06-20 - Tags: #服务器, #运维 * ****Physical Product Image**** * ****Core Hardware Configuration**** ****1. Controller Chip****‌ * Uses domestic TL63104 controller chip, supports PCIe transfer rates of 2.5GT/s, 5GT/s, 8GT/s, 16GT/s, 32GT/s, and supports 96+8 lanes. Supports 6 x16 groups and 1 x8 group, with each group supporting 1 to 8 ports. x16 groups support x16, x8, x4, x2 ports; x8 groups support x8, x4, x2, x1 ports. * Basic Mode: Extends PCIe interfaces and supports multi-level expansion, as shown in the figure below. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148793340/01_4393249fe01f4dcd99c1f3d8686a2768.png) * NT Mode: Interconnects multiple PCIe domains, supporting NTB and DMA features, as shown in the figure below.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148793340/02_13fb9a5eb3c4ee1927812c7fc12df48.png) * ‌P2P Mode: Supports data transfer between any DPs, effectively increasing transfer bandwidth and reducing transfer latency. * Supports non-bloc --- ## RISC-V-based Power Gateway, Supporting Power HarmonyOS, NeoKylin, and Other Domestic Operating Systems - URL: https://intl.sienovo.cn/blog/148792846 - Date: 2025-06-20 - Tags: #arm开发, #fpga开发, #人工智能 The Distribution Visualization Gateway is a purpose-built edge intelligent gateway developed on the NB2 RISC-V core board, designed to bring real-time AI inference and sensor fusion directly into the field for power-grid monitoring and other demanding industrial applications. This post walks through what the platform is, how it is architected, and why its combination of domestic OS compatibility, edge AI capability, and rugged form factor makes it well-suited for transmission-line infrastructure deployments. ## Background: Why Edge AI at the Substation and Tower Level? Modern high-voltage transmission networks span hundreds of kilometres of terrain that is difficult to inspect manually — mountain passes prone to wildfire, ridgelines subject to ice loading, and corridors shared with construction equipment. Traditional SCADA systems rely on periodic human patrol or simple threshold-based sensors. Neither approach can react quickly enough to a fast-moving wildfire front or a tower crane --- ## RISC-V IoT Gateway, Supports HarmonyOS, RT-Thread Real-time System - URL: https://intl.sienovo.cn/blog/148792709 - Date: 2025-06-20 - Tags: #risc-v, #物联网 An IoT gateway developed based on a core board, it can be used as a protocol converter, industrial gateway, serial server, etc. The IoT gateway integrates functions such as data acquisition, data analysis, data storage, multi-protocol conversion, and IoT platform access. It supports cellular, Wi-Fi, and Ethernet communication, meeting data acquisition and forwarding application needs in various IoT scenarios. The IoT gateway's peripheral interfaces include dual Ethernet ports, input/output IOs, RS485, RS232, CAN bus, USB, SD card, 4G/5G communication, audio input/output, and Wi-Fi interfaces. The entire board adopts an industrial-grade design, capable of operating in various harsh environments. **Product Features** • Rich Peripheral Interfaces • Industrial-Grade Design • Supports Wi-Fi Connectivity • Supports 4G Communication • Dual Ethernet Port Design • Isolated Input/Output • Supports Audio Input/Output • Expandable Zigbee, LoRa Communication **System Support** **Supp --- ## Fully Domestic Ultra-Compact RK3576 Core Board, Supporting RK3576 + FPGA for AI and Real-time Control - URL: https://intl.sienovo.cn/blog/148667790 - Date: 2025-06-15 - Tags: #fpga开发 ## Fully Domestic Ultra-Compact RK3576 Core Board: RK3576 + FPGA for Industrial AI and Real-Time Control Rockchip's RK3576 has quickly established itself as one of the more capable mid-range SoCs for industrial edge computing, and a new fully domestic core board built around it pushes the form-factor and supply-chain story even further. This post walks through the hardware specifications, the heterogeneous RK3576+FPGA co-processing architecture, the real-time control figures you can expect from that combination, and the development resources available to engineers evaluating the platform. --- ## Core Board Hardware and Domestic-Supply Credentials The board ships in a 55 × 28 mm PCB form factor on a 12-layer, 1.6 mm stack with four mounting holes. A B2B connector with a 4.0 mm mating height keeps the assembled height under 5.4 mm, which is tight enough for embedded enclosures where a full SBC would never fit. An alternative stamp-hole package (IDO-SOM7609-S1) is available for even m --- ## RK3568 1U Chassis, Supports Electrical and Optical Ports with B-code Time Synchronization, Suitable for Power, Transportation, and More - URL: https://intl.sienovo.cn/blog/148608599 - Date: 2025-06-12 - Tags: #人工智能, #fpga开发, #arm开发, #服务器, #运维 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148608599/01_fa86731133e14620a0f2f9c43680c3d6.png) The RK3568-based 1U chassis solution offers high reliability and multi-interface support capabilities in fields such as power and transportation. Key features are as follows: #### 🔧 I. Core Hardware Configuration * ‌**Processor Platform**‌: Equipped with a Rockchip RK3568 quad-core Cortex-A55 processor (main frequency 1.8GHz-2.0GHz), integrating a Mali-G52 GPU and a lightweight AI NPU (supporting 1TOPS computing power) to meet edge computing requirements 13. * ‌**Storage Configuration**‌: Onboard 8GB LPDDR4X memory + 64GB eMMC storage (expandable to 1TB SSD) 13. #### 🔌 II. Key Interface Capabilities 1. ‌**Network Communication**‌ * ‌**Electrical Ports**‌: * Dual Gigabit Ethernet ports (10/100/1000M adaptive) * Dual Fast Ethernet ports (10/100M adaptive) 13. * ‌**Optical Port Expansion**‌: Extends 4G/5G modules via MINI-PCIE/M.2 int --- ## 【Domestic NI Alternative】Application of Data Acquisition Cards in Landslide Disaster Monitoring and Early Warning - URL: https://intl.sienovo.cn/blog/148563475 - Date: 2025-06-10 - Tags: #人工智能, #网络 Recently, a severe landslide disaster occurred unexpectedly due to continuous rainfall and complex geological conditions. Such sudden events not only severely threaten the lives of local residents but also cause immense damage to infrastructure. In this context, the role of data acquisition cards becomes crucial. By integrating data acquisition cards with various sensors **(such as rain gauges and draw-wire displacement sensors)**, we can perform real-time monitoring of critical areas like rainfall and geological conditions, accurately collecting key information such as displacement, flow, and rainfall. This data helps us better understand environmental change trends and promptly identify potential landslide hazards. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148563475/01_fca8dca5a72847cdbd8d7bf370c46370.png) **1** **Monitoring Role of Rain Gauges** Rain gauges play a particularly important role in landslide monitoring, as rainfall is one of the primary factors t --- ## [Domestic NI Equivalent] ARM+FPGA+AI Wind Power Vibration Monitoring System: Ensuring Stable Operation of Wind Power Generation Systems! - URL: https://intl.sienovo.cn/blog/148563331 - Date: 2025-06-10 - Tags: #ARMDev, #FPGADev, #AI As the global energy transition accelerates, the wind power industry, as one of the main forces of clean energy, is entering a period of rapid development. However, due to the complex and variable natural environment, its core components **(e.g., gearboxes, generators, main shafts, bearings, etc.)** are prone to mechanical wear, making fault monitoring particularly crucial. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148563331/01_cb1e2fd0e8dc4114b25e13b121c7cd0d.png) **Vibration Signal Monitoring: The "Stethoscope" for Wind Turbine Health Management** Wind turbines are composed of multiple components, and the operational status and lifespan of these components are affected by factors such as wind speed, load, and temperature. Traditional fault detection methods rely on periodic manual inspections, which cannot achieve real-time monitoring and comprehensive evaluation, leading to delays. By analyzing vibration signals, vibration monitoring, as a non-invasive monito --- ## 【Phytium AI Rugged Server】Fully Localized Phytium + Ascend 310 + PCIe Switch AI Large Model Server Solution - URL: https://intl.sienovo.cn/blog/148498912 - Date: 2025-06-07 - Tags: #人工智能, #服务器, #运维, #arm开发, #fpga开发 Here is the fully localized Phytium AI Rugged Server solution featuring Phytium + Ascend + PCIe Switch: * * * #### 🖥️ I. Hardware Architecture Highlights 1. ‌**Dual-Engine Domestic Computing Power**‌ * ‌**Phytium Processor**‌: Equipped with Phytium FT2000+/64-core server-grade CPU (main frequency 1.8-2.2GHz), supporting high-concurrency tasks and complex computations, meeting data center-level load requirements28. * ‌**Ascend AI Accelerator Card**‌: Integrates Ascend 310/310B chips (supporting INT8 computing power up to 64TOPS), providing efficient AI inference capabilities, suitable for scenarios such as image recognition and natural language processing25.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148498912/01_43e9c25cfc3e4688878a77a8b89f216d.png) 2. ‌**PCIe 5.0 Switch Technology**‌ * Achieves high-speed interconnection via PCIe 5.0 Switch, significantly enhancing data transfer bandwidth and scalability between the CPU and AI accele --- ## PEX8748 High-Speed PCI Express Switch Expands GPU Card Slots, Supports Customization, Domestic Localization, and Platforms like x86, Hygon, Phytium - URL: https://intl.sienovo.cn/blog/148492897 - Date: 2025-06-07 - Tags: #express, #fpga开发, #人工智能, #arm开发 The following is a PCIe switch-based GPU expansion solution using PEX8748, which meets domestic localization and multi-platform support requirements: #### I. Core Advantages of the Solution 1. ‌**Flexible Expansion Capability**‌ PEX8748 supports 48-lane, 12-port PCIe 3.0 (8GT/s) switching, enabling multi-host interconnection via Non-Transparent (NT) port functionality. It can split a single PCIe link into multiple x8 lanes, meeting the demand for parallel access of multiple GPU cards15. It supports hot-plugging and point-to-point direct connection architecture, ensuring low-latency (150ns) and high-reliability data transmission16.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148492897/01_88c89dceef5247aa95ade9e82f82c121.png) 2. ‌**Comprehensive Domestic Localization Adaptation**‌ * ‌**Hardware Platform Compatibility**‌: Verified support for domestic processor platforms such as Phytium FT2000 (ARM architecture), Hygon (x86 architecture), and Loo --- ## Fully Localized Server Solution Featuring Phytium FT2000+, Ascend 310, and PCIe 5.0 Switch - URL: https://intl.sienovo.cn/blog/148481876 - Date: 2025-06-06 - Tags: #人工智能, #fpga开发, #arm开发, #服务器, #运维 In today's rapidly advancing information technology landscape, servers, as core devices for data processing and storage, bear an increasingly critical mission. This fully localized server motherboard features a Phytium FT2000+/64-core processor, paired with Huawei's Ascend 310 AI chip, delivering exceptional performance and reliability. Core Configuration, Powerful Performance The motherboard is equipped with a Phytium FT2000+/64 server processor, featuring 64 cores with a clock speed ranging from 1.8GHz to 2.2GHz, effortlessly handling both high-load computing and multi-task processing. Concurrently, the introduction of the Huawei Ascend 310B AI processor makes the deployment of intelligent applications more efficient, providing enterprises with powerful data analysis and processing capabilities. Reliable Memory and Storage The motherboard comes with 64GB DDR4 memory, supporting ECC technology to ensure data integrity and stability. Additionally, it features 8GB eMMC storage and mu --- ## RK3568 + LINUX + CODESYS with License + Real-time System, Simultaneously Running Your Own Vision Applications - URL: https://intl.sienovo.cn/blog/148383445 - Date: 2025-06-02 - Tags: #linux, #运维, #服务器 RK3568 + LINUX + CODESYS with License + Real-time System, Simultaneously Running Your Own Vision Applications, allowing you to dedicate some cores to CODESYS and others to custom applications. An industrial control and vision integration solution built upon the RK3568 processor can be realized through the following technical architecture: I. Hardware Platform Core Configuration 1. RK3568 Processor: Quad-core Cortex-A55 architecture, main frequency 2.0GHz, integrated Mali-G52 GPU and 1TOPS NPU, supports multi-channel video encoding and decoding 67 2. Real-time System Extension: * Solution A: Xenomai3 real-time patch (Linux-RT kernel) achieves real-time performance of <100μs 38 * Solution B: AMP architecture asymmetric multiprocessing, with some cores running the RT-Thread real-time system 5 3. Vision Processing Acceleration: Running TensorFlow/PyTorch models via NPU, supports 16-channel 1080P video structured analysis 68 ![](https://pub-048dcb96257f476697b113fcb5939c --- ## Design of a Sonar Data Acquisition System Based on a Zynq ARM+FPGA Heterogeneous Platform - URL: https://intl.sienovo.cn/blog/148368585 - Date: 2025-06-01 - Tags: #arm开发, #fpga开发, #人工智能, #大数据 0 Introduction In recent years, with the development of marine engineering technology, underwater unmanned vehicles (UUVs) have played an increasingly important role in safeguarding national maritime rights and interests and marine security due to their flexibility, low risk, and multi-functionality [1-3]. When UUVs perform a series of tasks such as target search, tracking, parameter estimation, and maneuvering, they generally require active sonar systems to provide accurate target parameters such as range, bearing, and velocity [4-5]. Therefore, during the development of UUVs, active sonar systems need to be debugged through pool tests and actual sea trials to ensure their reliable performance. Active sonar systems typically use bare-metal or real-time operating systems, making it inconvenient to visually plot, view, and analyze the collected sonar data and signal processing results. For testing UUV active sonar systems, program updates generally need to be completed without comprom --- ## Hardware-Software Co-design of an EtherCAT Master Based on the Zynq Platform - URL: https://intl.sienovo.cn/blog/148368469 - Date: 2025-06-01 - Tags: #fpga开发, #人工智能, #arm开发, #计算机视觉 Abstract: Addressing the demands for control capability and strong real-time performance in industrial automation, an improved EtherCAT hardware master solution based on FPGA is proposed. This solution utilizes the Zynq-7000 platform, implementing the FPGA protocol stack on the PL (Programmable Logic) side to ensure efficient execution of core functions. A data interaction mechanism between the PS (Processing System) and PL is designed based on the AXI4 bus, enhancing the master's flexibility and data transmission efficiency. Experimental results show that this design achieves a maximum communication jitter of 88 ns, maintaining the high real-time performance of a hardware master, while integrating the flexibility of ARM. 0 Introduction In recent years, due to the excellent performance of EtherCAT real-time industrial Ethernet technology [1], it has attracted numerous scholars to conduct related research. Among these, building EtherCAT masters (i.e., software masters) on Windows and --- ## Motion Control Module Solution Based on RK3576+FPGA+CODESYS Industrial Control Board - URL: https://intl.sienovo.cn/blog/148208289 - Date: 2025-05-25 - Tags: #fpga开发, #人工智能, #大数据, #arm开发 The following are the key design points for the industrial motion control module technical solution based on the RK3576 processor and CODESYS platform:![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148208289/01_3f08abaac62445fc9018f970f08f6398.jpeg) * * * #### I. Hardware Architecture Design 1. ‌**Heterogeneous Computing Architecture**‌ * The main controller utilizes the RK3576 processor, leveraging its quad-core Cortex-A72 (2.3GHz) for complex algorithms such as motion trajectory planning and AI vision processing, its quad-core Cortex-A53 (2.2GHz) for real-time control tasks, and integrating a Cortex-M0 hard real-time core to achieve μs-level servo control13. * An extended PCIe x4 interface connects to an FPGA module, deploying PID control loops and pulse direction signal generation circuits, reducing the response cycle to 50μs25. 2. ‌**Multi-Protocol Industrial Interface Configuration**‌ * Native dual CAN-FD interfaces (supporting 5Mbps rate) con --- ## 8-Channel CAN Bus PLC Solution Based on RK3568 Processor - URL: https://intl.sienovo.cn/blog/148207978 - Date: 2025-05-25 - Tags: #fpga开发, #arm开发, #信号处理 Implementing an 8-channel CAN bus PLC solution based on the RK3568 processor requires an integrated design combining hardware expansion and software protocol stack. The key points of the technical solution are as follows: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/148207978/01_17e2cc901e9c40df906df4272f3143a4.png) * * * #### I. Hardware Architecture Design 1. ‌**Core Platform Selection**‌ * Adopting the RK3568 quad-core Cortex-A55 processor (main frequency 2.0GHz), integrating Mali-G52 GPU and 1TOPS NPU, to meet multi-protocol parsing and edge computing requirements8. * Equipped with 4GB LPDDR4 memory + 32GB eMMC storage, supporting the execution of complex control programs and data caching. 2. ‌**CAN Bus Expansion Scheme**‌ * ‌**Native Interfaces**‌: Utilizing the RK3568's built-in dual CAN FD controllers (supporting 1Mbps speed) to achieve 2 high-speed CAN channels8. * ‌**Expansion Interfaces**‌: Adding PCIe-to-CAN modules (e.g., PCAN- --- ## RK3588 Serial Deserializer Board, Supporting 8-Channel GMSL Cameras - URL: https://intl.sienovo.cn/blog/147953359 - Date: 2025-05-14 - Tags: #数码相机 Connecting multiple GMSL cameras to an RK3588-based platform is a common requirement in autonomous driving development kits, industrial inspection rigs, and multi-channel NVR appliances. This post breaks down how many GMSL cameras the RK3588 SoC can realistically support, which deserializer boards make it possible, and what the hardware and software integration looks like in practice. ## Why a Deserializer Board Is Required GMSL (Gigabit Multimedia Serial Link) is a serialized coaxial camera interface developed by Maxim Integrated (now Analog Devices). It is designed for long-cable, noise-tolerant camera links—ideal for automotive and industrial environments—but the RK3588 SoC does not have a native GMSL receiver. Instead, the RK3588 exposes up to **6 MIPI interfaces** through its DCPHY and CSI modules. A deserializer board sits between the GMSL cameras and the SoC, converting the serialized GMSL2 signal on each coax cable into a MIPI CSI-2 stream that the RK3588 can ingest directly. --- ## TI AM6442 + FPGA Solution, Supporting 6 Ethernet Ports, 4 CAN Channels, and 8 Serial Ports - URL: https://intl.sienovo.cn/blog/147926217 - Date: 2025-05-13 - Tags: #fpga开发, #arm开发, #人工智能 The TI AM6442 + FPGA solution offers the following technical advantages and applicable fields: I. Technical Advantages 1. ‌**Heterogeneous Multi-core Architecture**‌: The AM6442 processor integrates 7 cores (2x Cortex-A53 + 4x Cortex-R5F + 1x Cortex-M4F), enabling application processing, real-time control, and collaborative execution of independent tasks across different cores to meet the multi-level processing requirements of complex industrial scenarios.2; 2. ‌**FPGA Expansion Flexibility**‌: Leveraging the programmable nature of FPGAs, customized interface expansion (e.g., high-speed I/O, dedicated protocol stacks) and hardware acceleration logic can be rapidly implemented, complementing the AM6442.24; 3. ‌**Real-time Performance and Low Latency**‌: The parallel processing capability of FPGAs, combined with the real-time R5F cores, can meet microsecond-level response requirements, making it particularly suitable for motion control and signal processing applications.28; 4. ‌** --- ## Metro/High-Speed Rail Onboard Firewall, M12 Interface Firewall Solutions - URL: https://intl.sienovo.cn/blog/147901107 - Date: 2025-05-12 - Tags: #网络, #fpga开发, #人工智能, #大数据 Industry Solutions — Integrated Monitoring System ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147901107/01_50a232861755a8ff00b23124beb52024.jpeg) * Communication Network Security **Monitoring and Auditing:** Passively deploy an Industrial Control Security Monitoring and Auditing System on switches at stations, depots, parking lots, control centers, backup centers, and equipment maintenance centers. This system collects, analyzes, and processes network traffic, and in conjunction with specific security policies, provides real-time alerts for abnormal operations and attacks, and conducts post-event auditing. **Intrusion Detection:** Passively deploy an Intrusion Detection System to extract features from traffic and match them against a rule base, quickly and effectively identifying anomalies and attack behaviors in industrial control networks. * Zone Boundary Security **Boundary Protection:** Redundantly deploy industrial control firewalls between st --- ## Huawei Ascend's Applications and Technical Solutions in Smart Mining Robots - URL: https://intl.sienovo.cn/blog/147756082 - Date: 2025-05-07 - Tags: #机器人, #人工智能 #### I. Core Application Scenarios for Smart Mining Robots ##### 1. **Underground Smart Inspection Robots** * Inspection robots equipped with Ascend AI chips can achieve **fully autonomous navigation and multi-modal perception**. By utilizing LiDAR + visual SLAM technology, they can build real-time underground 3D maps and accurately identify abnormal conditions such as roadway deformation and equipment oil leaks47. * Combined with Ascend edge computing capabilities, it supports **parallel analysis of multiple video streams** (e.g., infrared thermal imaging for monitoring electromechanical equipment temperature), improving the accuracy of abnormal event recognition to 99.2%78. ##### 2. **Unmanned Mining and Excavation Robots** * Deploying **robotic arms and transport robots with Ascend AI computing power** at the coal mining face, they can visually identify coal-rock interfaces and geological structures, autonomously adjust cutting paths, reducing the need for human intervent --- ## RK3568-based Multifunctional In-Vehicle Positioning and Navigation Smart Information Terminal - URL: https://intl.sienovo.cn/blog/147755838 - Date: 2025-05-07 - Tags: #人工智能, #大数据, #arm开发, #fpga开发, #计算机视觉 Developed on the Android system, integrating 5G and 4G modules, GPS/BD dual-mode positioning module (high-precision differential inertial navigation), WIFI module, Bluetooth module, RFID module, audio playback, video signal input (AHD or CVBS) module, and other functionalities, this multifunctional in-vehicle positioning and navigation smart information terminal supports vehicle positioning, location tracking, video surveillance, work photo capture, audio monitoring, local video recording, overspeed warning, business data interaction, live voice broadcast, etc. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147755838/01_77b680a558994054a791e392cebb74c7.jpeg) **II. Technical Parameters** **Product-Related Parameters** Operating System Android 11.0 Operating System CPU Processor CPU Name Cortex-A55 64-bit Processor CPU Frequency 2.0GHz GPU ARM G52 2EE Supports OpenGL ES 1.1/2.0/3.2, OpenCL 2.0, Vulkan 1.1 Embedded high-performance 2D acceleration hardware VPU --- ## Sienovo's Power Communication Management Unit: A Counterpart to Advantech ECU-4674, Featuring 8 x LAN, 10 x COM, 1 x IRIG-B, and Full Domestic Production Support - URL: https://intl.sienovo.cn/blog/147741142 - Date: 2025-05-06 - Tags: #网络 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147741142/01_b33f3cc79cdd47f99e41458a4f644df4.png) **Features** ƒ China Electricity Certifcate IV level Certifcation for substation applications ƒ IEC 61850-3 and IEEE 1613 compliant ƒ Intel® Atom® E3930 processor, 4G DDR3L ƒ 10 x RS232/485 isolated serial ports ƒ 8 x RS232/422/485 isolated serial ports extension (optional) ƒ 8 x 10/100/1000 Base-T Ethernet ports ƒ 8 x 10/100/1000 Base-T Ethernet ports extension (optional) ƒ 8 x DI/O ports extension (optional) ƒ 1 x Internal m-SATA, 2 x 2.5" SATA ƒ 1 x IRIG-B ƒ Redundant isolated power with 100~240V AC/DC input ƒ Mounting: 2U Rack-mount ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147741142/02_479e4fe84d0846928a30fd1be67f379b.jpeg) **Introduction** The ECU-4674 product is compliant with Electricity Certificate level IV with higher reliability and stability, which is suitable for Global P&E automation market and harsh environment. ECU-4674 i --- ## Comparable to Advantech ECU-461: Fanless ARM Communication Management Platform with Phytium 4-core/8-core Domestic Processors, Featuring 8 LAN Ports, 8 Serial Ports, IRIG-B Time Synchronization, and Dual Display - URL: https://intl.sienovo.cn/blog/147740953 - Date: 2025-05-06 - Tags: #arm开发 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147740953/01_f016c3a1fed7493c8a110893155d370f.png) ƒ Phytium FT-2000/4 and D2000/8 main controllers, main frequency 2.3~2.6GHz ƒ 8 Gigabit Ethernet ports, 8 full-function isolated serial ports ƒ HDMI+VGA dual display interfaces ƒ 3 USB2.0, 2 USB3.0 ƒ Supports 2 sets of SATA hard drive storage ƒ Supports CAN communication (replaces 4 or 8 COM ports) ƒ Fanless thermal design for the entire machine ƒ Supports 2 channels of 100~240VAC/DC power input ƒ Extremely high domestic component ratio for the entire machine ƒ Supports PCIE x 1 custom expansion ƒ Motherboard supports 1U and 2U rackmount chassis (1U requires customization) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147740953/02_35e8f3bdc12a4bee87127b486cb47cda.jpeg) Introduction The ECU-461 is an embedded communication management platform based on Phytium FT-2000/4 compatible with D2000/8 domestic processors. It features 8 onboard Gigabit Ethe --- ## Smart Industrial Vision Edge Computing Box Solution Based on BM1684X + RK3588 - URL: https://intl.sienovo.cn/blog/147628038 - Date: 2025-04-30 - Tags: #边缘计算, #人工智能 ## **Smart Industrial Vision Edge Computing Terminal Technical Solution Document**‌ ### ‌**1\. Product Overview**‌ #### 1.1 Product Positioning * High-performance AI vision processing equipment for industrial automation scenarios * Integrated BM1684X (8TOPS INT8) AI acceleration chip + RK3588 (6TOPS NPU) heterogeneous computing * Supports industrial-grade multi-camera access, real-time defect detection, high-precision positioning, OCR recognition, and other scenarios #### 1.2 Core Advantages * ‌**Dual-chip Synergy**‌: BM1684X focuses on deep learning inference, while RK3588 handles multi-channel video encoding/decoding and system control. * ‌**Industrial-grade Reliability**‌: Wide temperature design (-20℃~70℃), EMI resistance, supports 24/7 continuous operation. * ‌**Algorithm as a Service**‌: Pre-installed with 20+ industrial vision algorithm models, supports one-click deployment of TensorFlow/PyTorch/Caffe models. * * * ### ‌**2\. Hardware Specifications**‌ #### --- ## What are the Pros and Cons of x86, RK, and NV Platforms for AGV/AMR Robot Controllers? - URL: https://intl.sienovo.cn/blog/147578834 - Date: 2025-04-28 - Tags: #机器人 Below is a comprehensive analysis of the advantages and disadvantages of x86, RK (Rockchip), and NV (NVIDIA) platforms in AGV/AMR robot controller solutions: * * * #### I. Core Performance Comparison Platform Advantages Limitations Applicable Scenarios ‌**x86**‌ 1. Multi-core high-frequency CPUs support complex algorithm computations, suitable for large-scale path planning and multi-robot collaborative control. 2. Strong compatibility, can run Windows/Linux systems, facilitating industrial software integration. 1. Higher power consumption (15-45W), affecting mobile device battery life. 2. Hardware cost is higher than embedded solutions. AMR clusters with high-precision navigation, complex scenarios requiring real-time data processing. ‌**RK**‌ 1. Low power consumption (5-10W) design, suitable for long-duration basic AGV material handling tasks. 2. High integration, supports multi-interface expansion (CAN/USB/GPIO). 3. Significant cost advantage. 1. Limited computing power --- ## Typical AGV Application Cases and Technical Analysis on the RK3588 Platform - URL: https://intl.sienovo.cn/blog/147578135 - Date: 2025-04-28 - Tags: #人工智能, #目标检测, #计算机视觉, #信号处理 #### Typical AGV Application Cases and Technical Analysis on the RK3588 Platform ##### I. Multi-sensor Fusion Navigation and Dynamic Obstacle Avoidance 1. ‌**High-Precision Indoor Navigation**‌ * With its 8-core CPU (4xA76+4xA55) and 6TOPS NPU computing power, the RK3588 supports multi-source data fusion from LiDAR, vision cameras, IMU, and more, achieving centimeter-level positioning and real-time obstacle avoidance for AGVs, suitable for complex and dynamic industrial environments12. * Dynamic obstacle avoidance response speed is enhanced to milliseconds, adapting to human-machine collaborative operation scenarios and reducing collision risks68. 2. ‌**Visual Recognition and Path Planning**‌ * The built-in NPU supports AI models such as yolov5s, achieving up to 49fps when processing high-definition video streams, enabling AGV visual navigation and target tracking (e.g., warehouse shelf recognition)34. * Combined with SLAM algorithms for 3D mapping --- ## Fully Localized Real-time Processing System Solution Based on RK3588+FPGA, and Its Case Studies - URL: https://intl.sienovo.cn/blog/147482285 - Date: 2025-04-24 - Tags: #fpga开发, #机器人, #人工智能, #大数据, #网络 The fully localized real-time processing system solution based on RK3588+FPGA demonstrates significant technical advantages in fields such as industrial automation, smart terminals, and multi-screen control. Its core architecture and key technical features are as follows: * * * #### I. Hardware Architecture Design 1. ‌**Main Control Chip Combination**‌ * Utilizes Rockchip RK3588J domestic processor (8nm process, 4_A76+4_A55 heterogeneous architecture, 6TOPS NPU computing power)16, paired with domestic FPGA chips such as Unigroup Guoxin Titan-2 PG2T390H, Anlogic, or Gowin37, to achieve collaborative optimization of computing power and real-time performance. * The FPGA is high-speed interconnected with the RK3588 via PCIe 3.0 or RJ45 Ethernet interface, supporting real-time transmission of multiple 1080P video streams and industrial sensor data25. 2. ‌**Interface Expansion Capability**‌ * Integrates standard industrial interfaces such as USB3.0, RS485/23 --- ## AI Vision Solution for Smart Industrial Parks Based on RK3588/Sophon BM1684X - URL: https://intl.sienovo.cn/blog/147481642 - Date: 2025-04-24 - Tags: #人工智能, #大数据, #arm开发, #fpga开发, #计算机视觉, #机器人 ## AI Vision Solution for Smart Industrial Parks Based on RK3588/Sophon BM1684X Industrial parks have long been reliant on traditional surveillance systems, which lack the intelligence and automation needed to optimize operations and improve efficiency. However, with the advent of AI vision solutions, industrial parks can now leverage advanced computer vision and machine learning capabilities to enhance their management and operations. The development approach for an AI vision solution in an industrial park involves retrofitting existing infrastructure to build a foundation for AI capabilities. This can be achieved by deploying edge AI computing devices such as the RK3588 and Sophon BM1684X, which provide the necessary processing power and AI acceleration for real-time video analytics and object detection. The overall solution architecture for an AI vision solution in an industrial park typically involves the following components: * **Edge AI Computing Devices**: RK3588 and Sopho --- ## x86+FPGA Platform-based Robot Controller Solution with 6 Serial Ports, 6 Ethernet Ports, and CAN Bus Support - URL: https://intl.sienovo.cn/blog/147479636 - Date: 2025-04-24 - Tags: #边缘计算, #人工智能 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147479636/01_5ee6fa4857934194cd9f873e66642fff.jpeg) The stability and computing power of robot control systems directly impact production efficiency and precision. Faced with such complex working conditions and harsh environments, **an industrial robotics company has enhanced its overall high-efficiency processing capabilities, multi-device compatibility, and environmental adaptability by introducing Sienovo's latest six-port industrial PC.** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147479636/02_86b287511922f8c96b3bd91c0d0540e6.jpeg) **I. Real-time Responsiveness: The Hardware Foundation for Complex Algorithms** **In practical applications, industrial robots require precise control over the movement trajectory and force of robotic arms based on preset programs. This industrial PC, with its excellent processing capabilities, can quickly analyze complex process data and adjust robot actions in real-time --- ## RK3568 + FPGA-Based Coordinated Controller Solution for Energy Storage - URL: https://intl.sienovo.cn/blog/147471797 - Date: 2025-04-24 - Tags: #fpga开发 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147471797/01_cbdbd0e817524791be2c1fe4484a6397.png) Model: RK3568 RAM: Onboard 4GB (MAX 8GB) NPU: Up to 1T Storage: EMMC: 128GB (MAX 128GB) GPU: ARM G52 2EE Operating System: Ubuntu 20.04. Debian 11.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147471797/02_3dc61bbfe411eb6311cae631297e8.png) **1.2 Industrial-Grade Design** * Wide Operating Temperature Range: -40℃~85℃ (with active cooling) * Electromagnetic Compatibility: Complies with IEC 61000-4-2/4/5 standards * Protection Rating: IP40 metal enclosure design * Power Input: Supports DC 9~36V wide voltage input ##### II. Data Acquisition and Monitoring **2.1 Multi-Protocol Sensor Access** * Supports industrial protocols such as Modbus RTU/TCP, IEC104, CANopen * Provides 8-channel analog input (16-bit ADC, ±10V range) * Integrated digital acquisition module (supports opto-isolation and debouncing) **2.2 Real-time Status Monitoring** * --- ## How to Choose the Right Energy Storage Coordination Controller Solution for Industrial/Grid Scenarios? - URL: https://intl.sienovo.cn/blog/147456358 - Date: 2025-04-23 - Tags: #人工智能, #fpga开发 #### How to Choose the Right Energy Storage Coordination Controller? * * * ##### I. ‌**Define Core Functional Requirements**‌ 1. ‌**Scenario Adaptability**‌ * ‌**Industrial/Grid Scenarios**‌: Requires support for Primary Frequency Regulation (AGC), Dynamic Reactive Power Voltage Regulation (AVC), and multi-source coordinated scheduling (e.g., PV, energy storage, diesel generator linkage), suitable for complex systems like microgrids and power grids. * ‌**Commercial & Industrial Scenarios**‌: Prioritize controllers that support peak shaving and valley filling, demand control, and anti-reverse current strategies to reduce enterprise electricity costs by ‌**15-30%**‌ and meet transformer capacity limits. 2. ‌**Real-time Monitoring and Control Precision**‌ * Requires data acquisition frequency ≥1 Hz, supports millisecond-level updates for parameters such as battery SOC (State of Charge), voltage, and current, with an error requirement of <0.5%. * Eme --- ## ARM+FPGA+DSP-Based Energy Storage Coordination Controller Solution, Supporting Localization - URL: https://intl.sienovo.cn/blog/147455968 - Date: 2025-04-23 - Tags: #ARMDev, #FPGADev, #SignalProcessing #### Functions and Design Solution of Energy Storage Coordination Controller * * * ##### I. **Core Functions** 1. **Real-time Monitoring and Coordinated Control** * Real-time acquisition of energy storage system parameters such as voltage, current, and temperature; monitoring of battery charge status and charge/discharge power; dynamic adjustment of power interaction between energy storage, grid, and loads to ensure energy supply-demand balance15. * Supports Primary Frequency Regulation (AGC) and Dynamic Reactive Power Voltage Regulation (AVC) functions, responding to grid frequency and voltage fluctuations to enhance grid stability45. 2. **Energy Management Optimization** * Optimizes charge/discharge strategies based on time-of-use (TOU) electricity prices and renewable energy output forecasts (e.g., solar irradiance, temperature), reducing enterprise energy costs by **15-30%**56. * Smooths photovoltaic (PV) power generation volatility, reduces grid impac --- ## Domestic RK3568+FPGA Solution Centered on "Real-time Control + High-Precision Acquisition + Flexible Expansion" - URL: https://intl.sienovo.cn/blog/147448559 - Date: 2025-04-23 - Tags: #fpga开发, #机器人, #人工智能, #大数据, #网络, #运维 ## Domestic RK3568+FPGA Solution: Real-Time Control, High-Precision Acquisition, and Flexible Expansion As industrial automation moves deeper into edge-AI territory, system designers face a familiar tension: general-purpose application processors offer rich software ecosystems and AI inference capabilities, but they cannot match the deterministic timing of dedicated hardware. Meanwhile, standalone FPGAs deliver the real-time control and high-speed I/O that factories demand, but they lack the compute horsepower to run modern perception models. The RK3568+FPGA pairing resolves this tension by treating the two devices as complementary halves of a single control plane—and doing so entirely on domestically sourced silicon. This post walks through the core technical architecture of this combined solution, its key performance characteristics, and how it has been deployed across sectors ranging from precision manufacturing to energy-grid inspection. --- ## Architecture Overview The RK3568 --- ## BM1684X+FPGA+GMSL Vision Solution: The Core Engine Driving Industrial Intelligence Upgrade - URL: https://intl.sienovo.cn/blog/147448428 - Date: 2025-04-23 - Tags: #fpga开发 ##### I. **Technical Architecture and Core Advantages** **1. Technical Composition** * **BM1684X**: Bitmain Technologies' third-generation AI acceleration chip, with computing power up to 17.6 TOPS (INT8), supporting mainstream deep learning frameworks (TensorFlow/PyTorch), and optimized for edge-side vision inference. * **FPGA**: Provides flexible, programmable real-time signal processing capabilities, supports high-speed data parallel computing, and is adaptable to multi-sensor fusion scenarios. * **GMSL (Gigabit Multimedia Serial Link)**: Supports ultra-long-distance (over 15 meters) high-speed video transmission (up to 6Gbps), is resistant to electromagnetic interference, and meets the demands of complex industrial environments. **2. Synergistic Advantages** * **High-Performance AI Inference**: BM1684X accelerates models like YOLOv5 and ResNet, achieving millisecond-level object detection and classification. * **Low-Latency Real-Time Processing**: FPGA performs image --- ## Research on a Fully Domestically Produced RapidIO Solution Based on Loongson 2K1000 Processor and Fudan Micro FPGA K7 - URL: https://intl.sienovo.cn/blog/147409458 - Date: 2025-04-22 - Tags: #fpga开发, #信号处理, #嵌入式硬件, #机器人 After more than 20 years of development, the RapidIO bus protocol [1] has become one of the preferred solutions for high-performance system interconnects [2] based on packet switching. It is widely used in various fields such as wireless communication, military, supercomputing, medical image processing, and industrial control, all of which are, without exception, related to the national economy, people's livelihood, and national security. Currently, chips providing RapidIO bus interfaces mainly come from NXP's PowerPC (from the US), Texas Instruments' C6000 series DSP, Renesas' TSI series RapidIO switch chips and PCIe-to-RapidIO bridge chips, as well as Xilinx's RapidIO IP soft core. Domestically, there are few localized alternative solutions comparable to the aforementioned chips. This article proposes a fully domestically produced RapidIO solution based on the Loongson 2K1000 processor [3] and Fudan Micro FPGA, and verifies the feasibility of this solution through a specific projec --- ## Solution for Relay Protection Device Test Equipment Based on Domestic FPGA, Loongson 2K1000 Processor, and SylixOS Domestic Operating System - URL: https://intl.sienovo.cn/blog/147408985 - Date: 2025-04-22 - Tags: #fpga开发 **0** Introduction In recent years, China's independently controllable chips have developed rapidly under the support of national policies and government, initiating a wave of domestic substitution in fields such as electric power, military, machinery, communications, electronics, and medical care. However, there are still significant shortcomings in chip independent controllability and domestic substitution. In 2022, China's integrated circuit imports reached 538.4 billion units, with an import value exceeding 400 billion US dollars, while exports in the same year were 153.9 billion US dollars, making integrated circuits the commodity with the largest trade deficit in China \[1]. According to data from the National Bureau of Statistics, most of China's high-end chips are imported from European and American countries, which is a significant gap compared to the government's initiative for independently controllable chips. For IED equipment and test devices in the power industry, their --- ## 4U Rack-Mount Power Fault Recorder Design Solution with Screen, Based on DSP/ARM+FPGA+AI, Supporting Full Domestic Production - URL: https://intl.sienovo.cn/blog/147397436 - Date: 2025-04-21 - Tags: #fpga开发, #arm开发, #人工智能, #计算机视觉 4U Rack-Mount DSP/ARM+FPGA+AI Power Fault Recorder and Analyzer with Screen, supporting localization, includes CPU master control module, 96 channels of analog acquisition, 256 channels of digital inputs, communication expansion card, etc. #PowerFaultRecording #4URackMountWithScreen #NewEnergy #PowerMonitoring![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147397436/01_b1aca317d55948b1883797cc223f95fe.jpeg) Key Features 1) It is designed with an embedded graphical system, advanced DSP and 32-bit embedded CPUs, combined with a high-performance embedded real-time operating system, to meet the power system's evolving demands for transient and steady-state fault recording. 2) This device features a fully embedded design, utilizing an embedded graphical operating system, DSP technology, large-scale FPGA technology, embedded real-time operating system technology, and network communication technology. It incorporates the latest developments in power systems, particularly the --- ## RK3588+FPGA+AI YOLO Fully Localized USV Object Detection System (Part 2): Platform Design - URL: https://intl.sienovo.cn/blog/147385755 - Date: 2025-04-21 - Tags: #人工智能, #YOLO, #目标检测, #计算机视觉, #信号处理, #fpga开发 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147385755/01_d14ad55b9dba411796bd2e85463c67c4.png) Based on project requirements, the overall architectural design of the domestic AI platform was determined, and the selection and setup of hardware units, along with the configuration of the development toolchain, were completed. 4.1 Overall Architecture of the Domestic AI Platform This paper designs a flexible and efficient overall architecture for a domestic AI platform. The design method involves using a serial bus (Peripheral Component Interconnect Express, PCIe) or an RJ45 Ethernet port on an embedded platform to acquire 1080P image data streams. Then, through the collaborative work of relevant hardware units and software environments, it achieves forward inference of object detection algorithms and real-time display of detection results. Therefore, the processing flow architecture shown in Figure 4-1 was designed. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2 --- ## Unmanned Surface Vehicle Target Detection System Based on RK3588+FPGA+AI YOLO (Part 1) Overview - URL: https://intl.sienovo.cn/blog/147385513 - Date: 2025-04-21 - Tags: #人工智能, #fpga开发, #YOLO Unmanned surface vehicles (USVs) play a crucial role in fields such as marine monitoring, resource exploration, maritime security, and scientific research, improving the efficiency and safety of maritime operations. In this process, environmental perception technology and target detection technology complement each other, jointly forming the core functions of the system. With the rapid development of the artificial intelligence industry, various intelligent chips, sensors, processors, and embedded systems have been widely deployed, forming a relatively complete ecosystem. However, using foreign platforms for environmental perception poses information security issues, making the adoption of domestic platforms one of the key solutions to this problem. Therefore, this paper is dedicated to researching a surface target detection system based on domestic platforms and building a complete development toolchain. The main work is as follows: (1) To address the issues of insufficient detectio --- ## X86/RK/Allwinner + FPGA + AI-based Industrial Panel PC Application Solution in Power Grounding Systems - URL: https://intl.sienovo.cn/blog/147332301 - Date: 2025-04-18 - Tags: #网络, #运维 With the development of power technology and increasing demand, smart grid construction has garnered global attention. The construction of the power 'five-prevention' system is a core task for ensuring China's power safety, and the grounding management system is a critical component, essential for the safe, stable, and efficient operation of power systems. Industrial Panel PCs, with their excellent performance, stability, and environmental adaptability, and ability to meet EMC requirements for the power industry, including Power Level 3B and Level 4B certifications, play a crucial role in power grounding systems. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147332301/01_f5340b3a80e98f3cb51bb00033c1597a.png) A grounding system, also known as a grounding grid, consists of multiple buried metal grounding electrodes and conductors connected in a mesh structure. Its main functions include protecting personnel and equipment safety, and reducing electromagnetic interferen --- ## Nvidia Jetson/RK3588/X86+FPGA+AI Embodied AI Robot Controller, Supports Large Models, Supports Real-time Kernel - URL: https://intl.sienovo.cn/blog/147306062 - Date: 2025-04-17 - Tags: #人工智能, #大数据 On March 5, 2025, the Government Work Report reviewed by the Third Session of the 14th National People's Congress explicitly proposed establishing a growth mechanism for investment in future industries, fostering emerging industries such as biomaufacturing, quantum technology, 6G, and embodied AI. This policy signal demonstrates the nation's high regard for the development of the embodied AI industry, injecting strong momentum into its growth. The "Top Ten Trends in Humanoid Robots Outlook" released at the 2024 World Robot Conference pointed out that embodied AI refers to high-quality, high-performance intelligent systems capable of rapid and precise responses in highly dynamic environments. With continuous technological breakthroughs and the gradual improvement of the industrial ecosystem, embodied robots are accelerating their transition from laboratories to real-world application scenarios, becoming a crucial force in building a modern industrial system. ![图片](https://pub-048dcb96 --- ## X86/Nvidia+FPGA-Based Large Model Embodied AI Robot Controller Solution: Combining Computational Power with Real-time Convenience - URL: https://intl.sienovo.cn/blog/147305659 - Date: 2025-04-17 - Tags: #机器人 2025 marks the inaugural year for the industrialization of humanoid robots. The industry has moved beyond early-stage laboratory R&D, entering a new cycle of "scenario validation + mass production ramp-up." It is projected that the embodied AI market size will exceed one trillion yuan by 2031. This progress is underpinned by systematic breakthroughs in underlying technologies such as **hardware computational power, real-time control, and environmental adaptability**—and how to coalesce these technologies into reliable "machine intelligence" is becoming a critical battlefield for industry competition. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/147305659/01_ba832b672b264dc5a57bbf2532251a60.png) **The "Invisible Threshold" of Industrial Upgrading: Technical Coupling Challenges in High-Dynamic Scenarios** The ultimate goal of embodied AI robots is to equip machines with human-like perception, decision-making, and execution capabilities. However, in scenarios such as i --- ## Road Traffic Object Detection Design Based on ZYNQ MPSOC Heterogeneous Platform, also Supporting RK3588+FPGA - URL: https://intl.sienovo.cn/blog/147277177 - Date: 2025-04-16 - Tags: #目标检测, #人工智能, #计算机视觉 0 Introduction In recent years, China's automotive industry has continuously upgraded and developed, with the sales proportion of new energy electric vehicles steadily increasing. Automobiles are gradually evolving towards technological and intelligent development. Autonomous driving technology and driving safety detection in smart cars are inseparable from object detection technology. Traditional object detection relies on manually designed and extracted features, resulting in low detection accuracy. With the rise of deep learning technology and convolutional neural networks, deep learning algorithms have replaced traditional algorithms, becoming the mainstream algorithms for current object detection tasks. Conventional deep learning algorithms are typically deployed on high-performance computers, which are large in size and high in power consumption, making them inconvenient for installation in vehicles. Deploying object detection algorithms on embedded edge devices can effective --- ## Software Design of a Seismic Data Acquisition System Based on STM32+FPGA, Supporting RK3568+FPGA Platform - URL: https://intl.sienovo.cn/blog/147276553 - Date: 2025-04-16 - Tags: #fpga开发, #arm开发 0 Introduction Seismic observation is a key focus of geophysical observation and forms the foundation for the development of seismology and geophysics \[1]. The primary function of a seismic data acquisition system is to convert analog seismic signals collected by seismometers into digital signals for recording or transmission \[2], providing a large volume of fundamental data for seismology. This paper will introduce the software design of a seismic data acquisition system based on FPGA+ARM. 1 Research Background System Architecture. This design uses STM32MP157 as the main control unit, running in a Linux environment. The ADC acquisition module converts the three-component analog seismic signals generated by the seismometer into digital signals through sampling. The FPGA is primarily responsible for data acquisition, data transmission, and ADC parameter control, collecting IRIG-B codes received by the GPS module, forwarding PPS second pulses for timing to the ARM, and facilitating --- ## Integrated Device for Power New Energy Smart Substations Based on x86/RK3568 - URL: https://intl.sienovo.cn/blog/147251287 - Date: 2025-04-15 - Tags: #fpga开发, #arm开发, #架构, #人工智能 ****I. Project Overview**** Smart substations have always been a hot topic in the power industry. Addressing the construction requirements of smart substations, this application aims to solve problems such as low automation, poor economics, inconvenient operation and maintenance, and difficulty in achieving networked management in traditional station power supplies. By adopting the latest power electronics and communication measurement and control technologies, a new generation of highly reliable, cost-effective integrated power supply system has been developed. The integrated master monitoring unit, as the centralized monitoring and management unit of the smart integrated power supply system, can simultaneously monitor various station power supply equipment. Downstream, it communicates with each sub-unit monitoring device, collects sub-unit operating conditions and information data, achieving distributed measurement and control with centralized management. Upstream, it connects to --- ## Nationally Produced Switch Solution Based on Phytium/Loongson + Centec CTC7132 - URL: https://intl.sienovo.cn/blog/146712953 - Date: 2025-03-29 - Tags: #机器人, #信号处理, #fpga开发 1. ****Product Introduction**** * Centec CTC7132, built-in ARM-Cortex A53, clocked at 1.2GHz; * Supports 24 Gigabit Ethernet ports, 24 10 Gigabit optical ports (850nm multimode), 1 Gigabit management Ethernet port, 1 management serial port; * Supports 1 Fast Ethernet health management port: used for reporting device port status, voltage, current, temperature, and other information; * Internal connectors feature locking mechanisms, providing excellent reinforcement characteristics, stability, and reliability, suitable for use in harsh environments; * 100% domestic production and autonomous control; * Supports Layer 3 switching functions. Figure 1-1 Product Physical Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146712953/01_631848d5518145da9fc97583a0d10ee5.png) 1. ****Product Specifications**** ****Specification Item**** ****Specification Content**** CPU Centec CTC7132, built-in ARM-Cortex A53 1.2GHz Switch Chip Centec CTC7132 Memory 1G --- ## Centec CTC7132 Switch Core Module - URL: https://intl.sienovo.cn/blog/146712616 - Date: 2025-03-29 - Tags: #单片机, #嵌入式硬件, #信号处理 1. Introduction Built upon the Centec CTC7132 SOC solution, this module exposes 32 channels of 10G SerDes interfaces, 1 PCIe x1 interface, 2 SGMII management interfaces, 3 UART interfaces (1 debug serial port + 2 functional serial ports), 4 I2C interfaces (2 for SOC, 2 for PPU), 5 SMI interfaces (1 management port + 4 service ports), 1 100MHz PCIe differential reference clock output interface, a serial LED signal group, etc., via board-to-board high-speed connectors. When used with a carrier board, it can flexibly provide multi-rate, multi-form interfaces to meet diverse application requirements. 2. Hardware Parameters 1. Core board onboard DDR4 capacity: 2GB; 2. Core board onboard eMMC capacity: 8GB; 3. Provides 32 channels of 10G SerDes signal interfaces, supporting SGMII/QSGMII/XAUI/XFI/10G-KR and other modes; 4. Provides 2 SGMII management interfaces; 5. Provides 1 PCIe interface; 6. Provides system operation indicator signals, power indicator signals, over-temperature --- ## All-Domestic Standard 6U VPX Board Solution Based on Loongson 3A5000 Processor - URL: https://intl.sienovo.cn/blog/146712340 - Date: 2025-03-29 - Tags: #fpga开发, #运维, #信号处理, #服务器, #人工智能 ### ******1********, ********Product Features****** This product is a highly reliable standard 6U VPX board based on the Loongson 3A5000 processor and 7A2000 chipset, featuring Ethernet, SATA, PCIe, and display interfaces. The product functional block diagram is shown in Figure 1: Figure 1 System Block Diagram![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146712340/01_6a623fac29ff455394dd0b30c2d0f101.png) ### ******2, Technical Specifications****** **No.** **Item** **Specification** **Remarks** 1 Form Factor 6U VPX 2 Dimensions 233.5mm (L) * 160mm (W) * 25.4mm (H) 3 CPU Loongson LS3A5000 Industrial-grade, 2.0GHz clock speed 4 Chipset Loongson LS7A2000 Industrial-grade 5 Memory Capacity 16GB 6 Discrete Graphics Card 1x MXM interface Jingjia Micro JH920 graphics card 7 Integrated Graphics Card Loongson LS7A2000 9 BMC Reserved MCU for BMC functionality Module form 10 Onboard Storage Interfaces 1x mSATA, 1x M.2 connector M.2 shares a PC --- ## Fully Domestic 1U Rack-Mount Switch Solution - URL: https://intl.sienovo.cn/blog/146712150 - Date: 2025-03-29 - Tags: #SignalProcessing, #FPGADev, #Server 1. Specifications 1. Basic Parameter Information Basic Information Port Specifications 32 x 10/100/1000Base-T RJ45 ports, 8 x 1G/10Gig SFP+ ports 1 x RJ45 Console management port 1 x USB interface, 1 x reset button Dimensions 482 mm (L) × 300 mm (W) × 44 mm (H) (including rack ears) Installation Method 1U rack-mountable Weight ≤3 kg Operating Voltage Dual redundant 220V AC power supply Power Consumption ≤60 W Operating Temperature -40°C to +65°C, 5%–95% relative humidity, non-condensing Storage Temperature -40°C to +85°C, 5%–95% relative humidity, non-condensing Relative Humidity 5%–95%, non-condensing Protection Rating Fan-cooled, metal enclosure 1.1 Software Specifications **Main Software Features** Software Features Redundant Networking: Supports STP/RSTP/MSTP, EAPS, ERPS Multicast Support: Supports IGMP Snooping V1/V2/V3 Layer 3 Features: Supports static routing, RIP, OSPF, VRRP, and other Layer 3 routing protocols VLAN: Supports IEEE 802.1Q 4K VL --- ## All-Domestic Standard 6U VPX Board Based on Phytium FT2000/4, Supporting Galaxy Kylin - URL: https://intl.sienovo.cn/blog/146711888 - Date: 2025-03-29 - Tags: #SignalProcessing, #FPGADev, #Server, #DevOps, #AI ### ******1**** ****Features****** A high-reliability standard 6U VPX board based on the Phytium FT2000/4 processor and X100 chipset, featuring Ethernet, SATA, PCIe, and display interfaces. The product functional block diagram is shown in Figure 1: Figure 1 Functional Block Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146711888/01_bb42a6807bdb4caea0f0b6cdd6d9bf57.png) ### ******2 Technical Specifications****** The product's functional and performance specifications are detailed in Table 1. Table 1 Product Functional and Performance Specifications **System** CPU Phytium FT2000 quad-core processor, 2.2GHz clock speed, optional Phytium D2000. Memory Onboard 16GB DDR4 2400MHz, optional 32GB Firmware UEFI VPX Bus VITA46.0 VITA46.3 VITA46.9 VITA46.11 VITA65 **Display** Graphics Card Parameters Core frequency 600MHz Video memory capacity 8GB LPDDR4 Supports dual-screen 4K (3840x2160) resolution display output Display Interfaces Backplane supp --- ## CPLD+MCU-based 3U Chassis Digital Input Acquisition Board (DI) for Standard DC110V Digital Switch Signal Acquisition and Processing - URL: https://intl.sienovo.cn/blog/146315856 - Date: 2025-03-17 - Tags: #arm开发, #fpga开发, #架构, #人工智能, #单片机 ![01.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146315856/01_ff4de7d21dc758e3a7189ad1ded129dc.jpeg) This article introduces Sienovo's 3U-form-factor Digital Input (DI) acquisition board, a purpose-built embedded hardware module for reliably capturing and processing standard DC 110 V digital switch signals in industrial environments. If you are evaluating board-level I/O solutions for railway, power-grid SCADA, or substation automation systems—where 110 V DC logic levels are the norm—this design walkthrough covers the key architectural decisions, component choices, and electrical specifications you need. ## Why DC 110 V Switch Signals? Industrial control systems inherited the 110 V DC signaling standard from decades of railway and utility practice. Unlike the 24 V DC common in factory automation, 110 V DC provides inherent noise immunity over long cable runs and allows legacy relay circuits to interoperate with modern digital I/O cards without a separate voltage co --- ## CPLD-Based Digital Output (DO) Board for Power/Rail Transit 3U Chassis - URL: https://intl.sienovo.cn/blog/146315669 - Date: 2025-03-17 - Tags: #fpga开发, #边缘计算, #人工智能, #大数据, #嵌入式硬件 This board is a **14-channel digital output (DO) card** designed for 3U chassis deployments in power and rail transit applications. It combines a Freescale MC9S08DZ60 microcontroller, an Altera EPM570T CPLD, and solid-state relays to deliver robust, optically isolated switching suitable for the demanding electrical environments found in traction power substations and train control cabinets. This post covers the board's architecture, key component choices, and the design rationale behind its specification. ## Application Context Power and rail transit systems impose strict requirements on digital output hardware: wide operating temperature ranges, immunity to high-voltage transients, galvanic isolation between control logic and field loads, and deterministic behavior under fault conditions. A 3U CompactPCI or similar backplane chassis provides the mechanical and electrical framework, while individual function boards — like this DO card — plug in to perform specific I/O tasks. The DO b --- ## CPCI Bus 3U Chassis Pulse Input/Output Board (PIO) for Driving Inverter Power Modules, Used in Rail Transit / Power Storage, etc. - URL: https://intl.sienovo.cn/blog/146315597 - Date: 2025-03-17 - Tags: #fpga开发, #边缘计算, #人机交互, #人工智能 The **CPCI Bus 3U Pulse Input/Output (PIO) board** is a pure-hardware interface card designed to bridge a DSP controller and the gate-drive circuitry of inverter power modules. This post walks through the board's architecture, electrical specifications, and explains why each design choice matters for demanding applications such as rail-transit traction drives and grid-scale battery energy storage systems (BESS). ## What Problem Does a PIO Board Solve? Modern variable-frequency drives (VFDs) and inverter systems are built around a DSP or FPGA that generates precise PWM timing, but the signal levels that come off a DSP I/O pin—typically 3.3 V LVCMOS—are far too weak to directly switch insulated-gate bipolar transistors (IGBTs) or SiC MOSFETs. Those devices demand gate signals in the ±15 V range, with enough current sourcing and sinking capability to slew large gate capacitances quickly and cleanly. At the same time, safe closed-loop control requires that actual switching events are co --- ## CPLD+MCU-Based 3U Chassis Analog Acquisition Board (AIO-I), Featuring Analog Input, Analog Output, PWM Input, and PWM Output - URL: https://intl.sienovo.cn/blog/146315482 - Date: 2025-03-17 - Tags: #单片机, #嵌入式硬件 The AIO-I is a 3U chassis analog acquisition board built around a CPLD+MCU architecture, designed for industrial control systems that need simultaneous analog I/O, current-loop signalling, and PWM measurement in a compact, ruggedized form factor. This post walks through the board's architecture, key components, and the design rationale behind its signal chain. ## Overview and Target Application Industrial control racks—particularly those built to 3U CompactPCI or proprietary backplane standards—frequently require a single board that can handle mixed-signal tasks: reading process variables from 4–20 mA current-loop sensors, driving actuators with analog current outputs, capturing PWM-encoded feedback signals, and generating PWM drive signals for motor controllers or valve actuators. The AIO-I consolidates all four functions onto a 220 mm × 100 mm PCB, keeping the assembly weight at 160 g and staying within a standard single-slot 3U profile. ## Core Silicon: MC9S08DZ60 MCU and EPM570T --- ## FPGA-based 3U Chassis PT100 Temperature Acquisition Board for Rail Transit, Power Energy Storage, and Similar Applications - URL: https://intl.sienovo.cn/blog/146315347 - Date: 2025-03-17 - Tags: #fpga开发, #arm开发, #架构, #人工智能 ![01.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146315347/01_85cb42e427814f5c0dfa92766066a583.jpeg) Accurate temperature monitoring is a non-negotiable requirement in rail transit propulsion systems, grid-side power energy storage cabinets, and industrial drive enclosures. This post covers a 3U chassis-mountable PT100 temperature acquisition board built around FPGA-based signal conditioning, designed to read up to eight PT100 resistance temperature detectors (RTDs) simultaneously and deliver calibrated 4–20 mA current loop outputs directly to a host processor or PLC. ## Why PT100 RTDs for Industrial Temperature Sensing PT100 is a platinum RTD whose resistance is nominally 100 Ω at 0 °C and follows a well-characterised positive temperature coefficient curve defined by the IEC 60751 standard. Compared with thermocouples, PT100 sensors offer better long-term stability, higher repeatability, and immunity to the cold-junction compensation errors that plague thermocoupl --- ## FPGA-based 3U Chassis Analog High-Speed Sampling ADI Board, Applied in Rail Transit/Power Energy Storage, etc. - URL: https://intl.sienovo.cn/blog/146315266 - Date: 2025-03-17 - Tags: #FPGADev, #ARMDev, #Architecture, #AI ## FPGA-Based 3U Chassis Analog High-Speed Sampling ADI Board for Rail Transit and Power Energy Storage Applications Precision motor control in demanding industrial environments — rail transit drives, power energy storage inverters, grid-tied converters — hinges on fast, accurate feedback of two physical quantities: rotor speed and phase current. This post introduces a 3U chassis analog high-speed sampling board (ADI) built around a Xilinx Spartan-6 FPGA, designed specifically to close that feedback loop with the signal fidelity and isolation margins that industrial deployments require. ## What the Board Does The ADI board serves as the analog front-end for motor closed-loop control systems. It simultaneously captures: - **Motor speed** via frequency detection on up to six channels, accepting signals with amplitudes up to 15 V. These channels are well-suited to resolver-derived square waves, Hall-effect sensor outputs, or encoder differential signals that have been conditioned to s --- ## CPCI Motor Control Board (DSP) for Rail Transit 3U Chassis, Primarily Running Control Algorithms for Precise Motion Control of Traction Motors - URL: https://intl.sienovo.cn/blog/146315024 - Date: 2025-03-17 - Tags: #FPGADev ![01.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146315024/01_514ca6241f286f12967ce253ad215665.jpeg) Rail transit traction systems demand extremely tight control over motor torque, speed, and rotor position across wide temperature ranges and electrically noisy environments. This post covers a 3U CPCI motor control board built around a dual-TMS320F28335 DSP architecture, designed to run real-time control algorithms for precise motion control of AC traction motors. The board is a production-grade embedded computing card that slots into a CompactPCI chassis and handles everything from current sampling and frequency detection to CAN-based communication with supervisory controllers. ## Application Context: Traction Motor Control in Rail Transit In electric rail vehicles — metro trains, light rail, and locomotives — the traction inverter converts DC bus power into variable-frequency, variable-voltage AC to drive the traction motor. The motor controller sitting between th --- ## MPC8377-based MCPU 3U CPCI Board - URL: https://intl.sienovo.cn/blog/146314932 - Date: 2025-03-17 - Tags: #linux, #Codesys, #RK3568, #PLC, #RK3588 ![01.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146314932/01_56c5e25d5092d70bbf8f162a99fc79d4.jpeg) This post covers the hardware architecture and specifications of an MPC8377-based Master Control Processing Unit (MCPU) designed in the 3U CompactPCI form factor. Boards like this occupy a critical role in industrial control systems — bridging the gap between field-level I/O and supervisory software by handling logic execution, inter-board communication, safety switching, and persistent data storage in a single ruggedized module. ## Board Role in a CPCI Chassis The MCPU is the brain of a CompactPCI (CPCI) rack system. In a typical industrial deployment, peripheral boards — analog I/O, digital I/O, communication front-ends — plug into the same passive backplane and exchange data with the MCPU over the CPCI bus. The MCPU is responsible for: - **Logic control** — executing control algorithms, ladder logic, or function-block programs that determine actuator outputs fro --- ## FPGA-based 3U Rail Transit Network Communication Board: Internal Communication with Main Control and I/O Boards, External RS485, CAN, or MVB Networking - URL: https://intl.sienovo.cn/blog/146314856 - Date: 2025-03-17 - Tags: #fpga开发, #边缘计算, #人工智能, #大数据, #嵌入式硬件 ## Overview The NETI (Network Interface Board) is a 3U-format FPGA-based communication card designed for rail transit control systems. Positioned as the communication hub within a modular control rack, it bridges internal backplane traffic — carrying data to and from the main control board and distributed I/O boards — while simultaneously managing external field-bus connections to trackside equipment, other vehicles, or wayside controllers. This post walks through the board's architecture, component choices, and the role each interface plays in a typical rail transit installation. ![NETI Board](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146314856/01_49f0fe322fafc84947a36c940414be22.jpeg) ## Role in a Rail Transit Control Rack Modern rail traction and auxiliary control systems are built around a backplane-based, card-cage architecture. A typical rack contains a main control board (CPU/MCU), multiple I/O boards handling discrete signals, analog measurements, and relay o --- ## FPGA-based Rail Transit CPCI Fiber Optic Board (6U) - URL: https://intl.sienovo.cn/blog/146314793 - Date: 2025-03-17 - Tags: #fpga开发, #边缘计算, #人机交互, #人工智能, #嵌入式硬件 ## FPGA-Based Rail Transit CPCI Fiber Optic Board (6U): LVDS-to-Optical Signal Conversion for High-Speed Backplane Communication Industrial rail transit systems demand communication links that are immune to electromagnetic interference, capable of operating across wide temperature ranges, and reliable enough to meet the rigorous uptime requirements of passenger rail infrastructure. This 6U CPCI fiber optic board addresses those requirements by converting LVDS (Low-Voltage Differential Signaling) electrical signals to optical signals, bridging high-speed on-board data buses with the outside world through twelve SFP fiber ports. ![01.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146314793/01_df953ddf18c53ce552b387af51aa34ab.jpeg) ## What This Board Does and Why It Matters LVDS is the signaling standard of choice inside many industrial computing backplanes: it is fast, low-power, and differentially encoded to reject common-mode noise. The problem is that LVDS is inhere --- ## FPGA-based CPCI Pulse Board for Rail Transit 6U Chassis - URL: https://intl.sienovo.cn/blog/146314695 - Date: 2025-03-17 - Tags: #fpga开发, #人工智能, #大数据, #边缘计算, #运维 Rail transit drive systems demand extreme reliability, deterministic timing, and immunity to electrical noise — requirements that make FPGA-based control hardware the natural choice over general-purpose microcontrollers. This post covers Sienovo's FPGA-based CPCI Pulse Board for 6U chassis deployments, detailing its architecture, signal chain, and the engineering rationale behind its key design choices. ![Pulse Board Front View](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146314695/01_2d8c5658985de8b9497edc90de3d56fb.jpeg) ## What a Pulse Board Does in a Traction Drive System In a rail transit variable-frequency drive (VFD) system, the pulse board sits between the host CPU (typically running a supervisory control application on a companion processor board) and the inverter power module that drives the traction motors. Its job is tightly scoped but timing-critical: 1. **Receive control commands** from the CPU over the backplane bus. 2. **Execute control algorithms** — t --- ## Rail Transit DSP+FPGA Main Control Board (6U) Supporting Logic Control, Data Processing, Communication Management, System Safety Protection Switching, and Other Functions - URL: https://intl.sienovo.cn/blog/146314601 - Date: 2025-03-17 - Tags: #fpga开发, #arm开发, #架构, #人工智能 Rail transit control systems demand hardware that is simultaneously deterministic, fault-tolerant, and able to bridge high-speed optical interconnects with rugged field-bus protocols — all within the tight mechanical envelope of a 6U CompactPCI chassis. This post walks through the architecture and interface complement of a production-grade DSP+FPGA main control board designed specifically for that application, covering its logic-control role, communication topology, safety-switching capability, and the engineering trade-offs embedded in its specification. ## Role of the Main Control Board In a rail-transit electronic control unit (ECU) rack, the main control board is the system's nerve center. It owns four distinct responsibilities: - **Logic control** — executing deterministic, scan-cycle control logic that governs traction, braking, door, and auxiliary subsystems. - **Data processing** — aggregating sensor data from I/O modules, running diagnostics, and computing set-points for do --- ## Rail Transit CPU+FPGA Controller, Supporting Real-time Operating Systems like CoDeSys/VxWorks/SylixOS - URL: https://intl.sienovo.cn/blog/146314511 - Date: 2025-03-17 - Tags: #fpga开发, #arm开发, #架构, #人工智能 ![e16acd84979949689fe6cdd5b7c05f1.png](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146314511/01_8f6422fb24ed891a9ede19aeeda8584e.png) ### 1. **Controller Advantages** 1) Powerful features and comprehensive supporting software (includes CoDeSys 3.5, compliant with IEC 61311-3 standard; real-time operating system VxWorks 7.0; and standard PTU software), facilitating secondary development and maintenance; 2) Rich interface resources (7 Ethernet ports, 2 CAN-FD ports, 6 CAN 2.0 ports, 2 UART ports, 1 SATA port) and high integration, which can reduce costs by 30% to 50%; 2) High reliability, already widely applied in the rail transit sector; 3) Easily integrated into customer products, helping customers reduce development and product costs, and rapidly launch products; 4) Customizable development available. ### 2. **Product Introduction** The controller, serving as the core and brain of the system, adopts a "CPU+FPGA" combined architecture. It possesses powerful data p --- ## NXP+FPGA+QNX-Based Rail Transit 6U Chassis Vehicle Control Unit (VCU) - URL: https://intl.sienovo.cn/blog/146250004 - Date: 2025-03-14 - Tags: #fpga开发, #边缘计算, #人工智能, #大数据, #嵌入式硬件 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146250004/01_3f82a91a2a4a4aabb33f234819b32ba8.png) Modern rail transit systems demand onboard intelligence that can handle real-time control, safety-critical decision-making, and comprehensive diagnostics — all within the harsh vibration, temperature, and EMI environment of a moving train. The NXP+FPGA+QNX-based 6U chassis Vehicle Control Unit (VCU) described here is purpose-built for exactly that role. This post walks through the architecture, application scope, communication interfaces, I/O capabilities, and operating envelope of this platform, giving engineers a clear picture of where and how it fits into a modern rail vehicle network. ## What Is a VCU and Why Does It Matter? The Vehicle Control Unit sits at the top of a train's onboard control hierarchy. Unlike individual subsystem controllers — which manage a single door module or a single HVAC zone — the VCU provides train-wide supervisory control and diagnostics. It --- ## NXP+FPGA-based Permanent Magnet Synchronous Motor Traction Control Unit (Single-Board / Chassis Structure) - URL: https://intl.sienovo.cn/blog/146249949 - Date: 2025-03-14 - Tags: #fpga开发, #边缘计算, #人机交互, #嵌入式硬件, #人工智能 Permanent Magnet Synchronous Motor Traction Control Unit (Single-Board / Chassis Structure) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146249949/01_bcf3674a22d3448b841a1960562c9ce0.png) The Permanent Magnet Synchronous Motor Traction Control Unit (TCU-PMSM) is used in traction electric drive systems composed of traction inverters and PMSMs, employing an axle control method. It implements high-performance PMSM complex vector control strategies, featuring rapid response, effective and reliable anti-slip/slide control functions, and smooth, impact-free speed-based re-engagement technology. Maximum Torque Per Ampere (MTPA) Control and Field Weakening Control The control objectives for PMSMs in rail transit applications are: to control the traction motor to provide sufficiently large torque; and to control the traction motor to expand the speed regulation range while maintaining a constant voltage. Based on the operating characteristics of the PMSM, its operating region --- ## NXP+FPGA-Based Rail Transit 3U Chassis Structure Remote Input/Output Module (RIOM) - URL: https://intl.sienovo.cn/blog/146249895 - Date: 2025-03-14 - Tags: #fpga开发, #人工智能, #大数据, #边缘计算, #运维 ## NXP + FPGA-Based Rail Transit 6U Chassis Remote Input/Output Module (RIOM) ![RIOM Module](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146249895/01_b81499e9681a428aa1674282778c2a4e.png) Modern rail transit systems — metros, light rail, and mainline trains — demand reliable, low-latency data acquisition and actuation distributed across the entire consist. Wiring every sensor and actuator directly back to a central Vehicle Control Unit (VCU) is neither practical nor cost-effective: cable runs grow heavy, harness complexity multiplies fault points, and maintenance becomes a significant operational burden. The Remote Input/Output Module (RIOM) solves this by placing intelligent I/O concentration at the point of need, close to sensors and actuators, and communicating with the VCU over a fieldbus network. This article covers an NXP + FPGA-based RIOM designed for 6U chassis integration in rail transit rolling stock, detailing its architecture, interface options, configurable --- ## DSP+ARM+FPGA-Based Rail Transit 6U Chassis Structure Traction Control Unit (PCIe) - URL: https://intl.sienovo.cn/blog/146249704 - Date: 2025-03-14 - Tags: #fpga开发, #arm开发, #架构, #人工智能, #大数据 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146249704/01_d44b7cdc72d44b6ca974e17c68cde465.png) The hardware system of the Traction Control Unit (TCU) is a multi-processor-based embedded system. This system fully integrates the powerful computational and logical processing capabilities of Digital Signal Processors (DSP), embedded processors (PowerPC, ARM), embedded microcontrollers (MCU), and FPGAs. Combined with a real-time operating system, a single TCU can achieve control of up to 4 sets of rectification/inversion. Its configuration can also be flexibly adjusted according to actual product applications. The architecture of a typical configuration is as follows: ![qianyin1.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146249704/02_6f80dcab6d5788e4f1ffc8bc20d32d58.jpeg) Key Features: ▶ Independent hardware configuration for rectification control and inversion control (DSP + ADI + PIO); ▶ CPCI bus – for high-speed communication between MCPU, NETI, DS --- ## NXP+FPGA-Based Rail Transit 3U Chassis Structure Logic Control Unit (LCU) - URL: https://intl.sienovo.cn/blog/146249492 - Date: 2025-03-14 - Tags: #FPGADev, #ARMDev, #Architecture, #AI, #BigData NXP+FPGA-Based Rail Transit 3U Chassis Structure Logic Control Unit (LCU) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146249492/01_8364c652e4d346a08c82ebe0c96f687e.png) The Logic Control Unit (LCU) is a digital logic control device specifically designed for applications in rail transit environments. It is used to replace hardwired relay circuits in train control and implement their corresponding logic control functions. Modular The LCU device adopts a modular design, mainly composed of an IO controller, a main controller, and a network controller. It collects DC110V signals from the driver's controller, push-button switch groups, disconnectors, contactor auxiliary contacts, etc., and after logical calculation, outputs to drive various vehicle loads, completing specified sequential control functions. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146249492/02_acf26e453ef64d0c8f67fcebc08b733c.png) Contactless Control The introduction of contactless co --- ## NXP+FPGA-Based Rail Transit 3U Chassis Traction Control Unit - URL: https://intl.sienovo.cn/blog/146249259 - Date: 2025-03-14 - Tags: #fpga开发, #边缘计算, #人工智能, #大数据, #嵌入式硬件 NXP+FPGA-Based Rail Transit Asynchronous Motor Traction Control Unit (TCU-IM) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146249259/01_86001f7758e542fa90b18013cc2acae2.png) The Asynchronous Motor Traction Control Unit (TCU-IM) is used in traction electric drive systems composed of traction inverters and asynchronous motors, and can be implemented in vehicle-mounted or rack-mounted configurations. It executes high-performance asynchronous motor complex vector control strategies, featuring rapid response, effective and reliable anti-slip/slide control functions, and smooth, shock-free speed-based re-engagement technology. Sensorless Control By utilizing speed observer algorithms, accurate rotational speed and rotor position are estimated. In practical applications, this eliminates the need for speed sensors, reducing costs and minimizing potential failure points. Field Weakening Control Considering inverter output voltage and motor current constraints, as well as ma --- ## NXP+FPGA-Based Rail Transit Human-Machine Interface (HMI) and Prognostics and Health Management (PHM) Unit Solution - URL: https://intl.sienovo.cn/blog/146249018 - Date: 2025-03-14 - Tags: #人机交互, #边缘计算, #嵌入式硬件, #人工智能, #fpga开发, #大数据 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146249018/01_09d3bb35443645ddbaa25be76d553fc6.png) The Human-Machine Interface (HMI) is an interactive display device used for interactive information display for drivers and crew. It can also be used for CCTV monitoring. While supporting connections for various interface devices, its embedded Linux system can meet customers' customized requirements. Key Features Touch buttons are located around the display area, offering excellent durability with no mechanical wear and tear, and are easy to configure as required. It can be customized as a full touchscreen, without touch control buttons around the display area. Built-in ultra-low-power quad-core processor, with a processing capability of up to 1.2 billion instructions per second, configured with a 2D/3D graphics and video acceleration processor engine, and an independent multimedia processor engine. Equipped with 2 high-speed RS232 serial ports and 2 opto-isolated high-s --- ## Train Control and Management System (TCMS), Rail Transit ARM+FPGA+AI Solution - URL: https://intl.sienovo.cn/blog/146248829 - Date: 2025-03-14 - Tags: #FPGADev, #AI, #BigData, #EdgeComputing, #DevOps ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146248829/01_757ee475890a44ae88e9d2ee7fa8a35a.png) Train Control and Management System (TCMS) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146248829/02_841b4ad75f304b42b681dc5af6792a12.png) The Low-Vacuum Tube Maglev Hyperloop Train (referred to as "Hyperloop Train"), a major national strategic project, has seen the establishment of the Hyperloop Train Laboratory by China Aerospace Science and Industry Corporation (CASIC) Third Academy and other entities.       The Hyperloop Train utilizes superconducting maglev technology to decouple from the ground, eliminating frictional resistance. The pipeline, which maintains a near-vacuum environment, significantly reduces air resistance, thereby achieving "near-ground flight" at speeds exceeding 1000 km/h. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146248829/03_f54e2d52befe4de5b0c8e98c8569cc2b.png) --- ## ARM+FPGA-Based High-End Servo Drive and Motion Control Solutions - URL: https://intl.sienovo.cn/blog/146154180 - Date: 2025-03-10 - Tags: #FPGADev, #ARMDev, #Architecture, #AI, #BigData #### ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146154180/01_5e3ae4d8834d4308b6ef754b4a78ebf5.png)**1. Real-time and Deterministic Requirements** The current loop of a servo system is the innermost control loop and must complete the following operations within **microseconds (μs)**: * **High-Speed Sampling**: Feedback signals from current sensors (e.g., Hall sensors or shunt resistors) need to be sampled at frequencies of **100 kHz to 1 MHz**. * **Fast Computation**: Real-time computation of PID or other advanced control algorithms (e.g., Model Predictive Control) to generate PWM signals that drive power devices (e.g., IGBTs or SiC MOSFETs). * **Low-Latency Response**: The delay from signal sampling to outputting control signals must be controlled within **1 to 5 μs**; otherwise, it can lead to motor torque ripple or loss of synchronization. **Advantages of FPGA**: * **Hardware Parallelism**: FPGAs can process multiple signals simultaneously --- ## Application of ZYNQ MPSoC + QNX Real-time System + CPCI Board in Rail Transit Modular Systems - URL: https://intl.sienovo.cn/blog/146087485 - Date: 2025-03-07 - Tags: #FPGADev ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146087485/01_c9501a1608a2400fb709658f75dcc856.png) ### Application of ZYNQ MPSoC + QNX Real-time System + CPCI Board in Rail Transit Modular Systems ### **Block Diagram** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146087485/02_f6920f1a079644d4b0469cd845718e35.png)   ### **Technical Specifications** — Dual Main Control Chips: XC7Z020-CLG484 and XC7VX690T-2FFG1761I; — Memory: \-XC7VX690T with 8x 16-bit 1600 DDR3 SDRAM (up to 4GB supported), maximum bandwidth up to 25.6GB/s; \-XC7Z020 with 2x 16-bit 1600 DDR3 SDRAM (up to 4GB supported), maximum bandwidth up to 6.4GB/s; \-Supports SPI Flash for program loading; \-Features eMMC interface (can also be used as I/O expansion for XC7Z020); Features SD card interface; — Communication and Networking \-Supports UART communication; \-Supports Ethernet communication; \-Supports USB2.0 OTG slave mode; — Configuration: JTAG program download via Micro USB in --- ## Domestic Alternative to NVIDIA Jetson Nano: Sophon BM1684X + FPGA + AI Compute Box, Supporting DeepSeek Edge Deployment - URL: https://intl.sienovo.cn/blog/146069843 - Date: 2025-03-06 - Tags: #AI, #EdgeComputing, #BigData, #EmbeddedHardware A domestic alternative to the NVIDIA Jetson Nano, an AI compute box based on Sophon BM1684X, supporting DeepSeek edge deployment. Additionally, a BM1684X + FPGA + AI solution is also available. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146069843/01_286cfceeb4a17028a1f77bc1fcdac300.png) The core board is built upon the **Sophon SG2300X** SoC (also known as BM1684X). ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146069843/02_287d5103ae1a96bbb0b6781f1b07c9f7.png) It features an **8-core ARM Cortex-A53 @2.3GHz**, with a very high clock speed. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/146069843/03_b50375a552daa8dde65d042d69ae0fde.jpeg) Equipped with a TPU (Tensor Processing Unit). Compute power reaches **32TOPS@INT8**, **16TFLOPS (FP16/BF16)**, and 2TFLOPS (FP32). Supports deep learning frameworks such as TensorFlow, Caffe, PyTorch, Paddle, ONNX, MXNet, Tengine, and DarkNet. ![图片](https://pub-048dcb96257f476697b113fcb5939 --- ## Zhaoxin ZX-C4500 Fully Domestically Produced Power Communication Management Unit Solution, Power Class 4 - URL: https://intl.sienovo.cn/blog/145970828 - Date: 2025-03-02 - Tags: #AI, #EdgeComputing, #FPGADev ‌**The Power Communication Management Unit Solution**‌ is a design and application scheme for communication management units in power systems, aiming to enhance the communication efficiency and stability of power systems. The Communication Management Unit (also known as DPU) features multiple downstream communication interfaces and one or more upstream network interfaces, acting as a front-end processor. It is used to collect and consolidate communication data from all intelligent monitoring/protection devices within a substation and transmit it in real-time to the upper-level master station system, fulfilling functions such as tele-signaling and tele-measurement. Simultaneously, it can receive commands issued by backend machines or DCS and forward them to intelligent series units within the substation to achieve tele-control and tele-adjustment functions‌12. China's Independently Developed Processor, Zhaoxin **ZX-C4500** Power Class 4 Dedicated Machine Compliant with the Chinese Ma --- ## [ARM+Codesys Customer Case] Application Case of RK3568/A40i/STM32+Codesys in Intelligent Manufacturing - URL: https://intl.sienovo.cn/blog/145905607 - Date: 2025-02-27 - Tags: #stm32, #codesys, #rk3568, #A40I Vegetables are essential foods in people's daily lives, and there are various ways to consume them. Since entering a moderately prosperous society, people's pace of life has become increasingly fast, and many traditional services can no longer meet people's material needs and pace of life. In daily life, the rapid manual cutting of vegetables seriously threatens personal safety. Factors such as long cutting time or unskilled cutting can easily lead to injury. In places with high demand for cutting vegetables such as canteens and food processing plants, it is safe and fast to process vegetables into various shapes. Relying solely on manual labor is both time-consuming and laborious. How to cut vegetables faster will become a very tricky problem. Replace manual labor with food processing machines or supplement it. This will increase the efficiency of cutting vegetables. Therefore, it is necessary to conduct research on vegetable cutting robots. ![](https://pub-048dcb96257f476697b113fcb --- ## Allwiner T527+FPGA Solution for Asynchronous LED Display Control Card/Screen Splicing - URL: https://intl.sienovo.cn/blog/145848127 - Date: 2025-02-25 - Tags: #FPGADev Allwiner T527+FPGA Solution for Asynchronous LED Display Control Card/Screen Splicing  T527+FPGA solution: Built in 8-core Cortex-A55, with a maximum clock speed of 1.8GHz; G57 MC1 GPU , 2Tops computing power NPU; At the same time, it is equipped with 1 x RISC-V+2 x DSP cores, with powerful 4K high-definition decoding performance, multiple display interfaces, 2 x Gigabit Ethernet ports, 4 x RS485 (5KV isolation, surge protection) and other interfaces. It can achieve 12 screen splicing, same display, and different display, and is compatible with multiple operating systems. It is widely used in exhibition display, advertising content placement, new retail, supermarkets and other fields to display various media content. T527 core board interface description: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145848127/01_981c5159c65d4fc59e2f65e2de1e21cb.png) Joint screen splicing It can achieve any horizontal and vertical screen splicing mode within 12 screens, achievin --- ## Fully Domestic Asynchronous LED Display Control Card / Video Wall Solution Based on Allwinner T527+FPGA - URL: https://intl.sienovo.cn/blog/145847963 - Date: 2025-02-25 - Tags: #FPGADev, #AI, #BigData, #EdgeComputing, #DevOps T527+FPGA Solution: Features an 8-core Cortex-A55, with a maximum frequency of 1.8GHz; a G57 MC1 GPU, 2 TOPS NPU; also integrates 1×RISC-V + 2×DSP cores, providing powerful 4K high-definition decoding performance, and is equipped with multiple display interfaces, 2×Gigabit Ethernet ports, 4×RS485 (5KV isolation, surge protection) and other interfaces. It can achieve video wall splicing of up to 12 screens, synchronized display, and asynchronous display, compatible with various operating systems, and is widely applicable in fields such as exhibitions, advertising content delivery, new retail, and supermarkets for displaying various media content. 　　**T527 Core Board Interface Description:** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145847963/01_f395e8e1249c4697ab501d89a29dced2.png) **Video Wall Splicing** 　　It supports arbitrary horizontal and vertical screen splicing modes for up to 12 screens, achieving pixel-perfect splicing effects. 　**Long Strip Screen Di --- ## Smart Service Robot Solution Based on Allwinner T536 + FPGA + AI - URL: https://intl.sienovo.cn/blog/145847462 - Date: 2025-02-25 - Tags: #FPGADev, #AI, #BigData, #DevOps, #Robotics, #EdgeComputing #### Service Robot Solutions For service robot scenarios, by leveraging [3D vision](https://so.csdn.net/so/search?q=3D%E8%A7%86%E8%A7%89&spm=1001.2101.3001.7020 "3D视觉") perception technology and self-developed [ASIC](https://so.csdn.net/so/search?q=ASIC&spm=1001.2101.3001.7020 "ASIC") chips, we enable high-precision 3D depth information acquisition. This empowers service robots with capabilities such as perception, obstacle avoidance, and navigation, making them widely applicable in commercial cleaning, food delivery, building delivery, warehousing and logistics, education and entertainment, among other fields. Xinmai has provided technical and product services to over 100 leading service robot brands, including Gaussian Robotics, Yunji Technology, and Pudu Technology.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145847462/01_27a769b690664cdb8c8ce25b4ec645c2.png) #### [3D Vision](https://so.csdn.net/so/search?q=3D%E8%A7%86%E8%A7%89&spm=1001.2101.3001.7020 "3D视觉") Emp --- ## RK3588+12 GPU Edge Computing Server Design Solution, Supporting 120-Channel High-Definition Video - URL: https://intl.sienovo.cn/blog/145796261 - Date: 2025-02-22 - Tags: #RK3588, #GPU, #BM1688 ## RK3588+12 GPU Edge Computing Server Design Solution, Supporting 120-Channel High-Definition Video The high-density server is an edge computing product with high performance and high computing power. It is equipped with an intelligent visual deep learning processor BM1688, and 12 computing units are optional. It supports intelligent analysis of 192 high-definition videos (hardware decoding) and hardware encoding of 120 high-definition videos; it also supports multiple Ethernet ports, HDMI, USB, and storage expansion. It can flexibly respond to high-concurrency business scenarios such as public security, transportation, industrial parks, manufacturing, and warehousing, and is equipped with diverse algorithms to empower various industries with intelligence. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145796261/01_f54bc843886e4454a660ae6deff8f852.png) | Type | Key Parameters | |---|---| | Product Name | High-Density Server | | Product Model | XM3588-BM1688 | | AI Co --- ## Software PLC Solution for RK3568+Codesys ARM+LINUX Hardware Platform - URL: https://intl.sienovo.cn/blog/145664825 - Date: 2025-02-16 - Tags: #linux, #Codesys, #RK3568 **CODESYS Control Linux ARM SL** A soft PLC that complies with the IEC 61131-3 standard and is suitable for ARM&Linux hardware platforms. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145664825/01_5647854beba04bf197de8a9a1a983141.png) **Product Description** CODESYS Control Linux ARM SL is a CODESYS Runtime designed for ARM&Linux hardware platforms. The functionality of Runtime can be extended through the hardware properties of the system. After installing the included CODESYS deployment tool plugin in CODESYS IDE, users can install the product on the Linux operating system of the target controller through CODESYS IDE. After each restart, the CODESYS Runtime will automatically start. CODESYS Runtime supports running for two hours without any functional restrictions without authorization. **Product Features** CODESYS Runtime supports rich I/O interfaces, such as local I/O or bus type I/O, and supports an integrated IEC 61131-3 protocol stack. Fieldbus can be confi --- ## RK3576/RK3588+FPGA+AI Service Robot Solution - URL: https://intl.sienovo.cn/blog/145662856 - Date: 2025-02-16 - Tags: #AI, #RK3588, #STM32, #ROBOTICS ## RK3576/RK3588+FPGA+AI Service Robot Solution ### Introduction This article explores the RK3576/RK3588+FPGA+AI Service Robot Solution, a cutting-edge technology that leverages 3D visual perception and self-developed ASIC chips to empower service robots in various industries. By understanding this solution, readers will gain insights into the applications, benefits, and potential of this technology in fields such as commercial cleaning, catering delivery, and education. ### Service Robot Solution For service robot scenarios, leveraging 3D visual perception technology and self-developed ASIC chips, high-precision 3D depth information acquisition is achieved to assist service robots in performing functions such as perception, obstacle avoidance, and navigation. This technology can be widely applied in commercial cleaning, catering delivery, building delivery, warehousing logistics, and education and entertainment sectors. Xinmai has provided technology and product services to over --- ## Intelligent Analysis Design and Implementation of Health Status for High-Speed Rail Equipment Based on NXP IMX8 + FPGA + PHM Technology (Part Two) - URL: https://intl.sienovo.cn/blog/145613024 - Date: 2025-02-13 - Tags: #Robotics, #AI, #BigData, #DevOps 2.1.1 Basic Concepts of PHM for High-Speed Rail Equipment This article first clarifies the basic concepts in the field of PHM for high-speed rail equipment. Sensor: A device or apparatus capable of sensing relevant information from a specified measurand and converting it into a usable output signal according to certain rules, typically composed of a sensitive element, a transducer, and a measurement circuit [61]. Fault: A state of a product characterized by its inability to perform its required function. That is, a fault is a state caused by a failure [62]. Health: Concise information about the current ability of a system, subsystem, or component to perform its specified functions; it is a general term for the good state of an object. The health status of a general product cannot be directly observed and therefore requires evaluation. Health Monitoring: The process of evaluating a system's health status, including the measurement of state parameters and the identification of abnormal --- ## Intelligent Health Status Analysis Solution for High-Speed Rail Equipment Based on NXP IMX8 + FPGA + PHM Technology (Part 1) - URL: https://intl.sienovo.cn/blog/145612884 - Date: 2025-02-13 - Tags: #AI, #EmbeddedHardware, #EdgeComputing Currently, the prevailing maintenance strategy for high-speed rail rolling stock in China is predicated on Time-Based Maintenance (TBM), with the gradual implementation of Condition-Based Maintenance (CBM), component replacement, and centralized repair of major components [1]. China's high-speed rail maintenance model is transitioning from traditional "Time-Based Maintenance" to "Condition-Based Maintenance." As PHM is an advanced development of condition-based maintenance, it can enhance the safety of high-speed trains, accelerate the optimization of maintenance strategies, alleviate heavy maintenance workloads, and reduce maintenance costs. Therefore, utilizing PHM for analyzing the health status of high-speed trains is a meaningful and important research endeavor. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145612884/01_001ce22377684098add6660034524ae8.jpeg)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145612884/02_04b4db724964480b9dc0b2bdbd011d98. --- ## [PHM] Smart Maintenance Technology based on TI AM62X+FPGA+PHM for Wind Turbine Monitoring Applications - URL: https://intl.sienovo.cn/blog/145612529 - Date: 2025-02-13 - Tags: #Networking ### I. Introduction to Smart Maintenance Technology #### 1. Development and Challenges of Smart Maintenance Technology (Background of PHM Technology) The goal of smart maintenance is to solve problems encountered in manufacturing, including equipment downtime, component damage, poor quality, and low energy utilization. To solve these problems, we cannot start from their superficial manifestations, but rather focus on their underlying causes, which we generally refer to as "invisible problems." Invisible problems include component wear, corrosion, leakage, human error, and even environmental factors. These factors can manifest in various ways, often coupling, interacting, and jointly contributing to failures. In such situations, we must address these problems at their source. To avoid these issues, it is necessary to utilize monitoring, analysis, and even decision support tools. So, how can we prevent invisible problems from occurring? A crucial aspect is prediction.![](https://pub-048 --- ## [PHM] NXP IMX8 + FPGA + PHM Smart Maintenance Technology for Rail Transit and Marine Applications - URL: https://intl.sienovo.cn/blog/145612234 - Date: 2025-02-13 - Tags: #Networking, #AI, #DevOps, #EdgeComputing, #FPGADev ### The Evolution and Challenges of Smart Maintenance Technology 1. Maintenance Goals Regarding the background of PHM technology, we know that one goal of maintenance is to solve problems in manufacturing. These problems include equipment downtime, component damage, poor quality, and even low energy efficiency utilization or waste. To solve these problems, we cannot merely address their superficial manifestations, but must focus on their underlying causes. These causes are often invisible issues hidden behind the apparent problems, such as wear, corrosion, leaks in parts, or poor human operation, and environmental factors. These factors can manifest in various ways, often coupled and interacting, ultimately leading to failures. In such situations, it is crucial to address the root causes to prevent these problems. Therefore, the ultimate goal of maintenance is not just to detect failures, but to resolve and prevent them. This involves using monitoring analysis and even decis --- ## x86+FPGA-Based Solution for Digital Medical Devices - URL: https://intl.sienovo.cn/blog/145611951 - Date: 2025-02-13 - Tags: #EmbeddedHardware, #FPGADev, #AI, #stm32 ## Digital Medical Devices ![医疗数字设备](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145611951/01_be2794150e74c28979bcd6bf2a95cc48.jpeg) **Digital Healthcare** is far more than a simple collection of digitized medical equipment; it is a new, modern approach to healthcare that applies contemporary computer and information technology to the entire medical process. With digital healthcare, patients can complete appointments with minimal procedures, doctors' diagnostic accuracy is significantly improved, and patient medical records archive all current and historical patient health information, greatly facilitating doctor diagnoses and patient self-checks. It truly enables the comprehensive patient data retrieval required for remote consultations, providing fast, effective services. Another major advantage of digital healthcare is the ability to share resources between medical equipment and medical experts. For medical institutions, a comprehensive health information database le --- ## X86+FPGA-Based Smart Rail Transit Solution, Rail Switch, PHM Data Acquisition Card - URL: https://intl.sienovo.cn/blog/145611888 - Date: 2025-02-13 - Tags: #AI, #Networking, #BigData ## Smart Rail Transit ![智能轨道交通](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145611888/01_32a9b97f9b6605df65a8f93831261473.jpeg) ![智能轨道交通](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145611888/02_8ca98c379290449420879ce2100bf36b.jpeg) Urban rail transit includes various types such as subways, light rail, trams, and maglev trains. Smart urban rail transit systems include the Integrated Monitoring System, Passenger Information System, Integrated Security System, Communication System, Automatic Fare Collection System, and Signaling System. **I. Integrated Monitoring System** It is a large-scale computer integrated system based on modern computer technology, network technology, automation technology, and information technology. The system integrates and interconnects multiple specialized subway automation subsystems, primarily integrating the Environmental and Equipment Monitoring System, Power Monitoring System, and Automatic Fire Alarm System, and interconn --- ## X86+FPGA+STM32 MCU-based Robot Controller and AGV Forklift Controller Solution - URL: https://intl.sienovo.cn/blog/145610896 - Date: 2025-02-13 - Tags: #Robotics The XM-6830 is a 3.5″ embedded industrial motherboard developed with a 175×133mm footprint. This motherboard integrates Intel's latest high-performance quad-core/eight-thread processor. The board features an HDMI display output interface, 4 RJ45 10/100/1000Mbps adaptive Ethernet network interfaces, support for 4 serial ports with optional RS232/RS485 transceiver modes, 3 USB 3.0 ports, 1 USB 2.0 port, 1 M.2 interface for Wi-Fi/Bluetooth functionality, 1 M.2_5G slot, 1 Nano SIM card slot, 1 PCIe_CAN interface, 1 push-button switch, a 65536-level watchdog timer, 54-channel digital input/output (DIO), DDR4 dual-channel slots supporting up to 64GB of memory, and one mSATA slot. Leveraging Intel's latest Tiger Lake platform, this series of ultra-high-performance CPUs enables the EB-6830 to operate within an ambient temperature range of -20 to 70℃. The onboard CPU enhances system stability and reliability. An 8-layer PCB stack-up design enhances its capabilities in terms of electromagnet --- ## Application of 360-Degree Surround View in Unmanned Substations - URL: https://intl.sienovo.cn/blog/145583817 - Date: 2025-02-12 - Tags: #AI **Application of 360-Degree Surround View in Unmanned Substations** This system uses software algorithms to synthesize images from four outdoor fisheye lenses into a seamless panoramic image, which is then overlaid with a virtual 3D substation model. This composite image is transmitted in real-time via video signal to the central control display. The greatest innovation of this technology is that users can create custom viewpoints, i.e., custom virtual cameras. The system can freely and dynamically switch perspectives, intelligently emphasizing images of different areas around the substation during both static and dynamic processes. Simultaneously, this system also functions as a remote monitoring system, providing users with 24/7 monitoring records, comprehensive and blind-spot-free monitoring assistance from all angles, and other features. It is a high-tech smart hardware product integrated with AI. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145583817/01_268c4a93 --- ## RK3588 + 12-Way Sophon BM1688 Edge AI Server Design Solution, Supporting 120 Channels of HD Video - URL: https://intl.sienovo.cn/blog/145549203 - Date: 2025-02-10 - Tags: #Server, #DevOps, #SignalProcessing, #FPGADev This high-density server is a high-performance, high-compute edge computing product, equipped with the intelligent visual deep learning processor BM1688, and optionally configurable with 12 compute units. It supports intelligent analysis of 192 channels of HD video (hardware decoding) and hardware encoding of 120 channels of HD video. It supports multiple network ports, HDMI, USB, and storage expansion. It can flexibly handle high-concurrency business scenarios such as public security, transportation, smart parks, manufacturing, and warehousing. Paired with diverse algorithms, it empowers smart solutions across various industries.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145549203/01_aada455cbe734235a9e15b48cd57effb.png)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145549203/02_85dbfe0182a7436d9a2ecc4261cf6567.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145549203/03_ead5d7ceaa3a42d6b6dfb70d50cb56d1.png) ****Category**** ****Ke --- ## RK3588 + Multi-Channel Sophon BM1688 Intelligent Mining All-in-One Machine, Supporting Various Coal Mine Algorithms - URL: https://intl.sienovo.cn/blog/145548964 - Date: 2025-02-10 - Tags: #AI The Intelligent Mining All-in-One Machine is centered on preventing and mitigating major safety risks, fully leveraging the advantages of edge-side video intelligent recognition technology. Tailored for mining scenarios, it provides intelligent capabilities such as safety supervision, equipment monitoring, and disaster early warning. The product fully complies with the technical guidelines and acceptance standards for intelligent video system construction in mining scenarios. The Intelligent Mining All-in-One Machine adopts the latest domestic high-performance NPU intelligent chip, possessing server-grade compute power performance with strong scalability, reaching up to 768 TOPS. It integrates high-precision AI intelligent algorithms and a comprehensive video intelligence management platform, capable of intelligently identifying and accurately assessing unsafe behaviors of personnel, unsafe equipment statuses, and unsafe environmental factors in mines. It also features data fusion an --- ## Research on Multi-Image Sensor Fusion Detection Method for Large Truck Blind Spot Targets Based on RK3588 - URL: https://intl.sienovo.cn/blog/145438628 - Date: 2025-02-04 - Tags: #FPGADev, #EmbeddedHardware, #AI With the increasing prominence of road traffic safety issues, the technical demand for large truck blind spot monitoring has urgently risen. This paper proposes an innovative blind spot monitoring method that combines a lightweight deep learning model with multi-image sensor data fusion technology, conducting in-depth research and practical application for large truck blind spot monitoring. By introducing an improved YOLOv5 algorithm, modifying the loss function to SIoU, and integrating Ghostnet modules, BiFPN, and CA attention mechanisms, and by combining the Bdd100k dataset with a self-built dataset for model training and testing, the proposed improved YOLOv5 algorithm reduced model size by 15.9%, increased detection accuracy by 0.6% compared to the original YOLOv5 model, achieving an average precision of 77%, and improved inference speed by 4 FPS. This validates the effectiveness of the improved algorithm, as it slightly enhanced detection accuracy and inference speed while maintai --- ## System Design of a Six-Degree-of-Freedom Robotic Arm for Inspection Robots Based on RK3588/RK3576+FPGA - URL: https://intl.sienovo.cn/blog/145438501 - Date: 2025-02-04 - Tags: #Robotics Nowadays, robotic arms of inspection robots operating in complex environments such as utility tunnels often face problems of narrow spaces and dense obstacles. This requires the robotic arm to possess the ability to perform obstacle avoidance path planning in confined spaces. Furthermore, uncertain factors, such as difficulty in perceiving the global state information of the robotic arm under sudden or abnormal environmental conditions, can introduce new challenges to obstacle avoidance. In response to these issues, this paper primarily focuses on the following research points: (1) Addressing the problem of obstacle avoidance for robotic arms in narrow spaces, this paper proposes an improved RRT\* algorithm. This algorithm primarily introduces a greedy strategy into the node expansion guidance mechanism of the original algorithm, performing goal-oriented node expansion with a certain probability. Compared to the original algorithm, the improved algorithm significantly reduces time sp --- ## Design and Implementation of a Battery Cluster Management System for Energy Storage Power Stations Based on RK3588/RK3576 + STM32 MCU + AI - URL: https://intl.sienovo.cn/blog/145438296 - Date: 2025-02-04 - Tags: #SmartTV, #stm32, #AI, #EmbeddedHardware, #EdgeComputing With the high-quality and large-scale development of new energy storage technologies in recent years, energy storage power stations, as important carriers in the new energy sector, aim to facilitate the gradual transition into the era of smart grids and meet the innovative upgrade requirements for the energy structure and distribution of power systems. This poses new challenges for the design and implementation of battery management systems of corresponding scale. Meanwhile, the concept of edge-cloud collaborative design for electronic systems has become very mature. Facing the demand for highly safe, stable, and long-term operation of energy storage power stations, the functional architecture division between edge and cloud needs further refinement, and achieving high-performance computing at the edge has become an innovative embedded solution for the design of Battery Management Systems (BMS) in energy storage power stations. This paper focuses on the Battery Cluster Management Uni --- ## Cloud PC/Cloud Phone System Design and Implementation Based on RK3588 + Sophon BM1684X - URL: https://intl.sienovo.cn/blog/145438170 - Date: 2025-02-04 - Tags: #FPGADev, #AI, #BigData, #EdgeComputing ## Cloud PC / Cloud Phone System Design and Implementation Based on RK3588 + Sophon BM1684X A cloud PC is a comprehensive service solution that bundles cloud-side compute resources, a lightweight transmission protocol, and a thin-client terminal into a single deployable unit. Rather than packaging a CPU, RAM, and storage inside the box itself, the hardware lives in the cloud and is shared elastically across users. The thin client's only job is to encode local input events, ship them upstream, and decode the resulting video stream back to the display. This article walks through the hardware architecture, PCB design constraints, and the dual-mode signal-processing pipeline that make such a system practical on Rockchip RK3588 silicon — then closes with a look at the follow-on RK3576-based AIOT platform that adds an integrated 6 TOPS NPU for on-device AI inference. --- ## 1 Overall System Architecture The main controller is the **Rockchip RK3588**, paired with a **Realtek RTL8822CU** --- ## Research on Foreign Object Detection Technology for Railway Tracks Based on RK3576/RK3588 + FPGA + AI Deep Learning - URL: https://intl.sienovo.cn/blog/145295286 - Date: 2025-01-22 - Tags: #AI, #DeepLearning With the rapid development of high-speed rail technology, foreign object intrusion on railway tracks has become a critical factor affecting train operational safety. There is an urgent need for rapid identification of foreign objects on tracks to ensure safe train operation. Traditional foreign object detection methods suffer from issues such as insufficient detection accuracy and low efficiency. Based on a comprehensive analysis of domestic and international research on railway foreign object intrusion, this paper proposes a novel foreign object detection method for railway tracks. It completes key technical tasks such as image preprocessing, track region extraction, and detection model design, thereby improving the speed and accuracy of foreign object detection on tracks. The main contributions of this paper are as follows: To address issues such as detail loss and feature blurring in images or videos caused by noise, fog occlusion, and other factors, this paper conducts image prepr --- ## PLC Design Based on RK3576+FPGA+AI with Deep Learning Capabilities - URL: https://intl.sienovo.cn/blog/145294424 - Date: 2025-01-22 - Tags: #AI Introduction With the continuous advancement of the great trend of Artificial Intelligence (AI), more and more fields are leveraging AI to drive industrial upgrading and improve the efficiency of products or projects. In industrial control applications, the demand for automation is also increasing, and in many scenarios, there is an urgent desire for the introduction of AI technology to bring about product performance improvements. This is especially true in areas such as factory manufacturing lines and industrial robots, where AI technology is often needed to enhance the efficiency of image recognition and fault analysis \[1~3\]. On the other hand, industrial control emphasizes product stability and the convenience of product programming applications. How to simultaneously meet the application needs of both aspects is a direction the industry is currently striving for. Currently, there are two common modes: (1) Directly developing AI algorithms, performing AI computations, and pro --- ## RK3576/RK3588+FPGA+AI Service Robot Solution - URL: https://intl.sienovo.cn/blog/145185012 - Date: 2025-01-16 - Tags: #FPGADev, #AI, #Robotics ### Service Robot Solutions For service robot scenarios, based on [3D vision](https://so.csdn.net/so/search?q=3D%E8%A7%86%E8%A7%89&spm=1001.2101.3001.7020 "3D vision") perception technology, we achieve high-precision 3D depth information acquisition through self-developed ASIC chips, empowering service robots with functions such as perception, obstacle avoidance, and navigation. This can be widely applied in commercial cleaning, food delivery, building delivery, warehousing and logistics, education and entertainment, and other fields. Xinmai has provided technology and product services to over 100 leading service robot brands, including Gaussian Robotics, Yunji Technology, and Pudu Technology.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/145185012/01_27a769b690664cdb8c8ce25b4ec645c2.png) ### 3D Vision Empowerment: One Cleaning Vehicle Frees Up Three Workers Artificial intelligence is entering an explosive period of deep integration with industries and applications. --- ## RK3568/RK3588-based 360-Degree Surround View Active Safety Driving Assistance System Solution for Heavy-Duty Vehicles, Supporting ADAS/DMS - URL: https://intl.sienovo.cn/blog/144993851 - Date: 2025-01-07 - Tags: #AI, #BigData, #EdgeComputing ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144993851/01_88062d2d8ae84fdb9aeb6c73ae6abe37.png) * ******Product Design Philosophy****** The HS-P2-2D is a 360-degree panoramic imaging system developed to address blind spots in heavy-duty vehicles. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144993851/02_2e46d30561094659a56875d38ae34517.png) This safety driving assistance system uses ultra-wide-angle cameras installed around the vehicle to synthesize a panoramic bird's-eye view via algorithms. The bird's-eye view allows drivers to clearly see the surroundings of the vehicle, greatly reducing traffic accidents caused by blind spots. * ******Product Features****** 1. A 360-degree panoramic imaging system specifically developed for trucks and special vehicles, featuring proprietary 360-degree stitching algorithms for heavy-duty vehicles, a compact size, high integration, and a wide-temperature design, with an operating temperature range of -30°C --- ## Applications of RK3588, Kylin Domestic OS, FPGA, and AI in Vision and Acquisition Systems for Power and Rail Transit - URL: https://intl.sienovo.cn/blog/144913858 - Date: 2025-01-03 - Tags: #MCU, #stm32, #EmbeddedHardware The main functions provided by industrial visual recognition system manufacturers include: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144913858/01_968689a713419663f13cd8690acafa96.jpeg) These manufacturers utilize advanced visual recognition technology to achieve image acquisition, processing, and analysis. The systems can automatically complete tasks such as quality inspection, material sorting, and equipment monitoring, significantly improving production efficiency and product quality. At the same time, the systems offer high flexibility and scalability, allowing for customized development based on customer needs to meet the visual recognition requirements of various industries. Furthermore, these manufacturers also provide comprehensive technical support and after-sales service to ensure stable system operation and continuous optimization. Some industrial visual recognition system manufacturers choose to use RK3588 motherboards paired with Kylin domestic operat --- ## Power Applications Based on TI AM62X/AM64X + FPGA + AD7606/ADS8568 Multi-channel ADC Acquisition - URL: https://intl.sienovo.cn/blog/144913194 - Date: 2025-01-03 - Tags: #FPGADev Power Applications Based on TI AM62X/AM64X + FPGA + AD7606/ADS8568 Multi-channel ADC Acquisition ● Similar to asynchronous SRAM memory and dedicated ASIC devices. ● Asynchronous, synchronous, and page mode (only for non-multiplexed mode) burst NOR flash devices. ● NAND flash. ● ADC devices. ![bafd1d16-1952-11ed-ba43-dac502259ad0.png](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144913194/01_83872ef1c89526ec871acea37c84a0cc.png) Figure 1 GPMC Overview **2 GPMC Parallel Interface Features** Why do industrial applications prefer using the GPMC interface when communicating with FPGAs/ADCs? This article provides 3 reasons: **high bandwidth, rich connection modes, and flexible configuration**. Specifically, they are as follows: PS: The following will introduce an ARM + FPGA communication case based on AM570x GPMC, and a comprehensive multi-channel AD (AD7606/ADS8568) acquisition case. **(1) High Bandwidth, Speeds Exceeding 100MB/s** Taking AM57x as an example, when co --- ## RK3588+FPGA Fully Domestic Asynchronous LED Display Control Card / Video Wall Solution - URL: https://intl.sienovo.cn/blog/144912676 - Date: 2025-01-03 - Tags: #FPGADev The RK3588+FPGA core module features Rockchip RK3588, a new-generation flagship octa-core 64-bit processor. It supports 8K video encoding and decoding, multi-screen 4K output, and can achieve 12-screen video wall splicing, simultaneous display, and differentiated display. Compatible with various operating systems, it is widely applicable in fields such as exhibitions, advertising content delivery, new retail, and supermarkets for displaying various media content. 　　**RK3588 Core Module Interface Description:** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144912676/01_f395e8e1249c4697ab501d89a29dced2.png) **Video Wall Splicing** 　　Supports arbitrary horizontal and vertical splicing modes for up to 12 screens, achieving pixel-to-pixel splicing effects. 　**Bar-type Screen Display Effect** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144912676/02_c52a834d9816e2ecdda16ea8d4bb9b63.png) 　**Vertical Bar Screen Display Effect** ![](https://pub-048dcb9625 --- ## Domestic Alternative to NI: FPGA-based 4-Channel Voltage 250 MSPS Edge Computing Acquisition Board, Supporting Loongson/Phytium Host Processors - URL: https://intl.sienovo.cn/blog/144693519 - Date: 2024-12-24 - Tags: #EdgeComputing, #AI ## Domestic Alternative to NI: FPGA-based 4-Channel Voltage 250 MSPS Edge Computing Acquisition Board, Supporting Loongson/Phytium Host Processors In the realm of edge computing, high-speed data acquisition boards play a crucial role in various industrial applications. National Instruments (NI) has long been a dominant player in this space, but with the rise of FPGA-based solutions, alternatives have emerged. This article will delve into a domestic alternative to NI's offerings: a 4-channel voltage 250 MSPS edge computing acquisition board powered by an Arria 10 SoC FPGA, specifically designed to support Loongson and Phytium host processors. ### Overview of the Board The board in question leverages the Arria 10 SoC FPGA, a highly capable device capable of achieving a maximum sampling rate of 250 MSPS. This makes it an ideal choice for applications requiring high-speed data acquisition and processing. The board's primary function is to provide a hardware platform for high-speed compu --- ## [Domestic NI Alternative] FPGA+AI-based 2-Channel Voltage 80M Sampling (16-bit) PCIe Data Acquisition Card, Supporting Phytium/Loongson Host Processors - URL: https://intl.sienovo.cn/blog/144693444 - Date: 2024-12-24 - Tags: #FPGADev, #ARMDev, #EdgeComputing, #AI ## Overview of the 2-Channel Voltage 80M Sampling PCIe Data Acquisition Card In this article, we will explore the features and capabilities of a specialized data acquisition card designed for industrial applications. This card utilizes an XC7A100T-2FGG484I FPGA and offers a maximum sampling rate of 80 million samples per second (80M). It is particularly suited for integration with industrial PCs and standard computer hosts, making it a versatile choice for various data acquisition tasks. ## Key Features ### High-Speed Sampling The card is capable of sampling voltage signals at an impressive rate of 80M, which is essential for applications that require rapid data collection. This high sampling rate allows for precise monitoring and analysis of dynamic signals, making it suitable for a range of industrial applications. ### FPGA Technology At the heart of this acquisition card is the XC7A100T-2FGG484I FPGA. FPGAs (Field-Programmable Gate Arrays) are known for their flexibility and p --- ## Chinese-made NI Alternative: FPGA-based 2-Channel 50 MS/s USB 3.0 Voltage Data Acquisition Card - URL: https://intl.sienovo.cn/blog/144693346 - Date: 2024-12-24 - Tags: #FPGADev ## Chinese-made NI Alternative: FPGA-based 2-Channel 50 MS/s USB 3.0 Voltage Data Acquisition Card In this article, we will explore a Chinese-made alternative to traditional data acquisition systems, specifically a 2-channel 50 MS/s USB 3.0 voltage data acquisition card based on an FPGA design. This card, designed with an XC7A100T-2FGG484I FPGA, offers a high-speed data acquisition solution for various industrial and scientific applications. The card features a total of 2 channels, with each channel capable of sampling at a maximum rate of 50 MS/s. This makes it an attractive option for applications requiring high-speed data acquisition, such as industrial automation, medical equipment, and scientific research. The card's FPGA design allows for flexibility and customization, enabling users to tailor the card's functionality to their specific needs. The XC7A100T-2FGG484I FPGA is a member of Xilinx's Artix-7 family, known for its high-performance capabilities and low power consumption --- ## [Domestic NI Alternative] A7 FPGA-based 8-Channel Voltage 20 MS/s PCIe Data Acquisition Card - URL: https://intl.sienovo.cn/blog/144693285 - Date: 2024-12-24 - Tags: #FPGADev, #EdgeComputing, #ARMDev, #AI ## Overview of the A7 FPGA-based 8-Channel Voltage 20 MS/s PCIe Data Acquisition Card In this article, we will explore the features and applications of a high-speed PCIe data acquisition card that utilizes the XC7A100T-2FGG484I FPGA. This card is designed for industrial computing environments, offering a maximum sampling rate of 20 MS/s and the ability to integrate seamlessly with industrial PCs or desktop computers. ## Key Features ### FPGA Technology The A7 data acquisition card is built around the XC7A100T-2FGG484I FPGA from Xilinx. This FPGA is part of the Artix-7 family, known for its low power consumption and high performance. The FPGA allows for flexible data processing and can be programmed to meet specific application needs, making it an ideal choice for industrial applications. ### High-Speed Data Acquisition This PCIe acquisition card supports a maximum sampling rate of 20 MS/s. This rate is suitable for various applications that require real-time data acquisition, su --- ## 8-Channel Vibration/Voltage 5 Msps High-Speed Data Acquisition Board - URL: https://intl.sienovo.cn/blog/144677967 - Date: 2024-12-23 - Tags: #FPGADev, #AI, #EdgeComputing, #ARMDev ## Overview High-speed vibration and voltage monitoring is a cornerstone of predictive maintenance, structural health monitoring, and industrial condition monitoring. This post introduces an 8-channel dynamic signal acquisition board built around the Xilinx Artix-7 FPGA, capable of sampling at up to 5 Msps per channel — making it well-suited for applications where conventional 100 ksps DAQ cards simply cannot capture the full frequency content of the signals under test. ![8-Channel Vibration/Voltage 5 Msps High-Speed Data Acquisition Board — front](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144677967/01_b70aec4b57604f7786661b58592e2eee.png) ![8-Channel Vibration/Voltage 5 Msps High-Speed Data Acquisition Board — rear](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144677967/02_3318ff6470cd4001bf9d2469d59ae9e6.png) ## Core Hardware: XC7A35T-2FGGI FPGA The board's signal processing backbone is the **Xilinx XC7A35T-2FGGI**, a mid-range Artix-7 series FPGA in a --- ## Domestic Alternative to NI: DSP+FPGA-based 8-channel Vibration/Voltage + 2-channel Tachometer PTP1588 Network Synchronized Edge Computing Acquisition Board - URL: https://intl.sienovo.cn/blog/144677895 - Date: 2024-12-23 - Tags: #EdgeComputing, #AI ## A Domestic Alternative to NI: DSP+FPGA-Based Synchronized Edge Computing Acquisition Board Industrial measurement in China has long relied on National Instruments (NI) hardware for high-channel-count, synchronized data acquisition. This post introduces a domestically developed alternative: an 8-channel vibration/voltage + 2-channel tachometer acquisition board built on a Xilinx FPGA + TI DSP architecture, with PTP IEEE 1588 network-level time synchronization and onboard edge computing capability. If your application demands precision, low noise, and real-time signal processing at the edge — but NI's price tag is a barrier — this class of board is worth understanding. ## Hardware Architecture: XC7A100T-2FGG484 + TMS320C6655 The board pairs two purpose-built silicon devices: **Xilinx XC7A100T-2FGG484 (Artix-7 FPGA)** The Artix-7 100T is a mid-range FPGA in the 7-series family, offering approximately 101K logic cells, 4.9Mb of block RAM, and 240 DSP48E1 slices in a 484-ball fine-pi --- ## 【Domestic Virtual Instruments】DSP+FPGA-based 8-channel Vibration/Voltage Edge Computing Acquisition Board - URL: https://intl.sienovo.cn/blog/144677602 - Date: 2024-12-23 - Tags: #AI, #ARMDev, #EdgeComputing ## Overview This post introduces Sienovo's 8-channel Vibration/Voltage Edge Computing Acquisition Board — a compact, cost-aware data acquisition card built around a hybrid FPGA + DSP architecture. If you are designing an industrial monitoring node that needs high-precision analog acquisition, real-time signal conditioning, and on-board edge computation without the overhead of a full PC-class platform, this board represents a tightly integrated solution worth examining. ## Core Architecture: EP4CE40F23I7 + TMS320C6748 The board pairs two well-proven silicon devices: **Intel (Altera) Cyclone IV EP4CE40F23I7** — a mid-density FPGA with approximately 39,600 logic elements, available in an industrial-temperature variant (the "I7" speed grade is rated to −40 °C to +100 °C). On this board the FPGA handles the tasks it is best suited for: high-speed, deterministic sample capture, channel multiplexing, analog front-end control (gain switching, filter enable/disable lines, modulator clocking --- ## 【Domestic Virtual Instruments】DSP6748+FPGA-based 4-channel Vibration/Voltage Portable Edge Computing Acquisition Board - URL: https://intl.sienovo.cn/blog/144677526 - Date: 2024-12-23 - Tags: #EdgeComputing, #AI 4-channel Vibration/Voltage Portable Edge Computing Acquisition Board ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144677526/01_ae234098f7924c0497eeb99003fc1df2.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144677526/02_973d5f38a15e40fdbaa2211b8e53ea7b.png) It adopts an EP4CE30F23I7 + TMS320C6748 architecture, primarily adding a DSP for edge computing of data. It is mainly applied in scenarios where the channel count requirements are not high, but high sampling resolution and accuracy, noise sensitivity, cost sensitivity, and certain edge computing capabilities are required. NI boards, fully known as National Instruments boards, are a series of hardware devices launched by National Instruments (NI) for data acquisition, control, and signal processing. These boards are widely used in various test, measurement, and control systems, providing engineers and scientists with powerful data acquisition and processing capabilities. Main features of NI b --- ## Domestic NI Alternative: ZYNQ7020-based ARM+FPGA 30-Channel (24-bit) High-Precision Data Acquisition Board, Supporting 256k Adjustable Sampling Rate - URL: https://intl.sienovo.cn/blog/144677437 - Date: 2024-12-23 - Tags: #AI, #ARMDev High-density, high-precision data acquisition has long been dominated by commercial platforms such as National Instruments' CompactDAQ and CompactRIO families. This post introduces a domestically designed alternative built around Xilinx's ZYNQ7020CLG400 SoC — a 30-channel, 24-bit acquisition board that targets the same demanding industrial measurement applications at a significantly reduced BOM cost and with full source-level control over both the ARM processing pipeline and the FPGA fabric. ## Platform Choice: Why ZYNQ7020? The Xilinx Zynq-7000 series (XC7Z020 in the CLG400 package) combines a dual-core ARM Cortex-A9 hard processor system (PS) with a Artix-7 class programmable logic (PL) fabric on a single die. This tight PS-PL integration is critical for data acquisition work: the FPGA fabric handles deterministic, cycle-accurate sampling and digital filtering close to the ADC, while the ARM cores run the higher-level protocol stack, configuration management, and any signal process --- ## Chinese-Made NI Alternative: Artix-7 FPGA+AI Based 16-Channel, 16-bit Vibration PCIe Data Acquisition Card - URL: https://intl.sienovo.cn/blog/144677316 - Date: 2024-12-23 - Tags: #FPGADev, #AI ## Overview of the 16-Channel Vibration PCIe Acquisition Card In this article, we will explore the features and capabilities of a 16-channel, 16-bit vibration PCIe acquisition card that utilizes the XC7A100T-2FGG484I FPGA. This card is specifically designed for industrial applications, providing a cost-effective solution for data acquisition in environments where high sampling resolution is not a primary concern. ## Key Features ### FPGA Integration The heart of this acquisition card is the XC7A100T-2FGG484I FPGA from Xilinx's Artix-7 series. This FPGA is known for its balance of performance and power efficiency, making it suitable for industrial applications. The card leverages the FPGA's capabilities to handle multiple data channels simultaneously, ensuring efficient data processing and transfer. ### PCIe Interface The card is designed as an auxiliary component that can be easily inserted into the PCIe slots of an industrial or desktop PC. This design allows for straightforwar --- ## [Domestic NI Alternative] 16-Channel Vibration/Voltage + 8-Channel Tachometer + 2-Channel Analog Output Multifunctional Terminal Acquisition Card, Supporting High-Precision, Multi-Channel Dynamic Signal Acquisition - URL: https://intl.sienovo.cn/blog/144677238 - Date: 2024-12-23 - Tags: #FPGADev, #AI, #BigData ## A Compact, High-Channel-Count Dynamic Signal Acquisition Card Built on Dual FPGAs Industrial test and measurement engineers who have worked with National Instruments (NI) hardware know the trade-offs well: excellent software ecosystem, proven accuracy, but steep licensing costs and form factors that can feel oversized for embedded or field-deployed systems. This card is a domestic Chinese alternative aimed squarely at that gap — a 16-channel vibration/voltage + 8-channel tachometer + 2-channel analog output acquisition board that packs high-precision, multi-channel dynamic signal acquisition into a compact terminal form factor. ## Dual-FPGA Architecture At the heart of the design sit two FPGAs working in tandem: - **Intel (Altera) EP4CE10F17I7** — a Cyclone IV E device in a 256-pin FineLine BGA package, rated for the industrial temperature range (−40 °C to +100 °C, I-speed grade). The Cyclone IV E family is a well-proven choice for cost-sensitive I/O-heavy applications, offering --- ## FPGA-based 32-Channel (24-bit) High-Precision Data Acquisition Core Board: A Domestic NI Alternative - URL: https://intl.sienovo.cn/blog/144677176 - Date: 2024-12-23 - Tags: #FPGADev, #AI, #BigData High-precision data acquisition has long been dominated by commercial platforms like National Instruments (NI), but the cost and export-control realities of those systems have pushed Chinese industrial developers toward domestically designed alternatives. This post introduces a 32-channel, 24-bit dynamic signal acquisition core board built around an Intel Altera Cyclone IV E FPGA — a compact, two-card design targeting the same application space as NI's CompactDAQ and PXI acquisition modules, but integrated directly into a proprietary industrial chassis. ## Hardware Overview The acquisition core is split across two physically separate PCBs that work in tandem: - **Acquisition board** — handles the analog front end: 32 channels of 24-bit sampling, anti-aliasing filtering, and ADC interfacing. - **Communication board** — handles data aggregation, buffering, and transmission to the host or downstream processing chain. Both boards are controlled by an **EP4CE115F29I7** FPGA. This is an --- ## Domestic NI Alternative: 32-Channel Vibration/Voltage (Configurable Hybrid) High-Precision Data Acquisition Board for Complex, Large-Scale Measurement Scenarios - URL: https://intl.sienovo.cn/blog/144677020 - Date: 2024-12-23 - Tags: #FPGADev Industrial test and measurement has long been dominated by platforms such as National Instruments (NI) CompactDAQ and CompactRIO. For Chinese manufacturers and system integrators working on rotating machinery diagnostics, structural health monitoring, or multi-axis vibration analysis, import costs, lead times, and export-control exposure have driven demand for domestically engineered alternatives. This post covers one such alternative: a 32-channel, FPGA-based high-precision dynamic signal acquisition system built around a configurable board architecture that targets exactly the large-scale, cost-tolerant measurement scenarios where NI hardware has traditionally dominated. ## Hardware Architecture Overview ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144677020/01_e0e72989b67a42c79e911473d5ed9220.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144677020/02_65ff1ca5112f495ea687bf339adb3f0b.png) The system is built around an **Altera EP4CE115F29I7** F --- ## [Domestic NI Alternative] ZYNQ7020-based 8-channel Vibration/Voltage, Low-Frequency, Low-Noise, High-Gain (24-bit) Data Acquisition Terminal Board - URL: https://intl.sienovo.cn/blog/144676889 - Date: 2024-12-23 - Tags: #AI, #FPGADev 8-channel Vibration/Voltage, Low-Frequency, Low-Noise, High-Gain (24-bit) Data Acquisition Terminal Board ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676889/01_08a2d27f8e524aea851cfe9c4b034f6e.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676889/02_6f72dbb767549408e865902bd7cbda3.png) Featuring a hardware architecture based on the domestic AG16KF256 FPGA and STM32F429, it is primarily designed for low-frequency, low-noise application scenarios. The maximum sampling rate is 1 Ksps, and the minimum sampling rate is 50 sps. Under conditions of maximum sampling rate and maximum gain, the noise is merely 35 nVp-p, making it highly suitable for acquiring low-frequency small signals. **(II) 16-channel Vibration/Voltage/Current + 16-channel Temperature (24-bit) High-Precision Data Acquisition Terminal Board** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676889/03_4b82563c93e041dc801087199245e583.png) ![](https://pub-048dcb96 --- ## Chinese-Made NI Alternative: High-Precision Data Acquisition Terminal Board with 16 Vibration + 2 RPM Channels (24-bit ADC), 8-Channel I/O, 256 kSps Sampling Rate, Based on Entirely Domestic FPGA - URL: https://intl.sienovo.cn/blog/144676745 - Date: 2024-12-23 - Tags: #BigData, #FPGADev, #AI Industrial vibration monitoring and condition-based maintenance systems demand data acquisition hardware that can faithfully capture high-frequency mechanical signatures across many channels simultaneously. This post introduces a domestically designed high-precision terminal acquisition board built around the AG16KF256 FPGA — a Chinese-made device — that targets exactly this use case: pure, high-throughput signal capture without the overhead of an embedded application processor. ## Hardware Architecture Overview The board's core is the **AG16KF256**, a domestic (国产) FPGA. Rather than pairing the FPGA with an ARM core as many mixed-architecture boards do, this design uses a **pure FPGA architecture**, deliberately trading general-purpose edge compute capability for raw sampling bandwidth. An external **16 MB SDRAM** acts as a deep transmit buffer for the **Gigabit Ethernet** output path, decoupling the high-speed ADC front-end from the variable-latency network interface and preventing --- ## Domestic NI Alternative: Fully Chinese-Made 16-Channel Vibration + 2-Channel Rotational Speed (24-bit) High-Precision Terminal Acquisition Board Based on Domestic FPGA + GigaDevice GD32F450 - URL: https://intl.sienovo.cn/blog/144676652 - Date: 2024-12-23 - Tags: #FPGADev Industrial vibration monitoring has long been dominated by National Instruments (NI) hardware — reliable, but expensive and dependent on foreign supply chains. This post introduces a fully domestic alternative: a 16-channel vibration + 2-channel rotational speed terminal acquisition board built around a Chinese AG16KF256 FPGA and a GigaDevice GD32F450 ARM microcontroller, delivering 24-bit precision at a significantly lower cost and with a fully maintainable domestic software stack. ![Board front view](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676652/01_2cbbc7e0422547368a89ff3fe3707ac4.png) ![Board rear view](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676652/02_2b12afcd50934282b0ce9769d41ba22f.png) ## Hardware Architecture Overview The board is a two-chip design that divides signal processing into a clear front-end / back-end split: - **Front-end (FPGA — AG16KF256):** Real-time signal acquisition, anti-aliasing filtering, and decimation across al --- ## 【NI Domestic Alternative】Fully Domestic High-Precision 16-Channel Vibration + 2-Channel Speed (24-bit) Terminal Acquisition Board Based on Domestic FPGA + Allwinner T3 - URL: https://intl.sienovo.cn/blog/144676579 - Date: 2024-12-23 - Tags: #FPGADev, #AI ## Fully Domestic High-Precision 16-Channel Vibration + 2-Channel Speed (24-bit) Terminal Acquisition Board Based on Domestic FPGA + Allwinner T3 Industrial vibration monitoring and rotating machinery health assessment have long relied on high-channel-count data acquisition hardware from vendors such as National Instruments. This post introduces a fully domestically produced alternative: a 16-channel vibration plus 2-channel tachometer acquisition board built around the AG16KF256 domestic FPGA and the Allwinner T3 domestic ARM processor. The design targets predictive maintenance and condition monitoring applications where high channel density, precise phase alignment, and 24-bit amplitude resolution are non-negotiable requirements. ![Board overview](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676579/01_f326c16eeaf3458b9b4ca06037147220.png) ![Core and baseboard assembly](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676579/02_5a2412101e944e2296275204b5f9 --- ## 【Domestic NI Alternative】High-Precision 8-Channel Vibration + 4-Channel Temperature (24-bit) Terminal Data Acquisition Board Solution Based on STM32+FPGA, Supporting Fully Domestic Production - URL: https://intl.sienovo.cn/blog/144676513 - Date: 2024-12-23 - Tags: #FPGADev, #AI, #DevOps ## Overview Industrial vibration monitoring and thermal sensing demand precision hardware that can keep pace with high-frequency mechanical phenomena while maintaining signal fidelity across all channels. This article introduces a domestically-produced 12-channel terminal data acquisition board — 8 vibration channels plus 4 temperature channels — built around an Intel (Altera) Cyclone IV FPGA and an STM32H743 microcontroller. The design is a direct upgrade to an earlier 16-bit variant and positions itself as a cost-effective domestic alternative to National Instruments (NI) data acquisition hardware for industrial field deployments. ## Hardware Architecture: EP4CE10F17I7 + STM32H743 The board pairs two complementary processing engines to handle the distinct demands of real-time signal conditioning and host-side data management. The **EP4CE10F17I7** is an Intel Cyclone IV E FPGA with approximately 10,000 logic elements in an industrial-temperature-grade package (the `-I7` suffix ind --- ## [Domestic NI Alternative] STM32+FPGA-based 8-channel Vibration + 4-channel Temperature (16-bit) Data Acquisition Board Solution, Supporting Fully Domestic Production - URL: https://intl.sienovo.cn/blog/144676345 - Date: 2024-12-23 - Tags: #AI, #BigData **I. 8-channel Vibration + 4-channel Temperature (16-bit) Data Acquisition Board Solution** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676345/01_0799347bfb54481f843208cabe0acb0e.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676345/02_69c649dca033433281f3aa33900f30eb.png) Using the STM32H743 as the main control chip, this 12-channel data acquisition device is designed for industrial environments. The analog signal conditioning circuit of the acquisition unit features a modular design, with configurable and expandable front-end channel modules. The first 8 channels are compatible with IEPE, 4-20mA, and voltage acquisition, while the latter 4 channels support 4-20mA, voltage, and PT100/PT1000 acquisition. Supports fully domestic versions and OEM customization. **II. 20 (30)-channel (16-bit) Terminal Acquisition Board** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144676345/03_098ef9db89804d659e6d54e5a7f2f6b5.png) ![](http --- ## X86/ARM-based SLAM+AI Robot Controller [Semiconductor Solutions] Smart Logistics Upgrade for Semiconductor Packaging and Testing Process Segments - URL: https://intl.sienovo.cn/blog/144539365 - Date: 2024-12-17 - Tags: #ARMDev, #Robotics, #AI ##### A globally renowned semiconductor enterprise is undergoing a smart logistics upgrade for its packaging and testing process segments. This project covers two cleanroom scenarios, involving over 70 pieces of various semiconductor equipment, with a total route length exceeding 5 kilometers. More than 40 AMRs are deployed on-site, operating 24 hours a day without interruption, which severely tests the durability of both the AMR scheduling system and the AMR vehicles themselves. ![图片上传](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144539365/01_a450e51b0f7cf3900cf8dab265e8dbae.webp) #### **Solution Highlights:** 40+ cleanroom-certified composite robots specifically for packaging and testing Line-side buffer stations Warehouse and Logistics Management System (MWMS) Unified Resource Dispatching System (RDS) **Challenges and Solutions:** **Challenge 1: Difficult and lengthy deployment of 2D vision solutions** Solutions: 1. No markers required for production or insta --- ## X86/ARM+SLAM-based Robot Controller: [Machinery Industry] Empowers Customers to Achieve Smart Manufacturing - URL: https://intl.sienovo.cn/blog/144539133 - Date: 2024-12-17 - Tags: #AI, #Robotics, #ARMDev **Project Background** With the comprehensive advancement of a new round of technological revolution, production automation and the realization of intelligent internal logistics have become one of the most pressing topics for many manufacturers within the global manufacturing system, and also a critical issue that factory workshops urgently need to address. Especially for large, well-established enterprise workshops, where production automation is gradually maturing, solving internal logistics automation and intelligence has become the next critical step in building smart factories, which is of great significance for achieving high-efficiency and lean production. **Client Challenge** The client is a foreign-funded enterprise and a globally renowned manufacturer of pneumatic and electric components, modules, and systems. In the pneumatic component production workshop of one of its branches in North China, due to the frequent need to move semi-finished products between processing loc --- ## X86/ARM + SLAM-based Robot Controller [3C Electronics Manufacturing] One-stop Smart Logistics Solution - URL: https://intl.sienovo.cn/blog/144538898 - Date: 2024-12-17 - Tags: #Robotics, #Manufacturing **Project Background** The client for this project is a Fortune Global 500 company, known for its innovative technological concepts and advanced technical expertise. It provides global customers with products such as programmable human-machine interfaces (HMIs), industrial panel PCs, graphic logic controllers, and industrial information terminals. It enjoys an excellent reputation in the international industrial control (IPC) sector and is one of the leading brands in the industry. The client's production workshops are vast, and manufacturing components are scattered. Collaboration between production lines relies on manual labor combined with magnetic stripe guided vehicles. The two-shift work system, coupled with difficult-to-handle materials, presents the company with challenges of high labor costs and low handling efficiency. **Solution** In response to the client's various challenges, a one-stop smart logistics solution was provided. This solution leverages a vast product matr --- ## Industrial Robot Solution Based on RK3588 and 3D Vision Perception - URL: https://intl.sienovo.cn/blog/144534906 - Date: 2024-12-17 - Tags: #Robotics ## RK3588-Based Industrial Robot Solution For industrial robot applications, leveraging 3D vision perception technology, dToF LiDAR is used to acquire and output depth information of targets and environments. This assists industrial robots in achieving functions such as motion obstacle avoidance, grasping planning, and robot collaboration. It can be applied in industrial and logistics scenarios such as material handling, pick-and-place, assembly, gluing, and inspection. Currently, it serves several leading industrial robot manufacturers, including Standard Robots, Mech-Mind, and Siasun.![](https://pub-048dcb96257f4476697b113fcb5939cb9.r2.dev/blog/144534906/01_52a8e758094644b6a162e025d7c4518b.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144534906/02_d35994f10e444d5f8f422c942faf5891.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144534906/03_2724cb424f58713f7a1b0465af4aeee0.png) **What features are required for industrial robot control boards? --- ## Delivery Robot Solution Based on RK3588 Robot Controller and 3D Vision Sensor - URL: https://intl.sienovo.cn/blog/144514809 - Date: 2024-12-16 - Tags: #Robotics, #AI ## Delivery Robots By integrating 3D vision sensors and Xinmai Robot Controllers, delivery robots can flexibly avoid obstacles and navigate complex restaurant environments, significantly improving meal delivery efficiency, enhancing the user dining experience, and substantially reducing operating costs for businesses. Difficulty in delivering during peak hours has long been an industry pain point for delivery robots. Restaurants experience high foot traffic during peak hours, and the environment is highly complex and unpredictable. Equipped with RGBD depth sensors and efficiently integrating RGB cameras and LiDAR, they possess powerful visual perception capabilities, allowing them to navigate freely even in highly dynamic and complex environments. ![20220325-普渡巧乐送-4K-L.mp4_20221111_110957.445.png](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144514809/01_07a4e6e5a8e625dafcefb8fc6e41ad90.png) ![20220325-普渡巧乐送-4K-L.mp4_20221111_110903.988.png](https://pub-048dcb96257f47 --- ## RK3588 + 3D Vision-based Robot Controller for Cleaning Vehicles, AGVs, and Similar Scenarios - URL: https://intl.sienovo.cn/blog/144514424 - Date: 2024-12-16 - Tags: #AI ## Service Robot Solutions For service robot applications, leveraging 3D vision perception technology and proprietary ASIC chips, we achieve high-precision 3D depth information acquisition, enabling service robots to perform perception, obstacle avoidance, and navigation functions. These solutions are widely applicable in commercial cleaning, food delivery, building delivery, warehousing and logistics, education and entertainment, and other fields. Xinmai has provided technology and product services to over 100 leading service robot brands, including Gaussian Robotics, Yunji Technology, and Pudu Technology.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144514424/01_27a769b690664cdb8c8ce25b4ec645c2.png) ## Empowered by 3D Vision, One Cleaning Vehicle Replaces Three Workers Artificial intelligence is entering a period of explosive growth, deeply integrating with industries and applications. A number of AI industry chain enterprises, by independently developing key core --- ## Programmable Smart DAQ with 4-Channel Sound and Vibration Input, 24-bit, 128 kS/s, 4-Channel DI/O - URL: https://intl.sienovo.cn/blog/144293311 - Date: 2024-12-06 - Tags: #AI, #BigData, #DevOps Programmable Smart DAQ with 4-Channel Sound and Vibration Input, 24-bit, 128 kS/s, 4-Channel DI/O Key Features * Standalone Ethernet DAQ with Edge Computing Support * RESTful API for periodic machine status polling * Supports C/C#/C++/Python/LabView APIs for continuous data streaming * Built-in Web Console for easy configuration and portable DAQ use * Supports iApp deployment for edge-side data analysis and efficiency improvement The ultra-compact edge DAQ features an ARM Cortex-A9 processor with built-in, four-channel, 24-bit, high-resolution analog inputs. It can be used as a standalone device without a host PC, making it ideal for 24-hour vibration monitoring of rotating machinery. xmdaq provides high-precision static and dynamic measurement capabilities. The 24-bit Sigma-Delta ADC supports anti-aliasing filtering, modulation suppression, and out-of-band noise rejection, providing usable signal bandwidth at the Nyquist rate, making it an ideal choice for high dynamic r --- ## 4K DisplayPort Input Functionality for FPGA-based Video Wall Controller, LVDS to SerDes Conversion, Supporting Localized Customization - URL: https://intl.sienovo.cn/blog/144204185 - Date: 2024-12-03 - Tags: #FPGADev 4K (3840 x 2160 @60Hz) is increasingly becoming a video trend. Integrating 4K into a video wall controller is a challenging problem. First, let's look at the schematic interface: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144204185/01_20161020114221749.png) This is the LVDS interface of the ANX1122. Below is the system block diagram:     ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144204185/02_20160301100250179.png) The DisplayPort signal enters the ANX1122. The ANX1122 converts the DisplayPort input signal into an LVDS signal. The FPGA then converts the LVDS signal into video timing signals. Finally, the FPGA transmits these timing signals via SerDes. The output card receives the SerDes signal, converts it back into timing signals, and then performs video wall processing. Large-screen video wall applications are becoming increasingly widespread. They are found in security monitoring, home theaters, store displays, conference training, and ev --- ## FPGA-based Design for a Low-Latency 4K 60Hz Video Splicer - URL: https://intl.sienovo.cn/blog/144203917 - Date: 2024-12-03 - Tags: #FPGADev Video wall applications are becoming increasingly widespread, found in security monitoring, home theaters, store displays, conference training, and even promotional displays at restaurant entrances, among other venues. The increasingly common application of large video walls brings broad market prospects. [LCD displays](https://so.csdn.net/so/search?q=%E6%B6%B2%E6%99%B6%E6%98%BE%E7%A4%BA%E5%B1%8F&spm=1001.2101.3001.7020 "LCD displays") are characterized by clear and delicate image quality, but the size of individual LCD displays is limited. Currently, mainstream single-screen LCD TVs are only around 100 inches. If you want to form a larger display using LCD panels, you need to employ screen splicing technology. One drawback of large video walls is that the gaps between screen bezels cannot be completely eliminated. However, current excellent LCD screens can achieve ultra-narrow bezels down to 0.8mm, providing a very good visual effect. With the maturity of technology and the reductio --- ## Drone Gimbal Solution Implemented with RK3588, AI, and 4K Imaging - URL: https://intl.sienovo.cn/blog/144194184 - Date: 2024-12-02 - Tags: #UAV, #AI Drones equipped with payloads are a common configuration, allowing gimbals to carry different equipment to meet various mission requirements. Payloads are typically mounted on the underside or side of the drone and can be adjusted as needed. With the rapid advancement of drone technology, the emergence of 4K AI 180x hybrid zoom gimbal technology has elevated drone reconnaissance and surveillance capabilities to a new level. This technology integrates high-resolution imaging, artificial intelligence analysis, and high-magnification hybrid zoom, providing drones with unprecedented reconnaissance and identification capabilities. I. Technology Overview 1. 4K Ultra HD Imaging: Compared to traditional 2K resolution, 4K resolution offers higher image quality, with clearer details and more vibrant colors. This enables drones to capture finer target details, providing higher quality data for subsequent image analysis and processing. 2. AI Intelligent Analysis: By integrating artificial int --- ## UAV Gimbal Wireless Video Transmission and Vision Solution Based on RK3588 with AI Capabilities - URL: https://intl.sienovo.cn/blog/144194037 - Date: 2024-12-02 - Tags: #AI, #UAV We have implemented input from a Sony camera module and a [Gaode](https://so.csdn.net/so/search?q=%E9%AB%98%E5%BE%B7&spm=1001.2101.3001.7020 "高德") infrared module, along with compression, storage, and RTSP forwarding. Tracking and recognition functionalities have been added, including ByteTrack for multi-target ID assignment. We have also addressed and improved dual-channel transmission and control issues from previous models. If you are interested in using this solution, please contact me. I'm open to discussing it at a reasonable price, offering two options: open-source availability or direct shipment using my proprietary protocol. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144194037/01_a99ccd5a0b9349559683d521c33cdfda.png) There are still some issues, such as OSD overlay speed. For example, we lack sufficient training samples to achieve recognition of specific target types. Also, the current tracking [algorithm](https://edu.csdn.net/course/detail/40020?utm_sourc --- ## AI Edge Server based on BM1684 - Model Conversion, Large Model All-in-One Machine (Part 2) - URL: https://intl.sienovo.cn/blog/144193771 - Date: 2024-12-02 - Tags: #AI, #Server, #DevOps #### #### Object Tracking Note: All model conversions are performed within the Docker environment. First, enter Docker. We will be compiling in the Docker environment, so first, enter Docker. ```hljs :~/tpu-nntc# docker run -v $PWD/:/workspace -it sophgo/tpuc_dev:latest ``` Initialize Environment ```hljs root@2bb02a2e27d5:/workspace/tpu-nntc# source ./scripts/envsetup.sh ``` Install Compiler in Docker ```hljs root@2bb02a2e27d5:/workspace/sophon-demo/sample/YOLOv5/cpp/yolov5_bmcv/build# sudo apt-get install gcc-aarch64-linux-gnu g++-aarch64-linux-gnu libeigen3-dev ``` This C++ example depends on Eigen. You need to run the following command to install it on the machine where you compile the C++ program: ```hljs sudo apt install libeigen3-dev ``` First, download the relevant files, mainly the test video for tracking, test images, object tracking weights, and object detection weights. ```hljs # Install unzip, skip if already installedsudo apt install unzipchmod -R +x s --- ## BM1684-based AI Edge Server - Model Conversion, Large Model Integrated Machine - URL: https://intl.sienovo.cn/blog/144193493 - Date: 2024-12-02 - Tags: #AI, #Server, #DevOps If you encounter any issues during the installation, you can refer to online resources for troubleshooting. ### Download SDK Next, you will need to download the necessary SDK from the Sophon official website. The SDK includes several essential tools for model compilation and deployment: - **tpu-nntc**: This tool is responsible for offline compilation and optimization of neural network models trained using various deep learning frameworks, generating the BModel required for runtime execution. It supports frameworks like Caffe, Darknet, MXNet, ONNX, PyTorch, PaddlePaddle, and TensorFlow. - **libsophon**: This library provides BMCV, BMRuntime, and BMLib, which are used to drive hardware like VPP and TPU for image processing, tensor operations, and model inference. - **sophon-mw**: This encapsulates libraries like BM-OpenCV and BM-FFmpeg, facilitating video stream parsing and image encoding/decoding acceleration for deep learning applications. - **sophon-sail**: This provides high-level --- ## [Onboard AI Box] AI + Machine Vision Applications in Engineering Vehicle Scenarios, Including DSM Driver Behavior Analysis System and BDS System Design - URL: https://intl.sienovo.cn/blog/144155752 - Date: 2024-11-30 - Tags: #AI, #AudioVideo, #BigData 一、Industry Background As the modern economy develops and urbanization accelerates, the rapid increase in urban population has led to an astonishing growth in urban waste production. With the improvement of living standards, people are paying increasing attention to health and the environment. Urban environmental sanitation is a city's living business card. Muck trucks are the main force for urban waste transportation, but during operation, they often involve frequent driving and illegal operations, impacting traffic safety. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144155752/01_d35d8c198c8349018b564ae90e9bfcfa.jpeg)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144155752/02_ab2154e92e6542fda0cfa222cc1710e5.jpeg)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144155752/03_0df62446d92842d996eb9fccd23a386e.jpeg) 二、Solution Structure The smart management solution for muck truck transportation implements intelligent supervision through AI r --- ## 【Intelligent Transportation】Application of Onboard Smart AI Box in Intelligent Management Systems for Muck Trucks, Construction Vehicles, and Sanitation Vehicles (Part 3): Blind Spot Management, Driver Monitoring, Illicit Vehicle Management, etc. - URL: https://intl.sienovo.cn/blog/144155326 - Date: 2024-11-30 - Tags: #AI, #MachineLearning 1. 1. Blind Spot Monitoring The system supports the installation of four cameras, with driver monitoring inside the cab and roof monitoring being mandatory installations. Additionally, it supports the expansion of at least two video channels. This can prevent fatalities and injuries caused by blind spots. Intelligent pedestrian recognition in blind spots uses image recognition technology to intelligently detect pedestrians, triggering external audible and visual alarms, in-cab alarms to alert the driver, and uploading image data to the platform. 1. 1. 1. Blind Spot Pedestrian Recognition (BSD) Supports the recognition of pedestrians, electric bike riders, and bicycle riders in the forward right-side blind spot, and can distinguish between pedestrians and ordinary obstacles. 1. 1. 1. Operating Hours When the vehicle's ACC status is ON, the blind spot pedestrian monitoring function remains continuously active. 1. 1. 1. Blind Spot Pedestrian Collision Warning If a pedes --- ## Intelligent Transportation: Application of Onboard Smart AI Boxes in Intelligent Management Systems for Muck Trucks, Construction Vehicles, and Sanitation Vehicles (Part 2) - URL: https://intl.sienovo.cn/blog/144155120 - Date: 2024-11-30 - Tags: #AI 1. 1. 1. Vehicle Smart Lift Restriction When a vehicle is heavily loaded, its dump bed can only be lifted at designated locations (typically construction sites and disposal sites) to prevent unauthorized dumping of muck. If a heavily loaded vehicle attempts to lift its dump bed at an unauthorized location, the lifting mechanism will be restricted and unable to operate. Even if the lifting control is manually tampered with, the onboard terminal will report the unauthorized lifting alarm information to the platform. 1. 1. 1. Vehicle Smart Locking and Unlocking In cases of serious violations such as unauthorized dumping or entering restricted areas, the vehicle will be locked and unable to start. It will require management personnel to unlock it and impose penalties. In special circumstances, the platform can temporarily lock or unlock designated vehicles. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144155120/01_e51bc252f89c42de9c740f5cdea6d318.jpeg)![](https --- ## [Intelligent Transportation] Application of Onboard Smart AI Boxes in Smart Management Systems for Construction Waste Vehicles (Part 1) - URL: https://intl.sienovo.cn/blog/144154822 - Date: 2024-11-30 - Tags: #AI, #BigData, #Networking 1. ******Overview of the Construction Waste Vehicle Management System****** 1. Project Background With rapid economic development, the pace of urbanization is accelerating, leading to an increasing number of urban environmental management issues. Management of construction waste, as a crucial component of environmental sanitation improvement, is receiving growing attention. Due to the inadequacy of existing management systems, policies, laws, and regulations for construction waste disposal, the management of construction waste has become a prominent issue in urban environmental sanitation management, characterized by relatively outstanding problems, sharp conflicts, significant management difficulties, and high public concern. The volume of construction waste excavated annually in urban areas is enormous. Currently, some construction waste transfer and transport vehicles have completed the necessary procedures as required. However, a significant portion of construction waste --- ## Design of an NXP LS1043 OpenWRT-based Intelligent Transportation Edge Gateway - URL: https://intl.sienovo.cn/blog/144068358 - Date: 2024-11-26 - Tags: #SmartRouter 0 Introduction Urban public transportation is a vital infrastructure closely related to people's daily lives and production, and a public welfare undertaking concerning national economy and people's livelihood. The "13th Five-Year Plan for the Development of Urban Public Transportation" explicitly states: to build intelligent public transportation systems deeply integrated with the mobile internet; to promote the development of "Internet+ Urban Public Transportation"; and to advance the construction of diversified public transportation service networks. Intelligent public transportation systems are incorporating an increasing number of in-vehicle systems, such as active safety early warning systems, video surveillance systems, 360-degree surround view systems, safety monitoring systems, intelligent dispatching systems, intelligent terminals, passenger information systems, passenger payment systems, and intelligent safety alarm systems. Some in-vehicle systems lack wireless communica --- ## Design and Implementation of Virtualized Devices in Embedded Systems Based on NXP LS1046 + FPGA - URL: https://intl.sienovo.cn/blog/144067741 - Date: 2024-11-26 - Tags: #FPGADev ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/144067741/01_0c8f3437f41e432b85a9b5776fd3d80e.png) 3 Design of the Virtualized Device Simulation Platform The virtualized device designed and implemented in this paper requires building a simulation platform. A robust simulation platform is key to successfully setting up a virtualized device. Building the simulation platform requires specific hardware conditions and, more importantly, a software environment. This section will detail the setup of this virtualization platform. 3.1 Device Simulation Platform Architecture The hardware environment required for the virtualized device designed in this paper primarily consists of an ARM v8 architecture Linux server acting as the host machine, with no fewer than 16 CPU cores, a hard disk capacity of at least 500GB, and physical memory of at least 32GB. Regarding the software environment, the device simulation platform is mainly divided into three aspects: processor platform simul --- ## Design Ideas for Intelligent Power Systems Based on RK3568 Smart Gateway and Convolutional Neural Network Algorithm - URL: https://intl.sienovo.cn/blog/144051078 - Date: 2024-11-26 - Tags: #AI **1  Background** Infrastructure development plays a crucial role in a nation's economic growth, and the power system is a vital component of infrastructure. The stable operation of the power system is essential for the steady development of primary, secondary, and tertiary industries, including agriculture, industry, and commercial services. Among these, agricultural labor shortages are a current reality in agricultural production. Agricultural production is increasingly reliant on various agricultural machinery, and large-scale mechanized production in agriculture cannot function without the support of the power system, for tasks such as agricultural irrigation and drainage, crop threshing, and the production, processing, and packaging of agricultural products. Electricity prices for agricultural production are significantly lower than those for industrial and commercial use. The average retail price for general industrial and commercial electricity is above 0.6 yuan/(kW·h), where --- ## All-Domestic Industrial-Grade Switch: 2-Fiber, 4-Ethernet Port Solution - URL: https://intl.sienovo.cn/blog/144018657 - Date: 2024-11-25 - Tags: #Networking All-Domestic Industrial Switch Solution A network solution featuring domestically produced main chips and components, widely applied in communication networks for critical national industries such as power grids, military, and highways. A "fully domestic industrial switch," by its literal meaning, implies two things: **First, it is fully domestically produced (industrial switch)**, meaning over 95% of the components inside the switch are manufactured in China. Critical hardware chips, such as the switch chip, management chip, and interface chips, must be **researched, developed, and manufactured** domestically by Chinese vendors. **Second, it is a managed (industrial switch)**, meaning it can be managed over the network. Managed industrial switches offer three management methods: serial port management, Web management, and network management software management. They provide various network management options, including terminal control port (Console) and Web-based interfaces. This --- ## [Intelligent Transportation] Smart AI Vision System Monitoring Solution for Buses/Construction Vehicles - URL: https://intl.sienovo.cn/blog/143978483 - Date: 2024-11-22 - Tags: #AI With the rapid development of technology, AI is gradually permeating various fields, and traffic monitoring is no exception. In recent years, AI vision analysis system solutions have been increasingly applied in traffic monitoring, providing intelligent support for urban traffic management. For intelligent traffic monitoring, AI system solutions primarily include the following core components: I. Real-time Monitoring and Analysis The AI vision analysis system adopts advanced image recognition and processing technology to monitor urban traffic conditions in real-time. The system captures information such as traffic flow, speed, and vehicle types in real-time through cameras installed at intersections and road segments, providing data support for traffic management. II. Vehicle Information Recognition The system utilizes deep learning algorithms to extract key vehicle information such as license plates, vehicle types, colors, and speeds, providing detailed data for traffic monitori --- ## RK3588 + Ascend AI | 40 TOPS AI Computing Box Design Solution - URL: https://intl.sienovo.cn/blog/143873165 - Date: 2024-11-19 - Tags: #AI 1. ******Introduction to Integrated Video AI Analytics System****** Based on computer vision technology, AI empowers various industries. Relying on AI visual analytics technology and robust "edge-to-cloud" computing power, it performs real-time analysis of events such as smoke, fire, and intrusion. In conjunction with a cloud-based early warning platform, it achieves a closed-loop process for event detection, early warning, and handling. 1. 1. **Design Architecture** 1. **System Architecture** The video intelligent recognition system is divided into four layers from bottom to top: "Perception Layer, Network Layer, Support Layer, and Application Layer." The system's logical architecture is shown in the figure below: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143873165/01_63edb599f89147a1b1e8b3e009e42a32.png) ****Perception Layer**** Connects to front-end sensing devices, such as video surveillance cameras, NVRs, and other IoT sensing devices. It perf --- ## Implementation of an ARM+FPGA-based Power Communication Management Unit for IEC61850 Protocol Communication - URL: https://intl.sienovo.cn/blog/143802990 - Date: 2024-11-15 - Tags: #FPGADev This chapter addresses the shortcomings of traditional communication management unit solutions in supporting multiple RS485 ports and their performance bottlenecks when processing massive amounts of data. This paper utilizes Intel's new Cyclone V SoC FPGA chip, fully leveraging the high-speed parallel processing capabilities and field-programmable advantages of FPGAs, combined with the flexible computing and control capabilities of ARM processors, to design a hardware-configurable power communication management unit system based on a heterogeneous computing architecture [8]. This chapter will discuss the basic requirements for communication management units in photovoltaic arrays, as introduced in Chapter 2, and analyze the feasibility of SoC FPGAs for photovoltaic power communication system management units, considering the inherent hardware characteristics of SoC FPGAs. 3.1 Basic Concepts of SoC FPGA The Intel Cyclone V SoC FPGA, released by Intel PSG (formerly Altera) in 2013, is --- ## RK3568 + FPGA-based 1U/2U Power Communication Management Unit and Power Gateway Solution - URL: https://intl.sienovo.cn/blog/143790238 - Date: 2024-11-15 - Tags: #IoT, #MCU, #EmbeddedHardware 0　Introduction With the development of technologies such as electronics, computers, networking, communication, and embedded systems, new microprocessor-based measurement and protection IEDs (Intelligent Electronic Devices) have been widely applied in substation automation systems. Due to the lack of a unified standard, the communication methods and protocols adopted by various IED manufacturers are inconsistent and incompatible with each other. To address this, the IEC developed and promulgated IEC61850\[1-3\], an international standard for substation automation systems and communication networks. However, the acceptance and widespread adoption of the standard require a lengthy process, and a large number of IEDs that do not support the IEC61850 standard will continue to be used for some time. Therefore, this paper designs a communication management unit for substation automation systems, based on an ARM platform and utilizing an embedded operating system. As an interface device bet --- ## RK3568J-based Multi-port Power Trusted IoT Gateway Solution - URL: https://intl.sienovo.cn/blog/143786980 - Date: 2024-11-15 - Tags: #IoT, #AI ## Foreword With the popularization and increasing power of the Industrial Internet of Things (IIoT), edge computing gateways have emerged. Edge computing effectively reduces the load on cloud servers, significantly lowers bandwidth usage, and provides convenient conditions for localized regional autonomy. Edge computing gateways perfectly combine the advantages of "edge" and "endpoint," integrating AI, Industrial IoT, and edge computing through 4G/5G communication and the Internet. They achieve features such as cloud-edge collaboration, edge-endpoint linkage, compute offloading, and regional autonomy, making them widely applicable in fields like Industrial IoT, smart transportation, power IoT, environmental protection and fire safety, and smart agriculture. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143786980/01_8179f84c970f319014b90c50692a63cb.png) ## A Design for a Power Trusted IoT Gateway 0. Introduction In the current construction of the power IoT, intel --- ## 【Domestic AI Servers】Advanced Features and Applications of Fully Domestic PCIe 4.0/5.0 Switches, Illustrated with 12Gb SAS Expander Storage Controllers - URL: https://intl.sienovo.cn/blog/143708304 - Date: 2024-11-12 - Tags: #Server, #DevOps Looking at the Chinese source, "深圳信迈" appears exactly once, as the final standalone line: "深圳信迈支持全国产PCIE4.0/5.0 switch定制开发". The current English translation is truncated and never reaches that section. I'll return the English as-is and append the single brand mention. Many people have probably heard of PCI-E Switch chips, but most likely know very little about their basic functions. As a cutting-edge productivity tool, PCI-E Switches have been widely adopted in traditional storage systems, as well as in a limited number of server brands and models. As a system architect at PMC-Sierra, a company with the world's leading PCI-E Switch products, I'd like to popularize some basic knowledge about PCI-E Switches here. **Background Introduction** Everyone is familiar with PCI-E; motherboards have PCI-E slots, and the "golden fingers" inside are a bunch of signal lines directly connected to the CPU's internal PCI-E controller. However, current Intel platform CPUs support a maximum of 40 lanes --- ## AI Servers: Application Cases of Domestically Produced PCIe 5.0 Retimer Cards - URL: https://intl.sienovo.cn/blog/143707732 - Date: 2024-11-12 - Tags: #AI, #Networking With the rapid advancement of computer technology, high-speed interconnect technologies are continuously evolving. PCI Express (PCIe), as one of the most prevalent I/O bus standards today, sees a significant increase in data transfer rates with each iteration. PCIe 5.0 doubles the per-lane transfer rate to 32 GT/s, up from 16 GT/s in the previous generation. However, as data rates increase, signal integrity issues become more prominent, especially in long-distance transmission or complex environments, where signal attenuation and distortion can severely impact system reliability and performance. In such scenarios, Retimers become one of the key components for ensuring signal quality. **1** **Role of Retimers** A Retimer is a signal regeneration device whose primary function is to detect, process, and regenerate signals during transmission, thereby ensuring that the signal maintains good quality even after long-distance transmission. In PCIe 5.0, the application of Retimers is cruc --- ## Domestically Produced PCIe 4.0 Interface Signal Integrity Simulation Analysis, Taking 10 Gigabit Network Cards and 11-slot PCIe GPU Baseboards (PCIe 4.0/5.0) as Examples - URL: https://intl.sienovo.cn/blog/143705853 - Date: 2024-11-12 - Tags: #Networking **PCIe 4.0 Interface Signal Integrity Simulation Analysis in 10 Gigabit Network Card Design** Given the current low accuracy and reliability of existing PCIe interface signal integrity simulations, a new PCIe 4.0 signal channel link model and simulation analysis method have been established. A ×4 PCIe 4.0 signal channel link model was built for a 10 Gigabit network card PCB using the simulation software POWERSI; time-domain, frequency-domain, and loopback simulations were performed in ADS software using the established model; and the simulated return loss, insertion loss, and eye diagrams were analyzed to determine if the PCIe 4.0 signal traces meet design requirements. The return loss for all 8 pairs of PCIe 4.0 differential signals obtained by this method was less than -6 dB, the insertion loss was greater than -28 dB, and the eye diagram's eye width and eye height were both greater than 0.3 UI and 15 mV, respectively, satisfying the requirements of the PCIe 4.0 protocol specificati --- ## FPGA-based FPD-Link (LVDS 7:1) and FPD-Link II & III Implementation and Customization - URL: https://intl.sienovo.cn/blog/143677783 - Date: 2024-11-11 - Tags: #FPGADev This article primarily introduces the brief history of FPD-Link's development, focuses on the LVDS 7:1 technology applied in the first generation of FPD-Link, and briefly covers relevant content of the second and third generations of FPD-Link. FPD-Link (Flat Panel Display Link) is a free, royalty-free, high-speed digital video interface standard proposed by National Semiconductor (later acquired by TI) in 1996. It was primarily applied in laptops, tablet computers, early smartphones, and LCD TVs. At its inception, it aimed to address the increasing bandwidth demands of high-resolution LCD/LED displays, which traditional TTL/CMOS parallel interfaces could not meet. **1. FPD-Link and LVDS** FPD-Link was the first large-scale application of LVDS technology proposed by NS and was recognized and accepted by the industry. Because FPD-Link is a free and open standard, it has many aliases (or mutually compatible variant standards), such as FlatLink, proposed by TI in its early years. The S --- ## FPD-Link III Automotive Camera Solution Implemented with TI AM62A + FPGA - URL: https://intl.sienovo.cn/blog/143675431 - Date: 2024-11-11 - Tags: #FPGADev, #MCU, #EmbeddedHardware ### ******Functional Overview****** This module primarily features FPD-Link III / CML transceiver signals, HDMI / SDI / USB signals, and Gigabit Ethernet signals, supporting customer customization based on specified functions. The current default function is FPD-Link III / CML conversion to HDMI / SDI / UVC signals. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143675431/01_ff03fe75eccfed8d6df259cd938a2077.png) ### ******Specifications****** | Name | Description | | :--------------- | :---------------------------------------------- | | Power Supply | DC 12V | | FPD-Link RX | GM8914 | | FPD-Link TX | GM8913 | | Gigabit Ethernet | RJ45 Gigabit Ethernet (UDP - Cat6a cable recommended) | | Expansion Interfaces | | | HDMI | --- ## 【Chinese-made AI Servers】Fully Domestic PCIe 4.0/5.0 Switch GPU Expansion Solution, Supporting Platforms like Hygon/Phytium/Loongson - URL: https://intl.sienovo.cn/blog/143593552 - Date: 2024-11-07 - Tags: #Networking, #linux, #DevOps **Foreword:** A significant portion of the PCIe specification is dedicated to PCIe switches. In practical circuit applications, we often encounter scenarios where the number of PCIe ports is insufficient, requiring a switch to expand them. Currently, only Broadcom and Microchip offer PCIe Gen5-capable switches. Broadcom's PEX8900 series was released earlier, supporting PCIe Gen5 speeds, and offering both base switch mode (fanout expansion mode) and synthetic switch mode. I have experience with Broadcom's PEX89144 and PEX89104. In the practical application section below, I will focus on the considerations for PEX89144. Diodes' PI7C9X2G1616PR and Microchip's PM8536 will also be briefly analyzed. As a hardware developer, before delving into switches, it's essential to understand certain concepts from the PCIe specification. Taking Broadcom's PEX8724 as an example, parameters such as DMA, PCIe Lane/Port, transmission latency, and NT functionality must be understood to make correct swit --- ## 4-Channel PoE NVR (200m Power Supply Distance) Video Surveillance Solution - URL: https://intl.sienovo.cn/blog/143588880 - Date: 2024-11-07 - Tags: #AI, #ImageProcessing 4-Channel PoE NVR (200m Power Supply Distance) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143588880/01_145ce6c4d6bf429fa95a0c2fd45638f4.png) I. Service Parameters: 1. **Video input:** Supports 4-channel 5MP / 4-channel 1080P HD network video input, PoE network cable power supply, with an effective power supply distance of 200m. 2. **Step on the Internet:** Eliminates complex router settings. Through Xiongmai Cloud Service, various network traversals can be easily achieved, enabling remote monitoring in one step. 3. **Compression algorithm ideal:** The compression algorithm is upgraded to H.265. Advanced spatio-temporal filtering technology reduces the bitrate by over 30% compared to previous versions. 4. **Playback quality:** Supports full real-time encoding recording and full real-time multi-channel synchronous decoding playback. 5. **Main and Sub Stream:** Features simultaneous encoding of main and sub-streams. The main stream is used for local storage, ens --- ## Qualcomm QCM6125-based In-Vehicle AI Box Solution - URL: https://intl.sienovo.cn/blog/143428299 - Date: 2024-11-01 - Tags: #AI ###### Platform: QCM6125, 8-core Kryo 260 CPU, Clock Speed: 2.0GHz, 11nm Process Technology, Integrated Adreno™ 610 GPU @950MHz Memory Configuration: 4GB LPDDR4 + 64GB UFS (default) / 8GB LPDDR4X + 128GB UFS (optional) Android Version: Android 10/11/12/13 Display: Supports dual-screen independent display, 1 x 4-lane MIPI_DSI interface, maximum resolution support 2520*1080, 60fps; DP1.4 over USB Type-C, maximum support 1920*1200@60Hz Camera: 2 x 4-lane MIPI cameras, supports 16MP+16MP ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143428299/01_5b607adcb3ea48d593cf789fb59189a0.jpeg) **UART/I2C/I2S/SPI** **/SDIO:** Supports up to 3 UART interfaces Supports up to 4 I2C interfaces, for peripherals such as touchscreens, cameras, and sensors Supports up to 42 SPI interfaces Frequency Bands: LTE-FDD:B1/B2/B3/B4/B5/B7/B8/B20/B28 LTE-TDD:B38/B40/B41 WCDMA:B1/B2/B4/B5/B8 GSM:850/900/1800/1900 Video: Encoding: 4K30 HEVC/H264/VP8/MPEG4; Decoding: 4K30 8-bit: H.264/VP --- ## Urban Rail Transit: Overall Design of a Domestically Developed Onboard Central Control Unit Based on Hot Backup Technology (Part 1) - URL: https://intl.sienovo.cn/blog/143413601 - Date: 2024-10-31 - Tags: #TransportLogistics Overview It is responsible for managing communication between nodes on the vehicle bus, processing information exchange between coupled locomotives, real-time status detection of control units and data acquisition and output units, intelligent diagnosis of locomotive control system faults, and automatic identification and processing of coupled locomotive formations. Management of Communication Between Nodes on the Vehicle Bus Node devices on the vehicle bus include intelligent display units, logic control units, microcomputer control cabinets, locomotive safety information integrated monitoring devices, as well as analog input/output boards, digital outputs, digital inputs, and so on. Communication among these node devices is managed by the central control unit. When a node device on the bus fails, it generally does not affect the communication of other devices, but the entire locomotive will lose some or all functions of that device. Information Exchange Processing Between Coupl --- ## 【Rail Transit】Analysis of Fault Causes and Domestic Replacement for Locomotive Central Control Units - URL: https://intl.sienovo.cn/blog/143408059 - Date: 2024-10-31 - Tags: #TransportLogistics Overview of the Central Control System Hohhot Group Corporation in northern China experienced a locomotive upgrade and replacement, with SS4 modified electric locomotives being replaced by HXD2 high-power locomotives, which are now widely deployed. TCMS is the microcomputer network control system for these locomotives. Its network architecture consists of the Central Control Unit (MPU), Remote Input/Output Module (RIOM), Traction Control Unit (TCU), Auxiliary Control System (ACU), Brake Control Unit (BCU), and Driver Display Unit (DDU). The MPU chassis is installed in a microcomputer cabinet within the locomotive's equipment compartment. The microcomputer cabinet is divided into three layers: the bottom layer houses electrical wiring harnesses and circuit breakers, the middle layer contains the Remote Input/Output Module (RIOM2), and the top layer contains the Central Control Unit (MPU) chassis and the GW Gateway Module. The microcomputer cabinet does not have a ventilation system in --- ## 【AI Servers】Domestic PCIe 5.0 Switch SerDes Testing and Analysis, Taking an 11-slot PCIe GPU Backplane (PCIe 4.0/5.0) as an Example (Part 2) - URL: https://intl.sienovo.cn/blog/143241117 - Date: 2024-10-29 - Tags: #AI, #Server, #DevOps, #Networking 3 Comparison of PCIe 4.0 SerDes and 5.0 SerDes Requirements Table 2 summarizes the differences between PCIe 4.0 and 5.0 SerDes requirements. The PCIe standard comprises three interdependent specifications designed to ensure interoperability of SerDes and channels from different vendors: ● The PCIe BASE specification defines the chip-level performance for the entire protocol stack, a comprehensive document exceeding one thousand pages. ● The PCIe CEM (Card Electromechanical) specification defines the minimum performance of devices at the add-in card connector. ● The Test specification defines the rules for compliance testing.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143241117/01_4d058b6b6ea34389ab78d7d5509c50f4.png) As seen from Table 2, PCIe 4.0 and 5.0 share many commonalities. Both use NRZ modulation, 128B/130B encoding, the same 10^-12 bit error rate target, and have identical connector pinouts. The transmitter uses the same Feed-Forward Equalizer (FFE) sche --- ## [AI Server] All-Domestic PCIe 5.0 Switch SerDes Testing and Analysis, Taking an 11-slot PCIe GPU Backplane (PCIe 4.0/5.0) as an Example (Part 1) - URL: https://intl.sienovo.cn/blog/143241053 - Date: 2024-10-25 - Tags: #Networking 1 PCIe Gen 5 Introduction Peripheral Component Interconnect Express (commonly known as PCI Express and abbreviated as "PCIe") is an advanced interconnect I/O technology used for hard disk drives, solid-state drives (SSDs), graphics cards, Wi-Fi, and internal Ethernet connections, comprising a set of fast, scalable, and reliable input/output standards for serial data transfer buses. The physical layer of PCIe also supports Serial Advanced Technology Attachment Express (SATAe) and Non-Volatile Memory Express (NVMe). Table 1 shows the evolution of PCIe data rates. From this, it can be seen that the 5th generation PCIe 5.0 doubles the throughput of its predecessor, PCIe 4.0. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143241053/01_2034cbb956ec45e5b10df2c2b6c8c311.png) Note: The 8B/10B encoding scheme of PCIe 2 evolved into the 128B/130B encoding scheme of PCIe 3, with the corresponding overhead decreasing from 20% to less than 2%, the raw transfer rate increasing from --- ## Signal Integrity Design and Implementation of Locally-Produced PCIe 4.0/5.0 Switches for AI Server HBA Cards, Customizable (Part 2) - URL: https://intl.sienovo.cn/blog/143240997 - Date: 2024-10-25 - Tags: #Server, #DevOps, #AI ![](https://pub-048dcb96257f476697b113fcb5939cb39cb9.r2.dev/blog/143240997/01_cccd4d7e74f14dc38c58754645623f08.png) Table 2 shows the relative permittivity and loss tangent at different frequencies for the selected PCB dielectric materials: PSR4000AUS703, R-5670G-3313, R-5775G-3313, R-5670G-2116 x3, and R-5775G-2116. The R-5670G/R-5775G materials chosen for this design are resin-based laminates from the high-performance, ultra-low loss category, offering very low dielectric constant and loss tangent, excellent moisture and chemical resistance, good resistance to Conductive Anodic Filament (CAF), and strong thermal stability, among other advantages. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143240997/02_ff79a37e703848fd8d81f0884841ee82.png) Many design challenges were encountered during the design process. Initially, factors affecting signal integrity were not fully considered, leading to poor signal integrity. Therefore, the design files were modified. For exampl --- ## Signal Integrity Design and Implementation of Domestic PCIe 4.0/5.0 Switches for AI Server HBA Cards (Part 1) - URL: https://intl.sienovo.cn/blog/143240865 - Date: 2024-10-25 - Tags: #AI, #Server, #DevOps 0 Introduction A Host Bus Adapter (HBA) is a circuit board or integrated circuit adapter that provides a physical connection between a computer or server and storage devices [1]. In addition to physical connection, HBAs also perform input/output processing. By using an HBA adapter card, the host's microprocessor does not need to perform data storage and retrieval operations, thereby improving server performance [2]. Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard. PCIe 1.0 achieves a single-lane speed of 2.5 Gb/s, while the standard transmission rate for PCIe 4.0 is as high as 16.0 Gb/s. At such high transmission rates, ensuring the signal integrity of Printed Circuit Board (PCB) routing is extremely important [3-4]. Win et al. [5] proposed a new specification technique that can accurately test the frequency domain channel bit error rate parameters of high-speed differential interfaces on PCBs, including parameters such as inser --- ## AI Server PCIe Topology and PCIe 4.0 x16 Riser Card Application Research Based on Domestic PCIe 4.0/5.0 Switches (Part 4) - URL: https://intl.sienovo.cn/blog/143240638 - Date: 2024-10-25 - Tags: #AI, #Server, #DevOps GPU PCIe Topology Switching Design in AI Servers For different deep learning training models, combined with practical application scenarios, it is often necessary to switch between different GPU PCIe topologies within the same server to optimize performance. Manually changing cable connections requires opening the chassis, which is not user-friendly and may lead to workplace injuries such as cut fingers for maintenance personnel. The following 2 solutions can achieve BMC (Baseboard Management Controller) remote one-click topology switching. (1) GPU Topology Remote One-Click Switching Based on PCIe Switch FW Technology As shown in Figure 11, Port0 of PCIeSwitch0 is always an upstream port, and Port1 is always a downstream port; Port0 of PCIeSwitch1 is always an upstream port, and Port1 is always an upstream port. The topology switching is achieved by configuring the FW of PCIeSwitch1 or sending configuration commands to PCIeSwitch1. ![](https://pub-048dcb96257f476697b113fcb5939cb9 --- ## PCIe Topology for AI Servers Based on Domestic PCIe 4.0/5.0 Switches and Application Research of PCIe 5.0 Retimer Cards (Part 3) - URL: https://intl.sienovo.cn/blog/143235350 - Date: 2024-10-25 - Tags: #AI HPL Performance Analysis HPL (High-Performance Linpack) tests can characterize the performance of the three topologies in double-precision floating-point operations. The HPL performance test results for the three topologies—BalanceMode, CommonMode, and CascadeMode—are shown in Table 3. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143235350/01_4881bc6774954f2e936eb491a46c25ef.png) To clearly characterize the performance differences of the three topologies in HPL performance tests, taking BalanceMode's test score as the baseline, the proportion of HPL performance test scores for Common Mode and Cascade Mode relative to BalanceMode's score is obtained, as shown in Figure 6. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143235350/02_7adbba8a987b4b13bffaa728bc5a8b45.png) HPL tests require the use of processors and main memory. Due to the increased uplink bandwidth and memory utilization of dual-root topologies, performance will be superior to single-root --- ## PCIe Topology for AI Servers Based on Domestic PCIe 4.0/5.0 Switches and Application Research of 12Gb SAS Expander Multi-bay Backplanes (Part 2) - URL: https://intl.sienovo.cn/blog/143235135 - Date: 2024-10-25 - Tags: #AI 2.2 Topology Characteristics Analysis The BalanceMode configuration evenly distributes GPUs across 2 CPUs, resulting in higher total upstream PCIe bandwidth for the GPUs. CommonMode can, to some extent, satisfy point-to-point communication between GPUs while ensuring sufficient I/O bandwidth between CPUs and GPUs. CascadeMode has only one ×16 link, but because GPUs are daisy-chained through PCIe Switches, it improves point-to-point performance and reduces latency. For double-precision floating-point operations, GPU computation requires the use of processors and main memory. Due to the increased upstream bandwidth and memory utilization of the Dualroot topology, its performance will be superior to that of the Singleroot topology. For deep learning inference performance, GPUs with parallel computing capabilities can perform billions of computations based on trained networks, thereby quickly identifying known patterns or targets. The interconnection relationships between GPUs differ a --- ## Research on PCIe Topology Applications in AI Servers Based on All-Domestic PCIe Switch 4.0/5.0 (Part 1) - URL: https://intl.sienovo.cn/blog/143234745 - Date: 2024-10-25 - Tags: #AI 1 Introduction To meet the data collection and processing demands in fields such as big data, cloud computing, and artificial intelligence, various forms of heterogeneous AI servers have been widely adopted. CPU+GPU is a commonly used computational unit combination in AI servers \[1]. Among these, P2P (Peer-to-Peer) communication is used in multi-GPU systems, and with the aid of caching devices, PCIe resources can be effectively utilized for data exchange between GPUs \[2]. For GPU-accelerated applications, the industry has seen research focused on various software tools, hardware configurations, and algorithm optimizations. In 2016, Shi et al. \[3] compared software tools for GPU-accelerated deep learning (Caffe, CNTK, TensorFlow, and Torch, etc.) through performance benchmarking. In 2018, Xu et al. \[4] investigated the combined effects of software and hardware configurations, identifying the application characteristics and functionalities of different open-source deep learning fr --- ## Application of RK3568-based Energy Storage Technology ECU in Power Systems - URL: https://intl.sienovo.cn/blog/143205793 - Date: 2024-10-24 - Tags: #ProgrammerDay Research on the Application of Energy Storage Energy Management Units (EMU) in Power Systems and the Implementation of Primary Frequency Regulation AGC-AVC Functions: **Abstract:** With the rapid development of renewable energy and the intelligent transformation of power systems, energy storage technology and its management systems are playing an increasingly important role in power systems. The Energy Storage Energy Management Unit (EMU), as the core controller of energy storage systems, possesses functions such as monitoring, control, optimization, and dispatch. This paper first introduces the basic concepts and functions of Xinmai Energy Storage EMU, then discusses in detail the application of EMU in different fields through specific examples, and analyzes how EMU achieves primary frequency regulation (AGC) and (AVC) functions to improve power system stability and energy utilization efficiency. **Keywords:** Energy Storage Energy Management Unit; Primary Frequency Regulation; Au --- ## RK3588/Sophon BM1684 AI Box-Based: Integrated Video Intelligent AI Analysis System Construction Plan (Part Five) Edge Box and AI Server - URL: https://intl.sienovo.cn/blog/143108516 - Date: 2024-10-21 - Tags: #AI 1. 1. **Solution Hardware Introduction** 1. **Intelligent AI Analysis Server** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143108516/01_36b98949d0ef4669b72bef224a8bbfab.png) Model: 2U Rackmount Server Processor: CPU\_Xeon\_5318Y\_2.1GHz\_24C\_48T\_165W\*2 Memory: 32GB DDR4 3200 RDIMM\*4 240GB 2.5in (SATA SSD)\*1 Hard Drive: 6 TB, SATA 6Gb/s, 7.2K, 3.5in (SATA HDD)\*1 Network Card: Dual-port Gigabit PCIe Network Card, 1× Independent Management Port GPU Card: SC7-75 \*7 Power Supply: 1600W 1+1 Redundant Power Supply, Standard Rack Rails. The intelligent AI analysis server supports real-time analysis of 600 video channels. Each device can deploy 30+ types of algorithms, with each video stream supporting 3 algorithms for simultaneous analysis. It also supports algorithm polling analysis, making it suitable for large-scale cluster deployment in server rooms. Note: On-site server bandwidth must be above 1000Mbps. 1. 1. 1. **Intelligent Edge Applian --- ## Based on RK3588/SOPHGO BM1684 AI Box: Comprehensive Video Intelligent AI Analysis System Construction Plan (Part 4) Area Intrusion, Work Uniform, Making Calls, and Using Mobile Phone Scenarios - URL: https://intl.sienovo.cn/blog/143108433 - Date: 2024-10-21 - Tags: #AI, #AudioVideo, #ComputerVision 1. 1. 1. **Area Entry Detection Algorithm** 1. **Function Description** Area entry detection involves presetting a monitoring area in a surveillance scene and triggering an alarm when people or vehicles are detected entering that area. The resolution of detected targets in a 1080p image should be no less than 30*30 pixels. 1. 1. 1. 1. **Recommended Scenarios** Scenario Requirements: Can be used indoors and outdoors. Avoid direct sunlight or backlight conditions. At night, only full-color images are supported; if the camera does not support full-color mode, please use white light for supplementary illumination. Target Distance Requirements: Can detect events beyond 3 meters from a normal 3-meter pole height. Target Pixel Requirements: The resolution of detected targets in a 1080P image should be greater than or equal to 30*30 pixels. Recall Rate: 95% ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/143108433/01_6cfe2fda07f941ac878c0ddb835859a9.png --- ## Based on RK3588/Sophon BM1684 AI Box: Integrated Intelligent Video AI Analysis System Deployment Plan (Part 3) Hard Hat, Drowsiness/Absence from Post Detection, Electric Vehicles, Smoking Scenarios - URL: https://intl.sienovo.cn/blog/143108333 - Date: 2024-10-21 - Tags: #AI, #AudioVideo, #ComputerVision 1. 1. 1. **Hard Hat and Reflective Vest Detection Algorithm** 1. **Function Description** Hard hat and reflective vest detection involves pre-setting a monitoring area in a surveillance scene. If personnel within this area are not wearing a hard hat or reflective vest, an alarm is triggered promptly. The detected target's resolution in a 1080p image should be no less than 30*30 pixels. 1. 1. 1. 1. **Recommended Scenarios** Scenario Requirements: Suitable for indoor and outdoor use, avoiding direct sunlight or backlight conditions; at night, only full-color images are supported. If the camera does not support full-color mode, please use white light for illumination. Target Distance Requirements: Events beyond 3 meters can be detected from a standard 3-meter pole height. Target Pixel Requirements: The detected target's resolution in a 1080P image should be greater than or equal to 30*30 pixels. Recall Rate: 95% ![](https://pub-048dcb96257f476697b113fcb5939cb9. --- ## RK3588/Sophon BM1684 AI Box-Based: Integrated Video Intelligent AI Analysis System Construction Plan (Part Two) Smoke and Fire Detection, Unattended Object Detection, Lane Occupancy Detection - URL: https://intl.sienovo.cn/blog/143108208 - Date: 2024-10-21 - Tags: #AI, #AudioVideo, #ComputerVision 1. 1. 1. **Smoke and Fire Detection Algorithm** 1. **Function Description** Smoke and fire detection refers to presetting a monitoring area in a surveillance scene, and triggering an alarm when smoke or fire occurs within that area. The detection distance is 10-20 meters, and the resolution of smoke and fire in a 1080p image should be ≥ 30*30 pixels. 1. 1. 1. 1. **Recommended Scenarios** Scene requirements: Can be used indoors and outdoors, avoid direct sunlight or backlight conditions; only supports full-color images at night, if the camera does not support full-color mode, please use white light for illumination. Target distance requirements: Can detect events beyond 3 meters from a normal 3-meter pole height. Target pixel requirements: The resolution of the detected target in a 1080P image should be ≥ 30*30 pixels. Flame colors: Supports detection of red, orange, and yellow flames. Smoke colors: Supports detection of irregular smoke such as off-white and --- ## Based on RK3588/Sophon BM1684 AI Box: Integrated Video Intelligent AI Analysis System Construction Plan (Part 1) - URL: https://intl.sienovo.cn/blog/143108093 - Date: 2024-10-21 - Tags: #AudioVideo, #AI 1. ******Construction Background****** To actively respond to the nation's five major development concepts of "innovation, coordination, green, openness, and sharing," and to implement the relevant policy requirements of "Made in China 2025" and the "Guiding Opinions of the State Council on Actively Promoting the 'Internet+' Action," combined with the factory's current situation, production status, existing problems, and future development planning needs, it is proposed to comprehensively optimize, upgrade, and transform its process flows, green environmental protection, and intelligent manufacturing aspects. The goal is to build the enterprise into a domestic first-class, green, and intelligent production base, achieving a dual improvement in quality and efficiency. "Made in China 2025" is China's version of the "Industry 4.0" plan. The plan, approved by Premier Li Keqiang, was officially released by the State Council on May 8, 2015. Miao Wei, Minister of Industry and Information --- ## Verifying Ethernet Driver Hooks on an NXP LS1043 + FPGA ARM64-bit Platform - URL: https://intl.sienovo.cn/blog/142923377 - Date: 2024-10-14 - Tags: #ARMDev, #FPGADev I previously validated Ethernet driver transmit/receive hooks on an X86 platform. Today, I specifically deployed the code to an LS1043 board to verify its feasibility. Board Environment: LINUX 4.19.68 Cross-compiler: [GCC](https://so.csdn.net/so/search?q=GCC&spm=1001.2101.3001.7020 "GCC") 7.5.0 [CPU](https://so.csdn.net/so/search?q=CPU&spm=1001.2101.3001.7020 "CPU"): NXP LS1043 ARMV8 A53 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142923377/01_5082ee083fbc455d8654a10f754c09ad.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142923377/02_2d95f3d1f73d41bba4b4846edb793a01.png) The test code is as follows: ```hljs #include #include #include #include #include #include #include #include #include #include #include #include #include 1x RS232
1x PS/2
1x VGA
4x Button Inputs | | Debug Interface | JTAG / COP debug port | ### Description The NXP IMX6 is a powerful processor that provides a high level of performance and efficiency. The board' --- ## NXP LS1046 + FPGA-based 3U CPCI Multi-Port Network Solution for Rail Transit, Supporting QNX/VxWorks/Linux - URL: https://intl.sienovo.cn/blog/142628481 - Date: 2024-09-29 - Tags: #FPGADev Rail transit systems demand computing platforms that can handle real-time network aggregation, deterministic timing, and extended environmental operating ranges — all within strict form-factor constraints. This post covers a family of three embedded computing modules built around the NXP LS1046A processor and FPGA acceleration, designed specifically for rail transit network infrastructure and certified to operate under QNX, VxWorks, and Linux. ## Why LS1046A for Rail Transit Networking The NXP LS1046A is a quad-core ARM Cortex-A72 SoC clocked at up to 1.4 GHz. Beyond raw compute, what makes it well-suited to network-intensive rail applications is its integrated packet-forwarding engine and hardware-accelerated cryptography — allowing it to move and inspect traffic at line rate without burdening the application cores. The SoC also supports ECC memory, which is mandatory for safety-critical transportation environments where silent data corruption is unacceptable. All three modules in --- ## CPCI-Compatible Rail Transit Health Monitoring Data Acquisition and Analysis Solution Based on NXP LS1043 + FPGA - URL: https://intl.sienovo.cn/blog/142628023 - Date: 2024-09-29 - Tags: #FPGADev Rail transit fleets operate under punishing duty cycles — vibration, temperature swings, and continuous 24/7 loads that would shorten the life of commodity hardware within months. Health monitoring systems on trains and metro lines must therefore combine real-time signal acquisition with deterministic edge processing, all within a ruggedized, hot-swap-capable chassis standard. This post covers Sienovo's CPCI-compatible data acquisition and analysis boards built around the NXP LS1043 processor paired with FPGA fabric, and explains why this architecture is well-suited to rail transit health monitoring applications. ## Why NXP LS1043 + FPGA for Rail Applications The NXP LS1043A is a quad-core ARM Cortex-A53 SoC designed for embedded networking and industrial control. Running at up to 1.2 GHz in these configurations, it brings enough compute headroom to run Linux-based condition-monitoring software, protocol stacks, and on-board analytics simultaneously, without the power envelope or coo --- ## AM6254+FPGA-based In-vehicle Central Control Board, Supporting PC104, QNX, VXWORKS - URL: https://intl.sienovo.cn/blog/142627873 - Date: 2024-09-29 - Tags: #FPGADev The Sienovo AM6254+FPGA in-vehicle central control board is a ruggedized embedded computing platform designed for demanding transportation and industrial automation applications. Built around Texas Instruments' AM625X processor family and paired with an FPGA co-processor, this PC104-form-factor board targets deployments where deterministic real-time performance, broad OS compatibility, and vehicle-grade I/O are non-negotiable requirements. ## Processor and Platform At the heart of the board is the **TI AM625X**, clocked at up to 1.4 GHz. The AM625X (Sitara™ family) is a high-integration SoC that combines application-class ARM Cortex-A53 cores with integrated peripherals well-suited to industrial HMI and edge-control workloads. The 1.4 GHz ceiling delivers enough compute headroom for lightweight vision pipelines, protocol translation, and display management without the thermal penalties of higher-power embedded processors — a practical tradeoff for sealed enclosures with limited airfl --- ## AM64X+FPGA-Based Control and Protection Solution for UHV Power Transmission, Supporting VXWORKS - URL: https://intl.sienovo.cn/blog/142585079 - Date: 2024-09-27 - Tags: #FPGADev ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142585079/01_972aae0bfb5c40739468b55d75090fd3.png) AM64X+FPGA-Based Control and Protection Solution for UHV Power Transmission, Supporting VXWORKS Specification Description Processor 1 Dual-core 64-bit Arm Cortex-A53 at up to 1.0GHz Operating System LINUX, VXWORKS Storage 2GB DDR4, 8GB EMMC, QSPI Interfaces • 2x 10/100/1000 Mbps ETH • 5x 10/100Mbps ETH • 2x 100/1000 Base-FX • 1x IRIGB • 2x CANFD • 1x Debug RS232 • 15x PCIe • IRIGB Debug Interface JTAG / COP debug port UHV Transmission and Substation Monitoring System Architecture Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142585079/02_0b5201416cb14d5e9413bbf300abe469.png) UHV Protection Device Schematic Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142585079/03_5fa46983b15344ee9dffeb8c15382b00.png) Technical Advantages **Main Equipment Typical Configuration Table** **Category** **Type** **Main Func --- ## Power Low-Voltage Protection Main Control Board Solution Based on AM62x/AM64x + FPGA - URL: https://intl.sienovo.cn/blog/142584628 - Date: 2024-09-27 - Tags: #FPGADev ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142584628/01_7347bac726a3461b8e77cbeb695d34a9.png) Power Low-Voltage Protection Main Control Board Solution Based on AM62x + FPGA Specification Description Processor AM6231 at up to 1.2GHz Operating System VXWORKS Storage DDR4, 8GB EMMC Interfaces • 1x 10/100Mbps ETH • 1x USB2.0 • 6x KEYPAD Inputs • 1x RS485 • 1x IRIGB • 1x RS232 Debug Interface JTAG / COP debug port 0 Introduction As industrial users demand higher power supply reliability, digital protection and control devices are becoming increasingly widespread in industrial applications. Current low-voltage integrated protection devices on the market are based on a dual-CPU architecture of DSP and MCU, where the DSP is responsible for logic function calculations, and the microcontroller handles interface display and keyboard input. With the continuous advancement of IT technology, this architecture offers relatively low performance, with less fluid L --- ## Vehicle AI Box: AI-Based 360-Degree Surround View Safety Monitoring Solution for Excavators and Construction Vehicles - URL: https://intl.sienovo.cn/blog/142389784 - Date: 2024-09-20 - Tags: #AI ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142389784/01_20b203ab28a3437f8b6868710586a947.png) Reconstructing risk control service models with big data, aligning with enterprises' development trend of "reducing costs and increasing efficiency." ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142389784/02_31c59f98a33e43ecb5920d078d571fff.png) 2.1.1 DMS Safe Operation System Upgrade DMS (Driver Monitor System) is an abbreviation for Driver Monitoring System, which refers to an information technology system that continuously monitors the driver's fatigue status and dangerous driving behaviors during vehicle operation. Upon detecting driver fatigue, yawning, squinting, or other incorrect driving states, the DMS system will promptly analyze these behaviors and provide audible and visual alerts, serving to warn the driver and correct incorrect driving behaviors. DMS is generally divided into active DMS and passive DMS. Passive DMS judges the driver's state b --- ## AI Image Transmission Solution Based on Qualcomm Platform - URL: https://intl.sienovo.cn/blog/142388077 - Date: 2024-09-20 - Tags: #AI, #AudioVideo ### AI Image Transmission ###### Comprehensive Coverage of Various Network Standards Supports LTE Cat 6 and 2x20MHz carrier aggregation, with a maximum downlink speed of up to 300Mbps. ###### Supports dual camera functionality, with support for up to 4 cameras Supports dual-screen display with independent content and dual-touch control. The main screen supports up to 1920x1200 @60fps, and the auxiliary screen supports up to 1920x1080 @60fps. ###### Supports 1080P @60fps video recording and playback Integrated multi-constellation GNSS receiver, meeting the demand for fast and precise positioning in various environments. ![Fanconn](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142388077/01_ef22ba5de6cec1aebbe7900a0fc2781f.png) ![Fancon](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142388077/02_26ffb5588d27af9301bfd0c638bb1d3a.jpeg) ![Fanconn](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142388077/03_3b9207fa0b926cdfec00bd615936829c.jpeg) --- ## AI Mainboard/Edge AI Box Based on Qualcomm Snapdragon 845, Supporting On-device AI Algorithm Deployment and Customization - URL: https://intl.sienovo.cn/blog/142387195 - Date: 2024-09-20 - Tags: #AI #### Product Features: Qualcomm Snapdragon 845 SOC Qualcomm X55 5G Modem 4K 30 fps Output Gigabit Ethernet Bluetooth 5.0 Rich IO Interfaces ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142387195/01_c23eaf2bb0cb64bb806e26310d09e4ec.png) High Performance Running Android 9, offering powerful performance. Qualcomm SDA845 64-bit Processor; H.265 Hardware Decoding. Smart power management circuit, highly integrated design. The entire board features an industrial design, supports common external devices, and offers rich interfaces. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142387195/02_797a3a491eba992c58e6d0fb2190c36c.png) High-Speed Mobile Connectivity Nano SIM card slot, allowing you to access the internet using mobile services. Supports 5G and LTE-A with comprehensive network coverage, including NSA and SA modes. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142387195/03_e444405054d3754bbc24c09152d4732c.png) Industrial Standard --- ## High-Performance SDM660-Based HD Video, Multimedia, and AI Solution - URL: https://intl.sienovo.cn/blog/142386132 - Date: 2024-09-20 - Tags: #AudioVideo #### Key Features: Qualcomm Octa-core 64-bit ARM Cortex-A53 Processor Integrated LTE Cat 6 Connectivity Qualcomm AdrenoTM 506 GPU Android 7.1/9.0 Rich I/O Interfaces ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142386132/01_672901a1e0f7c6501efcc65c8de2ddf5.png) Qualcomm Octa-core Processor Equipped with the new generation high-performance SDM660 custom 64-bit ARM processor (Kryo260 CPU): KryoGold quad-core high-performance processor @ 2.2 GHz, 1 MB L2; KryoSilver quad-core low-power processor @ 1.843 GHz, 1 MB L2; Qualcomm® KryoTM 385 64-bit CPU + AdrenoTM 630 GPU. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142386132/02_febcca3ce90cc8dc27c4fa224c708e3e.png) High-Speed 4G LTE Mobile Connectivity Cat 6, 300Mbps Downlink / 50Mbps Uplink ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142386132/03_1f90a56ef50c32f5fb389f3e2df10d8c.png) Highly Integrated Integrates multiple functions such as HDMI, Ethernet, USB, Microphone, Wi-Fi, --- ## Qualcomm Snapdragon 865-based Multimedia + AI Computing Motherboard/All-in-One Solution, Supporting Motherboard and AI Algorithm Customization - URL: https://intl.sienovo.cn/blog/142385894 - Date: 2024-09-20 - Tags: #AI #### #### Product Features: Qualcomm Snapdragon 865 SOC Qualcomm X55 5G Modem 4K 30 fps Output Gigabit Ethernet, Bluetooth 5.0 Rich I/O Interfaces ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142385894/01_9ea72916bd65229b6849959576e52121.png) High Performance Powered by Android 9, offering powerful performance. Qualcomm SDA845 64-bit processor; H.265 hardware decoding. Intelligent power management circuit, highly integrated design, industrial-grade board design, supports common external devices, rich interfaces. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142385894/02_040fa98038cd11f2ce015a90eca5022e.png) 5G High-Speed Mobile Connectivity Nano SIM card slot, allowing you to access the internet using mobile services Supports comprehensive coverage of 5G and LTE-A multiple network standards, including NSA and SA modes. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142385894/03_bbfcad1a6c3d683c6f978e2f6683e9c8.png) Industrial --- ## Snapdragon AI Box based on Qualcomm SDM450 Chip, Face Payment Terminal - URL: https://intl.sienovo.cn/blog/142385175 - Date: 2024-09-20 - Tags: #AI #### Product Features: Qualcomm Octa-core 64-bit ARM Cortex-A53 Processor Built-in LTE Cat 6 Communication Capability Qualcomm Adreno™ 506 GPU Android 7.1/9.0 Rich IO Interfaces Qualcomm Octa-core Processor The Qualcomm Octa-core 64-bit ARM Cortex-A53 processor supports multi-network Smart LTE Cat 6 communication, features a built-in Qualcomm Adreno™ 506 GPU, and runs on the Android 7.1 operating system. It boasts an intelligent power management circuit, a highly integrated design, and an industrial-grade board layout, supporting common external devices with rich interfaces. High-Speed 4G LTE Mobile Connectivity Cat 6, 300Mbps Downlink / 50Mbps Uplink Industrial Standard, Stable and Reliable Uses industrial-grade modules, resistant to low and high temperatures. Undergoes stability testing to ensure system reliability. Guarantees 7x24 uninterrupted operation without crashing. ![Fanconn](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142385175/01_c4616a09b30abfc0eb --- ## AI and Edge Computing Large Model Appliance Based on Sophon/NVIDIA Jetson, Applied in In-Vehicle AI Boxes / AI-Assisted Driving Technology, etc. - URL: https://intl.sienovo.cn/blog/142367071 - Date: 2024-09-19 - Tags: #AI, #Server I. Leading new industry trends, tailor-made for assisted driving scenarios! This cutting-edge product, based on NVIDIA Jetson AGX Orin, with its outstanding performance and broad application potential, is rapidly sparking a technological revolution in fields such as autonomous delivery, smart inspection, and smart parks. As a leader in next-generation edge computing solutions, it integrates the computing power of NVIDIA Jetson AGX Orin, providing up to **200/275 TOPS** of computing power (user-selectable). This exceptional performance allows it to effortlessly handle massive data and execute complex computing tasks, providing continuous power for assisted driving scenarios. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142367071/01_dd9d8f8c50e84f25a3d8fa8f14fe4cad.png) **2** **Stable and Precise, Secure and Reliable** In critical scenarios such as autonomous driving and autonomous delivery, stable and reliable quality is paramount. Equipped with professional **Fak --- ## Domestic PCIe 4.0/5.0 Switch Chips and Military CPUs - URL: https://intl.sienovo.cn/blog/142218399 - Date: 2024-09-13 - Tags: #AI, #Server The XM series complies with the VITA 75 form factor standard, meeting the demand for high-performance graphics processing in land, sea, and air vehicles. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142218399/01_4ad2b2335a4e4e92b375dd368ff8f0d7.png) Introducing the compact, ultra-rugged military computer – the XM series, equipped with Intel Core i7 dual-core or quad-core processors and featuring up to 16GB of DDR3L-1333 ECC on-board memory. The sealed vacuum chassis design complies with IP67 waterproof and dustproof ratings, paired with MIL-DTL-38999 military-grade high-speed interfaces, and complies with VITA 75 design standards. Its volume is reduced by nearly 30% compared to major competing products on the market [Note 1], meeting the SWaP (Size, Weight, and Performance) requirements of modern military applications and suitable for various new military land, sea, and air vehicle applications. “The XM series is characterized by providing high-end functionality in --- ## 【AI Domestic Servers】Temporary Solution for Nvidia Cards Experiencing HW Power Brake Slowdown, Domestic PCIe 4.0/5.0 Switches for GPU Expansion Cards, NVMe Storage Cards, Replacing Broadcom - URL: https://intl.sienovo.cn/blog/142217988 - Date: 2024-09-13 - Tags: #AI, #Server After installing a new Tesla graphics card, the power consumption consistently failed to reach its potential. With a 250W TDP, it could only reach 70W under full load. Ubuntu didn't show core frequency information, so I had to use `nvidia-smi -q -d PERFORMANCE` to diagnose the issue: ``` ~$ nvidia \-smi -q -d PERFORMANCE   \==============NVSMI LOG \==============   Timestamp                                 : Sun Oct 23 12:36:25 2022 Driver Version                            : 515.65.01 CUDA Version                              : 11.7   Attached GPUs                             : 1 GPU 00000000:84:00.0     Performance State                     : P0     Clocks Throttle Reasons         Idle                              : Not Active         Applications Clocks Setting       : Not Active         SW Power Cap                      : Not Active         HW Slowdown                       : Active             HW Thermal Slowdown           : Not Active           --- ## AI Domestic Servers: GPU Power Brake, Domestic PCIe 4.0/5.0 Switches for GPU Expansion Cards and NVMe Storage Cards, Replacing Broadcom - URL: https://intl.sienovo.cn/blog/142217808 - Date: 2024-09-13 - Tags: #Server, #AI Power brake is categorized into proactive and reactive triggers. Proactive Trigger (Proactive) Operational Steps: 1. Enter UEFI --》 Select System Settings --》 Select Power --》 Change the "PCIe Power Brake" option to "Proactive" --》 Shut down 2. The installed PSU must comply with the following requirements: (The machine's total power wattage must exceed 1/3 of the PSU's wattage) 3. Powering on will trigger the power brake, and you will see the effect shown in "【Figure 1】" in the XCC web events log. 4. Run a GPU stress test, and you will see the effect shown in "【Figure 2】". (GPU power is not running at full capacity) Reactive Trigger (Reactive) Operational Steps: 1. Enter UEFI --》 Select System Settings --》 Select Power --》 Change the "PCIe Power Brake" option to "Reactive" --》 Restart and enter the OS 2. Unplug a fan. (Some machines may require heating with a hairdryer) 3. Shortly after, you will see the effect shown in "【Figure 1】" in the XCC web events log. (XCC has already trig --- ## Zhongxing Micro: Domestic Loongson + PCIe 4.0/5.0 Switch + GPU Expansion Card Solution with NVMe Hybrid Direct-Connect Backplane - URL: https://intl.sienovo.cn/blog/142145056 - Date: 2024-09-11 - Tags: #AI, #Server \*Hot-swappable hard drives; \*LED indicators for drive power, read/write activity, and error status; \*SPGIO drive error reporting function; \*Staggered drive spin-up; \*Fan temperature control; \*I2C (BMC); ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142145056/01_1a7b89b831b44f14bde73f253faa1dd4.png) Loongson Server: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/142145056/02_edaad37705db43d496ffbe4a9d3b1659.png) Item Parameter CPU Loongson 3A3000 processor, 4 cores, main frequency 1.2-1.5GHz Operating System Optional support for domestic operating systems such as Kylin, Deepin, and Puhua Firmware Domestic Kunlun firmware Hard Drive 2.5-inch/3.5-inch SATA hard drive, capacity no less than 500GB, maximum support 4TB Memory DDR3, maximum support 16GB Optical Drive Built-in DVD burner Display Standard discrete graphics card with 1GB VRAM, supports integrated graphics System Specifications System weight: ≤9kg (under standard configuration); Maximum sys --- ## Fully Domestic Phytium-based PCIe 4.0/5.0 Switch + GPU Expansion Card Solution - URL: https://intl.sienovo.cn/blog/142130987 - Date: 2024-09-11 - Tags: #AI, #Server As AI inference workloads push server interconnect bandwidth to its limits, system integrators face a familiar bottleneck: how do you fan out a single CPU's PCIe lanes to a full rack of GPUs without resorting to foreign silicon? Shenzhen Xinmai (深圳信迈) has developed a fully domestic solution built around Phytium-compatible infrastructure — a PCIe 4.0/5.0 Switch-based GPU expansion card paired with an NVMe hybrid backplane — that addresses this problem end-to-end while supporting OEM/ODM customization. ## The PCIe Switch GPU Expansion Card The expansion card sits at the heart of the solution. Its role is to take high-bandwidth PCIe host links from the server CPU and distribute them across a dense array of GPU slots, effectively acting as a non-blocking PCIe fabric within a single chassis. The card's key specifications are: - **1 direct-connect single-width slot** — allows a primary accelerator or NIC to connect to the host with minimal hop latency - **14× SFF-8654 x4 PCIe 4.0/5.0 host --- ## This Broadcom PCIe Switch Chip Soared to 140,000 RMB. Domestic Replacement is Imperative! - URL: https://intl.sienovo.cn/blog/142085763 - Date: 2024-09-10 - Tags: #AI The Chinese source mentions "深圳信迈" exactly once — in the final promotional line after the conclusion. That line is entirely absent from the truncated English. I'll append it as the minimal restoration. The AI sector is overcrowded. Even with all the most expensive GPUs for AI servers assembled, shipments are being held up due to a "chip shortage." "We looked for a thousand pieces overseas, but still couldn't get enough. It's too difficult." "When we tried to procure AI servers from suppliers, shipments couldn't be arranged because the motherboards were **missing Broadcom's PCIe Switch 4.0 chips**. Now they're searching everywhere for them." PCIe Switch chips, represented by Broadcom's SS26, have seen exceptionally high demand recently. Not only is spot supply scarce, but quotes have also **skyrocketed from $5,500 to $20,000**! No wonder AI server prices are rising. Once you dive into the deep sea of AI, it turns out it's not just GPU prices that are increasing... Reading this artic --- ## What is a PCIe Switch? Domestic PCIe Switch Solutions: Zhongxingwei - URL: https://intl.sienovo.cn/blog/142084514 - Date: 2024-09-10 - Tags: #Server, #Networking, #linux ### What is a PCIe Switch A PCIe Switch is a hardware device that provides expansion or aggregation capabilities, allowing more devices to connect to a single PCIe port. It offers the following functionalities: 1. **Connecting Multiple Devices**: A PCIe switch allows multiple devices to connect to a host system via a single PCIe bus, thereby expanding the system's connectivity. 2. **Data Exchange**: A PCIe switch can transfer data between multiple devices, allowing direct communication between devices without involving the host processor. 3. **Dynamic Allocation**: It supports dynamic allocation of bandwidth and resources, adjusting communication rates and priorities between devices as needed. 4. **NTB (Non-Transparent Bridge)**: It supports NTB technology, allowing direct communication between two or more systems, thereby improving data transfer efficiency. 5. **Peer-to-Peer**: It supports peer-to-peer communication, allowing devices to exchange data directly without involvin --- ## ARM+Codesys+AGV Mobile Robot Control System Based on Industrial Raspberry Pi - URL: https://intl.sienovo.cn/blog/142032301 - Date: 2024-09-08 - Tags: #AI, #EmbeddedHardware **Introduction** The COVID-19 pandemic that erupted in 2020 amplified human vulnerability to natural risks and further promoted the application of AGVs and similar technologies in various fields. An Automated Guided Vehicle (AGV) is a type of mobile robot primarily used for storing and transporting various materials, providing a crucial guarantee for system flexibility, integration, and efficient operation, and holding an important position in modern manufacturing enterprise logistics systems. 01 **Application Background** With the advent of the 5G era, many AGV companies have realized that endowing mobile robots with more "from vehicle to robot" concepts, riding the 5G wave, and promoting intelligent transformation is the general trend for mobile robot enterprises. 5G networks will seamlessly connect production equipment, meeting the demands for device interconnection and remote interaction applications in industrial environments. With continuous coverage of highly reliable netwo --- ## ARM+Codesys+AGV Motion Controller Solution, Customizable - URL: https://intl.sienovo.cn/blog/142032215 - Date: 2024-09-08 - Tags: #ARMDev ## ARM + CODESYS + AGV Motion Controller: A Customizable Edge-AI Motion Control Platform Autonomous Guided Vehicles (AGVs) demand precise, real-time motion control combined with flexible I/O and industrial communication protocols. Sienovo's ARM-based AGV Motion Controller integrates the CODESYS runtime with a purpose-built hardware platform, giving engineers a production-ready foundation for differential-drive AGVs without starting from scratch. This post walks through the controller's hardware architecture, supported platforms, and the key capabilities that make it suitable for factory-floor and warehouse deployments. ## What Problem This Solves Building an AGV motion controller from discrete components — an SBC, a CAN interface card, a PLCopen runtime license, and custom I/O boards — is time-consuming and introduces integration risk at every layer. A bundled ARM + CODESYS solution collapses that stack into a single validated board, letting teams focus on application logic (path pl --- ## 【NI Locally Produced Module】PXIe‑6612, 5 V, 8-Channel PXI Counter/Timer Module - URL: https://intl.sienovo.cn/blog/142032029 - Date: 2024-09-08 - Tags: #EmbeddedHardware, #AI ## What the PXIe‑6612 Does and Why It Matters in Test Systems The NI PXIe‑6612 is a dedicated counter/timer module for the PXI Express platform, running at 5 V logic and delivering eight independent 32-bit counter/timer channels. If your test system needs precise timing measurements, encoder tracking, or deterministic pulse generation — tasks that strain a general-purpose DAQ card — the PXIe‑6612 is designed exactly for that workload. This post walks through what the module can do, how its key features interact, and where it fits in a real industrial or automated test environment. ## Core Measurement and Generation Modes The PXIe‑6612 supports seven distinct operating modes, and a single chassis can run multiple modes concurrently across its eight channels: **Encoder position measurement** — Each counter can be configured to decode quadrature (A/B/Z) or two-pulse encoder signals, tracking position and direction without processor intervention. This is the primary mode for motion fee --- ## 【NI Domestic Alternative】PXIe‑6614, 5 V, 8-Channel, Precision Reference PXI Counter/Timer Module - URL: https://intl.sienovo.cn/blog/142031954 - Date: 2024-09-08 - Tags: #AI, #EmbeddedHardware ## PXIe‑6614: High-Precision 8-Channel Counter/Timer Module and Its Domestic Alternative For test-and-measurement engineers working in automotive validation, aerospace functional test, or motion-control manufacturing, timing accuracy is not a nice-to-have — it is the measurement. A counter/timer module that drifts or jitters contaminates every downstream result: encoder position, pulse width, frequency ratio. The NI PXIe‑6614 was designed specifically to close that gap, and Shenzhen Xinmai (信迈) now provides a domestically produced alternative and customization service for organizations that require local supply-chain compliance or prefer to reduce dependence on imported instrumentation. ## What the PXIe‑6614 Does The PXIe‑6614 is an 8-channel counter/timer module housed in a PXI Express (PXIe) single-slot form factor. Its eight independent counter/timer channels can be configured independently and simultaneously for a wide range of timing tasks: - **Encoder position measurement** — --- ## 【NI Localization】PXIe‑4303 24-Bit, 32-Channel, 51.2 kS/s, ±10 V PXI Analog Input Module - URL: https://intl.sienovo.cn/blog/142027473 - Date: 2024-09-08 - Tags: #AI, #EmbeddedHardware The PXIe‑4303 is a high-resolution PXI analog input module from National Instruments designed for demanding data acquisition applications where simultaneous, multi-channel sampling at high dynamic range is essential. This post covers the module's key capabilities, architecture choices, and how Sienovo (Shenzhen Xinmai) provides localized, customized versions for industrial customers in China. ## Overview The PXIe‑4303 slots into a PXI Express chassis and serves as a filtered front-end for acquiring voltage, thermocouple, and current signals across up to 32 differential channels simultaneously. At 24-bit resolution and a maximum throughput of 51.2 kS/s per channel, it targets applications such as acoustic and vibration analysis, structural health monitoring, power quality measurement, and sensor validation — anywhere you need both high dynamic range and true simultaneity across a large channel count. ## Architecture: Per-Channel ADC Design The most significant architectural feature --- ## 【NI Domestic Alternative】NI USB-6525 16-Channel, 60 V, 8 Solid-State Relays, 8 Inputs, Channel-to-Channel Isolated Digital I/O Device - URL: https://intl.sienovo.cn/blog/142027367 - Date: 2024-09-08 - Tags: #MCU, #EmbeddedHardware ## Overview The NI USB-6525 is a bus-powered industrial USB digital I/O device designed to bring reliable automation to demanding factory-floor and test-and-measurement environments. This article walks through the device's key specifications, explains how its solid-state relay outputs and isolated digital inputs work together, and discusses what to look for when evaluating domestic alternatives — including the customization services offered by Shenzhen Xinmai (信迈). ## Device Specifications at a Glance The USB-6525 packs a useful combination of outputs and inputs into a single USB-powered package: | Parameter | Value | |---|---| | Total digital channels | 16 | | Solid-state relay (SSR) outputs | 8 | | Digital inputs | 8 | | Max switching voltage | 60 VDC / 30 Vrms | | Max switching current per channel | 500 mA | | Isolation | Channel-to-channel isolated inputs | | Bus power | USB (no external supply required) | Because the device is entirely bus-powered, it eliminates the need for --- ## 4-Channel Power Measurement Conditioner: A Domestic Alternative to NI - URL: https://intl.sienovo.cn/blog/142027216 - Date: 2024-09-08 - Tags: #AI ## The Case for a Domestic Power Measurement Signal Conditioner In industrial test and measurement environments, accurate power analysis depends on far more than a capable DAQ card. The signal conditioning layer between the physical world and the acquisition hardware is where measurement quality is often won or lost — particularly when dealing with high-voltage, high-current systems that cannot be fed directly into standard I/O modules. National Instruments (NI) has long been the default choice for this class of hardware, but rising demand for supply-chain independence and lower total system cost has pushed Chinese manufacturers to develop credible domestic alternatives. The RM-26999 from Shenzhen Xinmai (Sienovo) is one such product: a rack-mount signal conditioning unit purpose-built for multi-channel power measurement, designed to slot into NI-compatible measurement architectures without sacrificing accuracy or channel synchronization. ## What the RM-26999 Does The RM-26999 is a --- ## Domestic AI Server: Phytium + Fully Domestic PCIe 5.0 SWITCH Solution, Replacing Broadcom - URL: https://intl.sienovo.cn/blog/141927100 - Date: 2024-09-05 - Tags: #AI, #Server, #DevOps ###### This dual-socket Phytium server is a standard 2U rack-mount unit, configured with two Phytium S2500 processors (64 cores/processor, 2.1GHz). The server features 16 DDR4 memory slots, expandable to 1TB memory capacity, with a maximum memory speed of 3200MT/s, and 10 front hot-swappable drive bays. It is suitable for processing applications with high information security requirements, offering high throughput, strong single-thread capability, high integer computation performance, and high access and I/O channel bandwidth. It can meet various demands in critical information technology fields and ensure user information security. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141927100/01_9b2db0ba2ed1434494c0ccf385b122.png) ###### Features ###### Core Advantages It possesses flexible expansion capabilities, with power consumption more than 50% lower than that of ordinary x86 servers. Compatible with a full range of domestic software, it is suitable for critical bus --- ## AI Server PCIe Switch Interconnect Chip Technology: Domestic Alternatives to Broadcom Solutions - URL: https://intl.sienovo.cn/blog/141926891 - Date: 2024-09-05 - Tags: #AI, #Server, #DevOps ## AI Servers: A Deep Dive into Interconnect Chip Technology ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141926891/01_1ca6bb1a792146bca349b399af39ae82.png) Shenzhen Xinmai provides custom board card services for Zhongxingwei PCIe Switch AI server interconnect chips. As large language models and generative AI workloads demand increasingly dense GPU clusters, the silicon connecting those GPUs to each other and to the host CPU has become just as strategically important as the GPUs themselves. This article walks through the three principal interconnect layers inside a modern AI server — PCIe Switch and Retimer chips for CPU-GPU links, NVLink and NVSwitch for GPU-to-GPU fabric, and memory interface chips for CPU-DRAM bandwidth — and surveys the competitive landscape for domestic Chinese alternatives to the Broadcom-dominated status quo. According to TrendForce data, AI server shipments reached approximately 130,000 units at the time of writing, accounting for about 1% o --- ## [Domestic AI Servers] Domestic Alternative to Broadcom PCIe 5.0 Switch Application Examples, Supporting ZS Micro Customization - URL: https://intl.sienovo.cn/blog/141926697 - Date: 2024-09-05 - Tags: #Server, #DevOps Domestic Alternative to Broadcom PCIe 5.0 Switch Application Examples **一，FANOUT switch** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141926697/01_453fd44a902cea2d9653c9f08eb3aee0.webp) Fanout switch **二，Graphics Processing Unit** Graphics applications typically use x16-width links. Peer-to-peer communication is supported in switch hardware, allowing the shortest possible path between the peers. As with the fanout switch, the links can be at any supported PCle speed, for any supported width. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141926697/02_52bcbbcf3e39cddac1229356693ed096.webp) As shown in the figure above: GPU1 can communicate with GPU2 using switch Switch1. GPU1 can communicate with GPU3 using switch1 through a fabric link to switch2. Note: P2P Requires software support. **三，NvMe Hot Add and Hot Remove** This switch supports a system that can add a PCle device to an empty slot either in a server or in the host without disrupting --- ## 【Localized AI Servers】Domestic PCIe Switch, Replacing Broadcom AI Server I/O Interconnect Card Solutions, Supports Customization - URL: https://intl.sienovo.cn/blog/141926261 - Date: 2024-09-05 - Tags: #c++ ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141926261/01_757b92b5b8694a5f82dfd11b890f31e7.png) Domestic PCIe switch, replacing Broadcom AI server I/O interconnect card solutions, supports customization. The PEX8796 has a total of 96 PCIe lanes, of which x16 are fixed for upstream connection to the motherboard slot. The remaining 80 PCIe 3.0 lanes are all designed to be routed out via SFF-8654 8i interfaces. To route out all 80 PCIe lanes, the entire card's size is quite large. At 255mm, it's among the largest even when compared to dual-fan mid-range graphics cards. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141926261/02_0558aef484214c34a1c945ab068b8bb0.png) Each SFF-8654 8i interface has 8 PCIe lanes and 2 PCIe clock signals. By default, each SFF-8654 8i can connect two U.2 SSDs via an adapter cable, allowing for a maximum of 20 NVMe SSDs to be connected. ![](https://pub-048dcb96257f476697b113fcb3939cb9.r2.dev/blog/141926261/03_5db3cefba727468f --- ## [VPX Bus] DSP+FPGA General-purpose Ultra-wideband Real-time Signal Processing Platform Based on 6U VPX Bus Architecture - URL: https://intl.sienovo.cn/blog/141675329 - Date: 2024-08-29 - Tags: #SignalProcessing, #FPGADev * 6U VPX architecture, compliant with VITA 46 specification * Onboard 1 TMS320C6678 multi-core DSP processing node * Onboard 1 XCKU115 FPGA processing node * Onboard 2 FMC+ interfaces * 4 x4 high-speed GTH interconnects between backplanes, supporting RapidIO, PCI Express * High-speed RapidIO interconnect between FPGA and DSP ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141675329/01_6dac146c8da44beab610533e70138d2d.png) This high-speed signal processing platform is based on a 6U VPX bus architecture. It utilizes a Xilinx Kintex UltraScale series FPGA (XCKU115) as the main processor to perform complex data acquisition, playback, and real-time signal processing algorithms. A high-performance embedded processor ZU9EG with an ARM core is used as a co-processor to implement communication and management functions. The main processor XCKU115 on this platform is externally connected to two groups of 72-bit DDR4 SDRAMs to achieve ultra-large capacity data caching, --- ## [DSP+FPGA] High-Performance Real-time Signal Processing Platform Based on 6U VPX Bus Architecture with Two TMS320C6678 DSPs and an XC7VX690T FPGA - URL: https://intl.sienovo.cn/blog/141675289 - Date: 2024-08-29 - Tags: #SignalProcessing, #FPGADev * 6U VPX architecture, compliant with VITA 46 specification * Onboard two TMS320C6678 multi-core DSP processing nodes * Onboard one XC7VX690T FPGA processing node * Onboard two FMC interfaces * Backplane features four x4 high-speed GTH interconnects, supporting RapidIO and PCI Express * High-speed RapidIO interconnect between FPGA and DSP ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141675289/01_15e87e081e95481b94e7924ac29a321b.png) This high-performance real-time signal processing platform is based on a 6U VPX architecture. It utilizes two TI KeyStone series multi-core DSPs, TMS320C6678, as the main processing units, and one Xilinx Virtex-7 series FPGA, XC7VX690T, as the co-processing unit. The platform features two FMC mezzanine card interfaces, and all processing nodes are interconnected via high-speed serial buses. The board adopts a standard 6U VPX Eurocard design, boasting excellent anti-vibration design, heat dissipation performance, and unique env --- ## Rack-mount 4U Height 6U 6-Slot VPX System Platform - URL: https://intl.sienovo.cn/blog/141675249 - Date: 2024-08-29 - Tags: #Networking * Standard 4U height VPX system platform, supporting rack-mount and desktop applications * Compliant with OpenVPX/VPX standards, conforming to VITA46/VITA65 specifications * 6-slot 6U VPX backplane, 5HP slot spacing * Supports standard 6U VPX plug-in power supplies or power modules * High-strength aluminum-magnesium alloy * Supports horizontal 6U plug-in cards, supports rear I/O ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141675249/01_74238bdb310a4077bff7f8c2e0ff6c14.png) A high-performance, high-reliability application system platform based on the 6U VPX bus architecture, supporting VPX and OpenVPX protocol standards. This system platform utilizes a high-performance 6-slot 6U VPX backplane with a highly optimized topology, providing users with various high-speed serial bus interconnections. The platform supports standard VPX plug-in power supplies and high-power module power supplies, offering maximum design support for VPX system power. It supports rea --- ## 【PXIe Bus Board】K7 FPGA Data Acquisition Card Based on Standard 3U PXIe Bus Architecture - URL: https://intl.sienovo.cn/blog/141675039 - Date: 2024-08-29 - Tags: #FPGADev A high-performance data pre-processing FMC carrier board based on the PXI Express bus architecture. The board features one FMC (HPC) interface and one x8 PCIe host interface. It utilizes Xilinx's high-performance Kintex-7 series FPGA as the real-time processor to achieve data acquisition and processing from the FMC interface, as well as conversion for the PCI Express bus interface. It includes one independent 64-bit DDR3 SDRAM large-capacity cache on board. By integrating various FMC daughter cards, this board can quickly establish a verification platform based on the PXI Express instrument bus. This board is a standard 3U PXI Express size, suitable for standard Eurocard PXIe chassis, and can be widely applied in scenarios such as radar and IF signal acquisition, and video image acquisition. Standard 3U PXIe Specifications * 1 FMC (HPC) interface, compliant with VITA57 specification * Onboard 1 XC7K325T FPGA processor * Supports x8 PCIe host interface, system bandwidth 4 GByte --- ## 4-Channel FMC Interface Baseband Signal Processing Platform Based on Virtex UltraScale+ VU13P FPGA - URL: https://intl.sienovo.cn/blog/141674721 - Date: 2024-08-29 - Tags: #FPGADev, #SignalProcessing * Virtex UltraScale+ Series FPGA Processor: XCVU13P-2FHGB2104I * Number of Dynamic Memory Modules: 2 groups of DDR4 SDRAM * Dynamic Memory Capacity: 4 GBytes per group, 8 Gbits per chip * Dynamic Memory Bandwidth: Operating clock 1000MHz, data rate 2000Mbps * Onboard 6-channel QSFP+ optical interfaces * Onboard 4 FMC+ high-speed expansion interfaces ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141674721/01_ffcbb90e1b3b4f248a63d59de1b969be.png) This high-performance 4-channel FMC interface baseband signal processing platform, based on the Virtex UltraScale+ series FPGA, utilizes one Xilinx Virtex UltraScale+ series FPGA, the XCVU13P, as the real-time signal processing unit. The board features four FMC daughter card interfaces (two of which are FMC+ interfaces). Nodes are interconnected via high-speed serial buses. This FPGA supports high-speed serial buses up to 32 Gbps, suitable for 100G Ethernet, JESD204B/JESD204C, and other high-speed interfaces. The bo --- ## [DSP+FPGA] High-Performance Real-time Signal Processing Platform Based on Virtex-7 FPGA + C6678 DSP - URL: https://intl.sienovo.cn/blog/141674579 - Date: 2024-08-29 - Tags: #FPGADev, #SignalProcessing * DSP + FPGA Co-processing Architecture * Onboard one TMS320C6678 multi-core DSP processing node * Onboard one XC7VX690T FPGA processing node * Onboard one FMC interface * Onboard four SFP+ fiber optic interfaces * High-speed RapidIO interconnect between FPGA and DSP ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141674579/01_db66b3d1befa44ae94ed258dd1879166.png) This high-performance real-time signal processing platform based on Virtex-7 FPGA utilizes one TI KeyStone series multi-core DSP TMS320C6678 as the main processing unit and one Xilinx Virtex-7 series FPGA XC7VX690T as the co-processing unit. It features two FMC daughter card interfaces, with processing nodes interconnected via high-speed serial buses. The board supports four SFP+ 10 Gigabit fiber optic interfaces and two RJ45 Gigabit Ethernet ports, making it suitable for high-speed real-time signal processing. #### Functional Block Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/ --- ## FMC Interface 10 Gigabit Fiber Optic Network Validation Platform Based on XC7K325T FPGA - URL: https://intl.sienovo.cn/blog/141674484 - Date: 2024-08-29 - Tags: #FPGADev * Onboard FPGA Real-time Processor: XC7K325T-2FFG900I (compatible with XC7K410T) * Standard FMC (HPC) interface, compliant with VITA57.1 specification * 4-channel 10G SFP+ fiber optic interfaces, supporting single-mode/multi-mode fiber, and RapidIO, Aurora protocols * Compliant with SATA 3.0 standard, supporting 6Gbps/lane line rate * Supports 1 USB3.0 interface * 1 high-precision clock unit (AD9516-1 clock generator) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141674484/01_8252ea79add847cb93ed6309c8c586a3.png) The 10 Gigabit fiber optic network validation platform based on XC7K325T FPGA features one FMC (HPC) interface, four 10 Gigabit SFP+ fiber optic interfaces, four SATA interfaces, and one USB3.0 interface. The onboard high-performance FPGA processor can implement fiber optic protocols, SATA bus controllers, and data transmission for the USB3.0 high-speed serial bus, providing high-bandwidth, low-latency data links. By integrating different FMC daug --- ## [DSP+FPGA] Universal Signal Processing Platform Based on DSP+FPGA XC7K325T and TMS320C6678 - URL: https://intl.sienovo.cn/blog/141674150 - Date: 2024-08-29 - Tags: #SignalProcessing, #FPGADev * DSP + FPGA Collaborative Processing Architecture * Onboard 1 TMS320C6678 Multi-core DSP Processing Node * Onboard 1 XC7K325T FPGA Processing Node * Onboard 1 FMC Interface * Onboard 4 SFP+ Optical Fiber Interfaces * High-speed RapidIO Interconnect between FPGA and DSP ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141674150/01_53262e6dacf842a8985bd21759c0be9d.png) A general-purpose high-performance real-time signal processing platform based on an FPGA and DSP collaborative processing architecture. This platform uses one TI KeyStone series multi-core floating-point/fixed-point DSP TMS320C6678 as the main processing unit, and one Xilinx Kintex-7 series FPGA XC7K325T as the co-processing unit. It features one FMC daughter card interface and four SFP+ 10 Gigabit optical fiber interfaces. Processing nodes are interconnected via high-speed serial buses. By pairing with different FMC daughter cards, this system can be widely applied in scenarios such as software --- ## ZYNQ SOC-Based Software Defined Radio Processing Platform - URL: https://intl.sienovo.cn/blog/141635981 - Date: 2024-08-28 - Tags: #ZYNQ, #SDR * Onboard SOC Real-time Processor: XC7Z020-2CLG484I * Onboard 2x AD9361 RF Transceiver Chips, compatible with AD80305 * Features 1x Gigabit Ethernet Port * Features 1x USB Serial Port, 1x USB OTG, 1x SD Card * ADC/DAC Sampling Bit Width: 12-bit * 2x TX, 2x RX, supporting full-duplex or half-duplex operation ![](https://pub-048dcb96257f476697b113fcb5939cb39cb9.r2.dev/blog/141635981/01_7e040509003d46f3b537f4eb938807f6.png) This Software Defined Radio (SDR) processing platform, based on Xilinx ZYNQ SOC, utilizes a high-performance Xilinx ZYNQ series SOC (XC7Z020) to achieve 2-channel AD9361 wireless RF signal transmission and reception. It is widely applicable to applications such as SDR, mobile base stations, Wi-Fi, wireless local area networks, and specialized or general-purpose wireless devices. The ZYNQ7000 is an extensible processing platform launched by Xilinx. The ZYNQ SOC integrates a dual-core ARM Cortex-A9 processor, perfectly coupling the programmability of the F --- ## FPGA+DSP Architecture-Based IF Signal Acquisition, Processing, and Remote Fiber Optic Transmission System - URL: https://intl.sienovo.cn/blog/141635873 - Date: 2024-08-28 - Tags: #FPGADev, #Networking * Supports 8-channel, 250 MSPS sampling rate, 16-bit analog signal input * Supports 4 SFP+ fiber optic channels, up to 10 Gbps/lane * Onboard 1 XC7K325T FPGA processor * Onboard 1 TMS320C6678 multi-core processor * Supports 2 Gigabit Ethernet ports * Supports multi-system cascading and synchronous acquisition ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141635873/01_5ea7e16ae68141218d27213050d4c798.png) #### Functional Block Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141635873/02_fededadf6f4660e753bcc90c4da9d2df.png) This high-performance radar signal real-time acquisition and processing platform, based on fiber optic transmission, integrates an I/O unit, a signal processing unit, and a remote transmission unit. It enables real-time acquisition, real-time processing, high-speed transmission, and high-speed storage of radar signals. The system platform consists of one signal processing platform card and one 4-channel fiber optic --- ## 4-Channel 250 MSPS IF Signal Acquisition, Processing, and Storage System Based on 3U PXIe Bus Architecture - URL: https://intl.sienovo.cn/blog/141635766 - Date: 2024-08-28 - Tags: #Architecture, #IFDAQ * Standard 3U PXIe Specification * 1 FMC AD Daughter Card, supporting 4-channel 250 MSPS 16-bit AD acquisition * Onboard 1 XC7K325T FPGA Processor * Supports x8 PCIe Host Interface, System Bandwidth 4 GByte/s * Supports Inter-board Synchronization * Supports Multi-system Synchronization ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141635766/01_250822492ed845c3b0591317828ee382.png) An Intermediate Frequency (IF) signal acquisition, processing, and storage system based on the PXI Express bus architecture. The system consists of one PXIe-compliant FMC carrier board and one FMC AD daughter card. The system features an x8 PCIe host interface, and the system board utilizes a high-performance Xilinx Kintex-7 series FPGA as the real-time processor, enabling the acquisition and processing of FMC interface data, as well as conversion to the PCI Express bus interface. It includes one independent 64-bit DDR3 SDRAM large-capacity cache onboard. This board is a standar --- ## Ruggedized High-Performance Data Acquisition and Motion Control System Based on ZYNQ FPGA + DSP C6678 - URL: https://intl.sienovo.cn/blog/141608661 - Date: 2024-08-27 - Tags: #FPGADev This ruggedized high-performance motion controller, built on an FPGA+DSP real-time control system architecture, supports multi-channel parallel synchronous real-time high-speed sampling. Data is directly passed point-by-point to the DSP for algorithm processing at the low level to ensure real-time performance. It can achieve high-speed point-by-point control output, ensuring the control system can excellently fulfill highly demanding real-time control tasks in scenarios involving multi-input, multi-output high-speed control. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141608661/01_d2a84b25ba0b8db57e65a64762b9bc66.jpeg) **Product Features** **Accurate Measurement** Extremely strong anti-interference capability ensures precise measurement of the controlled object's output signals. **Superior Computing Power** The core processor utilizes an 8-core high-performance DSP, possessing superior computational processing power. **Fast Control Response** High-speed proc --- ## 【NI Domestic Alternative】24-bit, 8-Channel PXI Strain/Bridge Input Module (Domestic Alternative to PXIe-4330) - URL: https://intl.sienovo.cn/blog/141399982 - Date: 2024-08-21 - Tags: #PXIe‑4330, #NIAlternative ## Overview For test engineers building high-density structural, mechanical, or materials measurement systems, the NI PXIe-4330 has long been the reference-standard module for bridge-based sensor acquisition. This post covers the module's architecture and specifications in detail, and introduces why domestic Chinese alternatives to the PXIe-4330 are now a practical consideration for labs and production lines operating under supply-chain or budget constraints. ## What Is the PXIe-4330? The PXIe-4330 is a synchronous, 24-bit, 8-channel PXI Express strain and bridge input module from National Instruments. It integrates signal conditioning and data acquisition into a single PXI slot, accepting signals directly from Wheatstone bridge-based sensors — strain gauges, load cells, torque transducers, and pressure sensors — without requiring a separate signal conditioning chassis. The module's defining characteristic is that all eight channels sample simultaneously and synchronously. In multi --- ## 【NI Domestic Alternative】PXIe‑4331 Domestic Replacement 24-bit, 8-Channel PXI Strain/Bridge Input Module - URL: https://intl.sienovo.cn/blog/141398863 - Date: 2024-08-21 - Tags: #NIAlternative ## Replacing the NI PXIe-4331 with a Domestic Alternative: 24-bit, 8-Channel PXI Strain/Bridge Input For test engineers running high-density structural, load, or pressure measurement systems inside PXI chassis, the NI PXIe-4331 has long been the reference-class strain/bridge input module. It packs 8 channels of 24-bit simultaneous acquisition, integrated signal conditioning, and per-channel excitation into a single PXIe slot — a combination that is hard to replicate. With growing interest in domestically sourced alternatives across China's industrial and aerospace sectors, understanding exactly what the PXIe-4331 delivers is the right starting point before evaluating any replacement. ## What the PXIe-4331 Actually Does The PXIe-4331 is not a generic analog input card. It is purpose-built for Wheatstone bridge transducers: strain gauges, load cells, torque sensors, and pressure bridges. The distinction matters because a raw ADC cannot drive a bridge, balance it, or compensate for lea --- ## 【NI Domestic Alternative】NI‑9235 Quarter-Bridge Strain Gage, 8-Channel C Series Strain/Bridge Input Module - URL: https://intl.sienovo.cn/blog/141398786 - Date: 2024-08-21 - Tags: #NIAlternative ## NI 9235: A Domestic Alternative for High-Speed Synchronous Strain Measurements The NI 9235 is an 8-channel C Series strain/bridge input module that enables high-speed synchronous measurements of dynamic strain on all channels. This feature is particularly crucial for applications that require comparing multiple channels at a specific moment, such as impact testing. In this article, we will explore the key features and technical specifications of the NI 9235, as well as its potential applications and advantages. ## Key Features and Technical Specifications The NI 9235 features built-in voltage excitation for quarter-bridge sensors, making it a convenient and efficient solution for strain measurement applications. Additionally, it provides 60 VDC isolation and 1,000 Vrms transient isolation, which enhances safety and provides high common-mode noise rejection. The module's technical specifications include: ### Bridge Configuration * 1/4 Bridge ### Analog Input Channels * Maximum --- ## 【NI Domestic Alternative】NI-9236 Quarter-Bridge Strain Gauge, 8-Channel C Series Strain/Bridge Input Module - URL: https://intl.sienovo.cn/blog/141398716 - Date: 2024-08-21 - Tags: #NIAlternative ## Overview: What the NI-9236 Does and Why It Matters The NI-9236 is an 8-channel C Series strain/bridge input module designed specifically for quarter-bridge strain gauge measurements at up to 10 kS/s per channel. Engineers working in structural testing, vibration analysis, impact testing, and industrial load monitoring rely on modules like this to acquire dynamic strain data from multiple sensors simultaneously. This post covers the NI-9236's key technical characteristics — synchronization, isolation architecture, bridge excitation, and form factor — and explains why these specs matter when evaluating domestic alternatives for NI C Series hardware. ## Quarter-Bridge Configuration and What It Means for Wiring A quarter-bridge circuit uses a single active strain gauge element as one leg of a Wheatstone bridge, with the remaining three legs completed by precision resistors inside the module itself. The NI-9236 specifies a 350 Ω bridge resistance, which matches the most common industr --- ## [Domestic Alternative to NI] Full Domestic Alternative to NI-9218, 2-Channel C-Series Universal Analog Input Module - URL: https://intl.sienovo.cn/blog/141398559 - Date: 2024-08-21 - Tags: #ni, #ni-9218 ## Domestic Alternative to NI: Full Domestic Alternative to NI-9218, 2-Channel C-Series Universal Analog Input Module The NI-9218 is a widely used analog input module from National Instruments, designed for versatile measurements in various applications such as automotive, off-highway, and data logging. However, for users who prefer domestic alternatives, there are options available that can provide similar functionality. In this article, we will explore a domestic alternative to the NI-9218, a 2-channel C-series universal analog input module. This module is designed to provide built-in support for various types of measurements, including accelerometers, powered sensors, full-bridge and voltage measurements, as well as quarter-bridge, half-bridge, 60V, and current measurements. ## Key Features of the Domestic Alternative The domestic alternative to the NI-9218 has the following key features: ### Maximum Number of Differential Analog Input Channels The module has a maximum of 2 di --- ## [ARM+Codesys Customer Case Study] Application Case in Smart Manufacturing Based on RK3568/A40i/STM32+CODESYS: Hydraulic Power Unit - URL: https://intl.sienovo.cn/blog/141283420 - Date: 2024-08-17 - Tags: #Manufacturing, #ARMDev, #stm32, #Automation, #codesys, #EmbeddedHardware Poppe + Potthoff is a group company specializing in technology R&D and product manufacturing in the high-pressure sector. The company develops and manufactures advanced technical products for the automotive industry, special vehicle industry, marine industry, and more. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141283420/01_e5765985d408f5cf43ceae1096d57a52.jpeg) Xinmai provides localized ARM+Codesys customization. At its Nordhausen plant, Poppe + Potthoff develops test systems for burst testing, autofrettage, pulsation testing, and rotary bending fatigue experiments. These systems require flexible test programs, not only needing to perform tests under linear and constant pressure but also capable of burst pressure testing under linear gas flow. Due to the unique characteristics of the test objects and pipelines, the design of this test system presented special requirements. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141283420/02_da7761f583f6 --- ## 【ARM+CODESYS Customer Case Study】Application of RK3568/A40i/STM32 + CODESYS in Smart Manufacturing: Fully Automatic Slicing Robot - URL: https://intl.sienovo.cn/blog/141283373 - Date: 2024-08-17 - Tags: #stm32, #Manufacturing, #Robotics, #codesys, #Automation, #ARMDev Vegetables are an indispensable part of people's daily diet and can be prepared in various ways. Since entering a moderately prosperous society, people's pace of life has accelerated, and many traditional services can no longer meet their material needs and lifestyle demands. In daily life, fast manual vegetable cutting poses a serious threat to personal safety. Factors such as prolonged cutting time or lack of skill can easily lead to injuries. In places with high demand for vegetable processing, such as canteens and food processing plants, there is a need to process vegetables into various shapes both safely and quickly. Relying solely on manual labor is both time-consuming and laborious. How to cut vegetables faster has become a challenging problem. Using food processors to replace or supplement manual labor will increase the efficiency of vegetable cutting. Therefore, research into vegetable cutting robots is highly necessary. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2 --- ## [ARM+Codesys Customer Case Study] Application Cases of RK3568/A40i/STM32+CODESYS in Smart Production Lines: A Brief Discussion on the Packaging Industry — Adaptive Smart Equipment - URL: https://intl.sienovo.cn/blog/141283154 - Date: 2024-08-17 - Tags: #Middleware, #Networking, #stm32, #Automation, #codesys, #ARMDev ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141283154/01_efbb3e8112dec3452895606ee83f4e2a.jpeg) Consumer goods manufacturers prefer packaging equipment that combines productivity and cost-effectiveness. The characteristic of future high-end smart equipment is high "usability." What exactly is "usability"? Firstly, it requires minimal operators and energy consumption, and secondly, high material utilization. A modern factory must possess sufficient adaptability to meet any demands of the production process. For equipment manufacturers, this means they must always be ready to provide customers with required modular functional extensions and integrate them into existing manufacturing equipment. PC-based soft control technology and decentralized drive technology help meet these machine equipment requirements, as the software already includes expandable functions and can be connected via simple, standardized interfaces. To enable the system to adapt to new product types --- ## [ARM+Codesys Customer Case Study] Application Case based on RK3568/A40i/STM32+CODESYS in Smart Production Lines: Fully Automatic Assembly of LeanMotor Rotors using Robots - URL: https://intl.sienovo.cn/blog/141283124 - Date: 2024-08-17 - Tags: #ARMDev, #Robotics, #Automation, #codesys, #stm32 In Europe, especially Germany, the assembly of workpieces using fully automatic robots has long been nothing new. For example, the encoderless LeanMotor manufactured by STOBER in Pforzheim (a German city) holds the top position in the global market. It uses a fully automatic robotic component installation system to produce rotors for this highly efficient drive solution. The system is fully automated, based on the latest internally developed technology and **CODESYS** control solutions from Germany as core support. Coupled with its extensive product portfolio, STOBER can realize a wide variety of applications. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141283124/01_2874fa1a4b00d69fc5f13b75e9d64f5c.jpeg) Encoderless drives provide consistent output, are lighter than asynchronous drives, and their motors are smaller, more cost-effective, and more robust than servo motors. With full torque control, speed and torque can be controlled arbitrarily, achieving an efficie --- ## 【ARM+Codesys Customer Case Study】 Application of RK3568/A40i/STM32+CODESYS in Smart Production Lines: Professional Packaging System Solutions - URL: https://intl.sienovo.cn/blog/141283085 - Date: 2024-08-17 - Tags: #codesys, #ARMDev, #Automation, #stm32 **Background Introduction** Due to the diverse shapes and sizes of product packaging, the demand for packaging machines today is equally varied. While packaging primarily serves to protect its contents, product presentation often boosts purchasing desire, necessitating continuous adjustments to meet point-of-sale requirements. Even with frequently changing packaging tasks, operators expect their packaging machines to be reliable, offer high cycle speeds, and, most importantly, be flexible. Today's machines are highly automated, thus requiring intelligent, modular safety solutions that maintain economic viability and provide a competitive edge. To address this, the German company CODESYS has developed a new intelligent control solution. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141283085/01_0af623e8bbfb79f6a25701141be0ea97.jpeg) **Oystar Packaging Group** Founded in 1893 and located in Stutensee near Karlsruhe, the Oystar Packaging Group is a world-leading supp --- ## 【ARM+Codesys Customer Case Study】Application of RK3568/A40i/STM32 + CODESYS in Factory Automation: Eaton Moeller Modular Controller XC200 - URL: https://intl.sienovo.cn/blog/141283049 - Date: 2024-08-17 - Tags: #ARMDev, #stm32, #Automation, #codesys, #EmbeddedHardware German company Sigloch Maschinenbau provides customized production lines for the entire process of binding brochures and books, including collators, adhesive binders, end sheet machines, staplers, backing machines, drying conveyors, and ribbon feeders. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141283049/01_804ad149d037c1374a3abda039c70bc1.jpeg) All equipment in the entire automated production line is controlled by the XC200 modular controller from Eaton Moeller (USA). This PLC is developed based on the German **CODESYS** industrial software platform. The Moeller XC200 controller can communicate with multiple XI/ON remote I/O devices. At the communication level, the CANopen bus handles communication between field modules, and smart drives are also connected via CANopen. Furthermore, communication between the PLC and operator units, as well as communication between machine units, is realized via Ethernet. Finally, for the operator interface, Moeller XVH300 and XV4 --- ## 【ARM+Codesys Customer Case Study】 Application of RK3568/A40i/STM32 + CODESYS in Factory Automation: Eaton Rapid Link System - URL: https://intl.sienovo.cn/blog/141283016 - Date: 2024-08-17 - Tags: #stm32, #Automation, #EmbeddedHardware, #codesys, #ARMDev The world's most advanced material handling systems today are configured using modular and decentralized systems. For example, internationally renowned warehousing system suppliers have already used the Rapid Link system in multiple projects. This system, developed in collaboration with German industrial software company **CODESYS**, can guarantee the system's safety, stability, flexibility, reliability, and speed to the greatest extent. At the same time, system manufacturers and operators are continuously ensuring its outstanding advantages in planning and installation. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141283016/01_0685681469c70c35508f696c5b395d50.png) ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141283016/02_e6408e69a762885620741ad32efae479.jpeg) This case study focuses on the baggage handling system at Europe's largest airport. As one of the international transport hubs, the airport handles over 65 million passengers annually, and --- ## 【ARM+Codesys Customer Case Study】 Application of RK3568/A40i/STM32+CODESYS in Factory Automation: Riveting Machine - URL: https://intl.sienovo.cn/blog/141282980 - Date: 2024-08-17 - Tags: #stm32, #Automation, #EmbeddedHardware, #codesys, #ARMDev Application: Riveting Machine: Process control for riveting machines in joining, pressing, and welding processes. Berghof supplies Werner Krayer GmbH in Germany with an HMI-integrated controller for riveting machines, which features powerful I/O expansion capabilities. Using this controller can significantly reduce the error rate or defect rate during the riveting process. Its compact size reduces space requirements in the machine and control cabinet. Berghof provides Werner Krayer GmbH with the DC1000 controller, featuring a display and I/O expansion capabilities. Based on this, Krayer GmbH can also develop its own process control program "proMY," which allows the factory to not only perfectly monitor the riveting process but also to 100% control quality through adjustable parameters. This process controller is specifically designed for a wide range of applications in the fields of joining, pressing, and welding. The highlight of this riveting machine is its process control, which --- ## [ARM+Codesys Customer Case Study] Application of RK3568/A40i/STM32+CODESYS in Factory Automation: PCB Soldering Machine - URL: https://intl.sienovo.cn/blog/141282920 - Date: 2024-08-17 - Tags: #ARMDev, #Automation, #Networking, #codesys In modern manufacturing, electronic components are typically produced using automated equipment, such as in the assembly of PCBs (Printed Circuit Boards). However, production processes also face challenges, for instance, how to securely and precisely mount various components onto a PCB? IBL Löttechnik GmbH's CM800 soldering machine (also known as the "vapor hammer") provides a complete solution for this, with its control unit featuring Berghof's DC1012TT large-format, high-resolution, high-precision color display and control integrated controller. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141282920/01_ba5f0062d2d8bbe8c516b16edf2a3e22.jpeg) To accurately display all operating statuses, the IBL "vapor hammer" is equipped with the Berghof DC1012TT controller (this large-format, touch-enabled, high-precision color display and control integrated controller is developed based on the German CODESYS industrial software programming platform). A core advantage IBL has in --- ## 【ARM+Codesys Customer Case】Electroplating Production Line Solution - URL: https://intl.sienovo.cn/blog/141282870 - Date: 2024-08-17 - Tags: #codesys **1 Introduction to Electroplating Production** Electroplating is a crucial process. Products treated with electroplating not only achieve improved quality but also significantly enhanced performance, while extending their service life. An electroplating production line refers to a complete system that integrates various related components according to specific electroplating process requirements. These components include electroplating treatment tanks, electroplating hoist movement devices, power supply equipment, circulation and filtration units, testing instruments, heating devices, air agitation devices, drainage systems, and pollution treatment units, all coordinated and controlled by an electrical control system. Automatic electroplating production lines reduce material consumption, lessen human labor intensity, minimize human contact with chemical pollutants, and simultaneously improve production efficiency and quality. They also facilitate the digital and centralized manageme --- ## 【ARM+Codesys Case Study】Application of Controllers Developed Based on RK3568/A40i/STM32+CODESYS in Automatic Conveying and Sorting Systems, Customizable - URL: https://intl.sienovo.cn/blog/141282805 - Date: 2024-08-17 - Tags: #ARMDev, #codesys In 2021, JD.com's "618" cumulative order value exceeded 343.8 billion yuan, setting a new record! From placing an order to receiving goods, various items can be delivered to any household nationwide within just a few days through an extensive logistics network. The rapid development of e-commerce and express logistics has placed higher demands on warehousing, sorting, and distribution efficiency and accuracy, accelerating the development of smart logistics. Smart logistics is an important component of Industry 4.0. Industrial production logistics systems, commercial distribution logistics systems, and the smart logistics equipment industry chain constitute the three major elements of smart logistics equipment, with automation being its foundation. Against the backdrop of the new economic normal and industrial upgrading, as labor, land, and warehousing rental costs continue to rise, the emergence of smart logistics equipment is an inevitable trend, with the overall market size expecte --- ## [ARM+Codesys Customer Case Study] Developing AGV Motion Controllers based on RK3568/A40i/STM32+CODESYS, Supporting Domestic Customization - URL: https://intl.sienovo.cn/blog/141282734 - Date: 2024-08-17 - Tags: #ARMDev ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141282734/01_2f86789d80f99e49f1b9bc75ac6d506d.png) In the past, Kinco primarily provided AGV customers with single, high-performance low-voltage servo core components. Now, Kinco has developed a specialized controller for AGV robots, the "Azure Dragon No. 1", based on **CODESYS**. It now offers AGV bus control system solutions centered around Kinco's AGV motion controller FD1X4S series, Green series low-voltage servos, HMIs, and other core components. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141282734/02_329bb84e9c0c13f3bbbbd4ae5ffe14cb.jpeg) The "Azure Dragon No. 1" controller uses an ARM Cortex A9 667MHz processor. It supports 2 CAN bus master ports and 2 Ethernet ports; 4 RS485 ports and 1 RS232 port. It integrates 24 digital input channels and 16 digital output channels. It has a built-in reserved slot for an expandable Wi-Fi communication module. It integrates basic function libraries for AGV --- ## TI AM64x + FPGA Solution for PLCs, Motor Drives, Industrial Robots, Supports Customization - URL: https://intl.sienovo.cn/blog/141264131 - Date: 2024-08-16 - Tags: #FPGADev, #Robotics Texas Instruments' (TI) AM64x is a 64-bit Arm series processor designed with safety features, suitable for Programmable Logic Controllers (PLCs), motor drives, remote I/O, and industrial robots. The high-end processor in this series, the AM6442, features seven cores, including two Cortex-A53 application cores, four Cortex-R5F real-time cores, and one Cortex-M4F independent core. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141264131/01_507feb8ae6c54a15b096679a1c9053af.png) To my knowledge, the documentation for this processor first appeared in January 2021. Subsequently, TI also announced the processor in a blog post in February, though its title was somewhat vague. It wasn't until early May that it was first featured by **Embedded Computing**, the world's largest electronic engineering community. In addition to the processor itself, TI also offers an AM64x Starter Kit and a full-featured AM64x Evaluation Kit. Furthermore, several companies are now preparing developm --- ## RK3568 vs Raspberry Pi 4 + CODESYS Solution Comparison - URL: https://intl.sienovo.cn/blog/141247097 - Date: 2024-08-16 - Tags: #codesys, #RK3568 #### ▎Introduction The embedded computing field has always been intensely competitive, with the RK3568 and Raspberry Pi 4 standing out as two highly anticipated platforms that have garnered widespread attention. This article will provide a comprehensive comparison of the RK3568 and Raspberry Pi 4, covering aspects such as processor performance, expandability, power consumption, and software support, to help readers better understand the advantages and suitable application scenarios of these two platforms. #### ▎RK3568 After years of development, Rockchip has built a rich product line in general-purpose processors, machine vision, and other fields, capable of meeting the industry demands of various scenarios. At its 2020 Developer Conference, Rockchip unveiled the RK3568 chip. This chip features a 22nm process technology, a quad-core A55 architecture CPU (up to 2.0GHz), a Mali G52 2EE graphics processor (800MHz), a built-in NPU providing 1 TOPS of computing power, and support for va --- ## IoT HMI/Gateway Featuring ARM+CODESYS for Integrated SoftPLC+HMI - URL: https://intl.sienovo.cn/blog/141165299 - Date: 2024-08-13 - Tags: #IoT, #codesys IoT HMI/Gateway with CODESYS for Integrated SoftPLC+HMI 1. Hardware: ARM platform, supporting STM32, Allwinner T3, RK3568, Raspberry Pi, and other platforms. 2. Software: CODESYS V3.5, JMobile Studio CODESYS is a powerful PLC software programming tool that supports the six IEC 61131-3 standard PLC programming languages: IL, ST, FBD, LD, CFC, and SFC. Users can select different languages to edit subroutines, function blocks, and more within the same project. By porting the Runtime to a hardware platform, any embedded device or PC-based device can be transformed into an IEC 61131-3 compliant industrial controller. Consequently, more and more engineers are favoring CODESYS applications. The IoT HMI/Gateway is a high-performance data acquisition and monitoring device that supports **200+ communication protocols**, including common **OPC UA**, **Modbus TCP**, and **MQTT** protocols, as well as major PLC protocols from **Siemens**, **Mitsubishi**, **Omron**, and others. It su --- ## NXP IMX8M + FPGA-based In Vitro Diagnostic POCT Device - URL: https://intl.sienovo.cn/blog/141155207 - Date: 2024-08-13 - Tags: #AI, #IMX8P, #ARMDev, #FPGADev In Vitro Diagnostic POCT Devices With an aging population and increasing emphasis on health, POCT (Point-of-Care Testing), a sub-segment of IVD (In Vitro Diagnostics), continues to grow in market size. POCT (point-of-care testing) refers to clinical tests and bedside testing performed near the patient. It is a testing method that uses portable analytical instruments and corresponding reagents to quickly obtain test results. Common POCT devices include biochemical analyzers, immunoassay analyzers, PCR instruments, etc., employing various technologies such as dry chemistry, immunoassay, chemiluminescence, biosensors, biochips, and microfluidics. They are applied in fields such as cardiac markers, blood glucose, blood gas, electrolytes, coagulation, infectious diseases, pregnancy, drug testing, drunk driving detection, food safety, and tumor marker detection. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141155207/01_4c48858c5a996b09711aca68dce66256.jpeg) **POCT Advanta --- ## Based on NXP IMX6U + FPGA: An Analysis of the Mainboard Solution for IVD In Vitro Diagnostic Devices - URL: https://intl.sienovo.cn/blog/141130021 - Date: 2024-08-12 - Tags: #IMX6ULL, #FPGA, #ARMDev ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141130021/01_ad856d58fd164c89b73dc0809a8b34ac.png) I. Medical Diagnostic Devices With the increasing abundance of biochemical reagents, immunodiagnostic reagents, and molecular diagnostic reagents, domestic medical diagnostic devices have seen significant market demand. The technological development of diagnostic devices has evolved from microcontroller-based processing to Cortex-A53 processing, with a gradual increase in parallel processing channels, leading to a noticeable improvement in both detection speed and efficiency. II. Immunodiagnostics: The Most Diverse Category Immunodiagnostic reagents constitute the largest category among all diagnostic reagents. They can be categorized by application into infectious diseases, endocrinology, oncology, drug monitoring, and blood typing. They can also be classified by method, such as chemiluminescence, colloidal gold, EIA, and so on. Its general block diagram is as follows: --- ## NXP i.MX6 + FPGA-based POCT Fluorescence Immunoassay Analyzer Solution - URL: https://intl.sienovo.cn/blog/141129867 - Date: 2024-08-12 - Tags: #ARMDev, #fpga Point-of-care testing (POCT) demands compact, reliable, and cost-effective embedded platforms that can handle real-time signal acquisition, motor control, and a responsive user interface simultaneously. This post covers how NXP i.MX6 series processors, combined with FPGA-assisted signal processing, serve as the hardware backbone for a multi-model fluorescence immunoassay analyzer — and how a unified Linux/Android software stack makes it practical to ship several product tiers from a single codebase. ## What Is a Fluorescence Immunoassay Analyzer? Fluorescence immunoassay analyzers detect target biomarkers (cardiac markers, hormones, infectious disease antigens, etc.) by illuminating a test strip with a specific wavelength of light and measuring the resulting fluorescent emission. The intensity of that emission correlates to analyte concentration. Because the optical signal is weak and time-sensitive, the embedded platform must coordinate precise motor timing, analog front-end control --- ## NXP IMX6Q + FPGA-Based Fully Automatic Blood Analyzer Solution - URL: https://intl.sienovo.cn/blog/141129734 - Date: 2024-08-12 - Tags: #ARMDev, #FPGADev, #imx6ul Fully automatic blood cell analyzers — known clinically as complete blood count (CBC) analyzers, hemocytometers, or blood cell counters — are among the most widely deployed instruments in clinical laboratories worldwide. They automate the detection and classification of red blood cells, white blood cells, and platelets within a defined volume of whole blood, replacing the laborious and error-prone manual differential count. Embedding this capability into a compact, cost-effective embedded platform is a recurring design challenge: the system must drive precision analog front-ends, communicate with FPGA-based signal processing logic, render a clinician-friendly GUI, and meet strict medical reliability standards — all simultaneously. This post outlines a solution architecture that tackles exactly that combination using the NXP i.MX6Q application processor paired with an FPGA co-processor. ## Why i.MX6Q for Medical Instrumentation The NXP i.MX6Q (Quad) is a member of NXP's i.MX6 Cortex-A --- ## Solution for Fully Automatic Chemiluminescence Immunoassay Analyzer Based on NXP IMX8P, FPGA, and AI - URL: https://intl.sienovo.cn/blog/141129635 - Date: 2024-08-12 - Tags: #IMX8, #FPGADev Fully automatic chemiluminescence immunoassay (CLIA) analyzers sit at the intersection of precision fluidics, high-speed signal processing, and real-time embedded computing. This post walks through a hardware platform solution for such an analyzer, built around the NXP i.MX 8M Plus (IMX8P) application processor, an FPGA co-processor, and an on-device AI inference engine — a combination that addresses the demanding mix of real-time motion control, photon-counting signal acquisition, image processing, and clinical reporting that modern CLIA instruments require. ## What a Fully Automatic CLIA Analyzer Does A chemiluminescence immunoassay analyzer automates the detection of proteins, hormones, infectious-disease markers, and cardiac biomarkers by exploiting light emitted during a chemical reaction between a labeled antibody and the target antigen. The instrument accepts whole blood, serum, or plasma specimens, runs reagent-mixing and incubation cycles, and then measures photon output fro --- ## Fully Automatic Fluorescence Immunoassay Analyzer Solution Based on IMX6ULL + FPGA - URL: https://intl.sienovo.cn/blog/141129565 - Date: 2024-08-12 - Tags: #ARMDev Fluorescence immunoassay (FIA) sits at the intersection of biochemistry and embedded systems engineering. This post walks through a complete hardware platform design for a fully automatic fluorescence immunoassay analyzer — a class of point-of-care instrument used in hospital laboratories to detect trace biomarkers in patient samples — built around an NXP i.MX6ULL application processor paired with an FPGA for real-time signal acquisition and control. ## What Fluorescence Immunoassay Actually Measures Fluorescence immunoassay technology exploits the highly selective binding between an antigen and its corresponding antibody. A fluorescent label is attached to one of the binding partners; when excitation light at the correct wavelength hits the label, it re-emits at a longer wavelength. The intensity of that emission is proportional to the concentration of the target analyte. The technique's three defining characteristics make it well-suited for clinical diagnostics: - **Strong specif --- ## PCR Gene Amplification Instrument Solution Based on IMX6ULL+FPGA - URL: https://intl.sienovo.cn/blog/141129512 - Date: 2024-08-12 - Tags: #IMX6ULL, #FPGA, #PCRThermalCycler PCR (polymerase chain reaction) gene amplification instruments sit at a demanding intersection of precision biology and real-time embedded control. A modern PCR thermal cycler must ramp temperatures with millikelvin accuracy, sustain tight cycle timing across 30–50 amplification cycles, and simultaneously drive a user interface, log data, and communicate results — all within a cost envelope that makes clinical and field deployment practical. This post walks through a hardware architecture that meets those demands by pairing NXP's i.MX 6ULL application processor with an FPGA on a compact, connector-mounted industrial core board. ## What PCR Instruments Actually Do A PCR gene amplification instrument — also called a PCR nucleic acid amplification instrument or polymerase chain reaction nucleic acid amplification instrument — automates the cyclic heating and cooling of a biological sample to exponentially copy a target DNA sequence. Typical applications include: - **Genetic disease scr --- ## NXP IMX6UL+MCU+FPGA-Based Medical Ventilator Solution - URL: https://intl.sienovo.cn/blog/141129340 - Date: 2024-08-12 - Tags: #ARMDev, #imx6ul, #fpga With the global outbreak of the COVID-19 pandemic, ventilators have become the most critical medical equipment for treating COVID-19 patients, earning them the title of "life-saving machines." The barriers to ventilator production and registration are high; transitioning to ventilator production requires overcoming multiple challenges, including raw material supply, component assembly, and registration and certification. Consequently, global ventilator production cannot be significantly increased in the short term. In the global ventilator market, the invasive ventilator segment is dominated by foreign brands. In China's invasive ventilator market, imported brands prevail, accounting for over 80% of the market share. ![医用呼吸机的AMR解决方案](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141129340/01_305023b2a7012d0942083567fb603155.jpeg) As an effective means of artificially replacing spontaneous ventilation, ventilators are widely used in cases of respiratory failure caused by v --- ## i.MX8M Plus + FPGA + AI Patient Monitor Solution - URL: https://intl.sienovo.cn/blog/141129205 - Date: 2024-08-12 - Tags: #FPGADev A patient monitor is a device or system that measures and controls a patient's physiological parameters, compares them with known set values, and can issue an alarm if these values exceed the set limits. ![监护仪ARM核心板解决方案](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141129205/01_6c4a1522dfb4bb8fed8868d4a0abbef0.jpeg) (1) Patient monitors primarily collect and measure human physiological parameters such as ECG, blood pressure, blood oxygen, and body temperature. This requires collecting and processing a large amount of data, and the system needs to handle multiple tasks in parallel, which consumes significant CPU resources. Based on the i.MX8M Plus, NXP's first i.MX8 series product to integrate a dedicated Neural Processing Unit (NPU), it focuses on machine learning and vision, advanced multimedia, and highly reliable industrial automation. It features powerful quad-core or dual-core Arm® Cortex®-A53 processors with an NPU, operating at up to 2.3 TOPS. The core board uses --- ## NXP i.MX8M Mini-based Anesthesia Depth Monitor Solution - URL: https://intl.sienovo.cn/blog/141129125 - Date: 2024-08-12 - Tags: #IMX8, #AnesthesiaAnalyzer Anesthesia depth monitoring is one of the most clinically sensitive measurement tasks in the operating room. Under-sedation risks patient awareness during surgery; over-sedation prolongs recovery and increases cardiovascular risk. This post covers Sienovo's hardware solution for a next-generation anesthesia depth monitor built around the NXP i.MX8M Mini SoC, explaining why the processor's heterogeneous architecture is well-suited to the real-time signal acquisition and display demands of this application. ## What an Anesthesia Depth Monitor Does An anesthesia depth monitor continuously acquires physiological signals — most commonly processed EEG (electroencephalogram) derived from frontal scalp electrodes — and computes a dimensionless index that represents the patient's level of consciousness. The most widely recognized index format is the Bispectral Index (BIS), though proprietary algorithms vary by manufacturer. The device must: - Sample and digitize weak bio-electrical signals w --- ## Portable Biochemical Analyzer ARM Solution - [Allwinner T113] - URL: https://intl.sienovo.cn/blog/141128289 - Date: 2024-08-12 - Tags: #ARMDev Anesthesia Depth Monitor Biochemical analyzers, often simply called biochemical instruments, are devices that use the principle of photoelectric colorimetry to measure specific chemical components in body fluids. Due to their fast measurement speed, high accuracy, and small reagent consumption, they are now widely used in hospitals of all levels, epidemic prevention stations, and family planning service centers. Their use can significantly improve the efficiency and benefits of routine biochemical testing. ![手持式生化分析仪-全志T113](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141128289/01_ea1e6365146d4170ab98e279d2c6e5e6.jpeg) A certain company adopted an Allwinner core board design. With the enhancement of ARM performance, the control section switched to using an ARM main control board. It runs on a Linux system, is powered by a lithium battery, is compact and portable, and is used for rapid microbial detection in medical systems. With the enhancement of ARM performance, the --- ## Plasma Medical Aesthetic Device RK3568 ARM+FPGA Solution - URL: https://intl.sienovo.cn/blog/141128206 - Date: 2024-08-12 - Tags: #RK3568 ## How Plasma Aesthetic Devices Work Plasma medical aesthetic devices achieve skin rejuvenation through a precise photochemical mechanism: a high-voltage, low-current electrical field ionizes atmospheric nitrogen and oxygen at the skin surface, creating a plasma arc. The free radicals and reactive oxygen species generated by this arc penetrate into the dermis, triggering a controlled inflammatory response. That response stimulates fibroblasts to synthesize new collagen and elastin, gradually restoring the skin's structural support network and reducing the appearance of fine lines and wrinkles — without ablating the epidermis the way traditional laser resurfacing does. ![等离子医疗美容仪](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141128206/01_eff85220294b0588cb7de7c5c3d92e10.jpeg) ![等离子医疗美容仪](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141128206/02_20dfc70a6ff48a6eb61b90b7b00b34a9.png) The clinical control system behind a device like this carries its own engineer --- ## Medical Endoscope RK3568 ARM+FPGA Solution - URL: https://intl.sienovo.cn/blog/141128130 - Date: 2024-08-12 - Tags: #ARMDev, #RK3568, #FPGA Medical Endoscope Endoscopes are inserted into the human body through natural orifices or small surgical incisions. When in use, the endoscope is guided into the organ to be examined, allowing direct visualization of changes in the relevant areas. The quality of the image directly impacts the effectiveness of the endoscope and signifies the level of development in endoscope technology. ![医用内窥镜.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141128130/01_ea391d50b2b00a1e4999ca8206fd7242.jpeg) A certain company leverages the domestically produced RK3568 core board to support high-end localized medical imaging instruments. With deep customization of kernel drivers, it has overcome USB signal transmission attenuation, achieving stable and clear image quality, dual-screen mirrored/extended display, and adaptability to multiple scenarios, leading to its widespread adoption. RK3568 Core Board 1. Clock speed 2GHz, 2GB RAM, 8GB ROM 2. HDMI and local LVDS screen, dual-screen --- ## [IVD] ARM+FPGA-based Fully Automatic Nucleic Acid Extractor - URL: https://intl.sienovo.cn/blog/141128034 - Date: 2024-08-12 - Tags: #IVD Fully Automatic Nucleic Acid Extractor ARM: NXP IMX8/IMX6U, TI AM62X/AM5728, RK: RK3588/RK3568 FPGA: Xilinx A7/K7/SPARTAN6/ZYNQ/MPSOC, Domestic Fudan Microelectronics, Anlogic, Gowin Semiconductor, Unigroup A fully automatic nucleic acid extractor is a high-precision, high-efficiency nucleic acid extraction device primarily used for extracting nucleic acids from samples. Its principle involves using an automated control system to perform nucleic acid extraction steps on samples through various reagent kits and software algorithms. It features simple operation, high speed, high efficiency, and high accuracy, and is widely used in biological laboratories, disease diagnosis, gene sequencing, and other fields. The fully automatic nucleic acid extractor is a simple, fast, and cost-effective instrument that can automatically purify DNA or RNA from samples such as whole blood, viruses, tissues, plants, bacteria, and cultured cells. It is now widely used in nucleic acid detection. ![全自动核 --- ## All-Domestic Phytium D2000/8 ITX Motherboard + Galaxy Kylin/UOS Operating System, Applied in Industrial All-in-One PCs, Industrial Tablet PCs, and Ruggedized Tablets - URL: https://intl.sienovo.cn/blog/141001847 - Date: 2024-08-07 - Tags: #Computer, #ipad, #ios, #PhytiumFullyDomestic **ITX-F601 All-in-One Motherboard Product Specification Sheet** 1. ****Product Overview**** The ITX-F601 is a high-performance all-in-one motherboard, designed and developed based on the domestically produced Phytium D2000/8-core processor. Featuring a low-profile I/O design, it can be used in industrial all-in-one PCs, industrial tablet PCs, and similar applications. With optimally arranged CPU, Mini-PCIe, and M.2 slots, and compatibility with Galaxy Kylin/UOS operating systems, it provides high performance, high stability, and high reliability for the overall solution. 1. ****Product Photos**** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/141001847/01_4182df96766848f793389be9d4023695.png)                                    Figure 1 – Physical Motherboard Image 1. ****Product Features**** 1. Features Phytium Tengrui D2000 8-core CPU, main frequency 2.0~2.3GHz 2. Motherboard integrates multiple display interfaces, supporting VGA, HDMI, LVDS 3. Supports 2 U --- ## Domestically Produced Phytium D2000 Discrete Graphics Pluggable OPS PC Motherboard, Applied in Xinchuang Education, Conferencing, Office, and Other Fields - URL: https://intl.sienovo.cn/blog/141001682 - Date: 2024-08-07 - Tags: #Phytium, #FullyDomestic, #OPSPC, #ITDomesticReplacement **Specification Sheet for Domestically Produced Phytium D2000 Motherboard** 1. ****Product Overview**** The XM-F611 is a discrete graphics pluggable OPS PC motherboard independently developed and designed by our company, compliant with the Intel OPS (Open Pluggable Specification) standard. It features a Phytium Tengrui D2000 octa-core processor and a domestically produced discrete graphics card, paired with domestic Galaxy Kylin or UOS operating systems. It offers functions such as synchronous display, broadcasting, and 4K@60Hz ultra-high-definition display, providing customers with higher display rates, shorter latency, and better display effects. This product offers advantages such as easy installation, easy maintenance, and easy upgrades. This OPS PC host is widely used in multi-functional electronic conferencing systems, large screen splicing, facial recognition, digital signage, interactive flat panel displays for education, multimedia advertising machines, interactive electr --- ## All-Domestic ARM+FPGA+Line Scan Camera: Principles, Technology, and Applications, Customizable - URL: https://intl.sienovo.cn/blog/140957901 - Date: 2024-08-06 - Tags: #DigitalCamera, #LineScanCamera ## All-Domestic ARM+FPGA+Line Scan Camera: Principles, Technology, and Applications, Customizable In this article, we will explore the principles, technology, and applications of line scan cameras, particularly focusing on their advantages over area scan cameras. Line scan cameras are essential in various industrial applications, and understanding their functionality can help in selecting the right camera for specific needs. ### Why are Line Scan Cameras Needed? Customers utilize line scan cameras for several reasons, primarily due to the following factors: 1. **Characteristics of the Target Object**: Line scan cameras are ideal for capturing moving, infinitely long objects such as fabrics, steel strips, film materials, and paper. They are also suitable for products of varying sizes, colors, and distributions on conveyor belts, including fruits, vegetables, ores, and metal parts. Additionally, they can effectively capture cylindrical objects like beverage cans and roller devices. --- ## SerDes Design Solution for LS1046A & LS1028A + FPGA Platforms - URL: https://intl.sienovo.cn/blog/140946216 - Date: 2024-08-06 - Tags: #FPGADev, #LS1046 **In this issue, we will dedicate an article to the SerDes resource allocation for this series of platforms.** The LS series products boast abundant resources, among which the SerDes protocol is often the most perplexing. Baidu Baike explains it as follows: SERDES is an abbreviation for SERializer/DESerializer. It is a mainstream time-division multiplexing (TDM), point-to-point (P2P) serial communication technology. Specifically, at the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, which then travel through a transmission medium (optical fiber or copper cable), and finally, at the receiving end, the high-speed serial signals are converted back into low-speed parallel signals. This point-to-point serial communication technology fully utilizes the channel capacity of the transmission medium, reduces the number of required transmission channels and device pins, enhances signal transmission speed, and thus significantly lowers commun --- ## NXP LS1028+FPGA Smart Networking Solution for Rail Transit and Industrial Control Applications - URL: https://intl.sienovo.cn/blog/140944581 - Date: 2024-08-06 - Tags: #Networking, #FPGADev, #ls1028 ## With the rapid development and application of technologies such as the Internet of Things (IoT), big data, and artificial intelligence, immense challenges have been brought to the traditional cloud computing model. This has also spurred a transformation in computing paradigms, leading to the birth of edge computing. ![LS1028/LS1043/LS1046+FPGA+TSN多路时间敏感性网络智能工业网关方案_云计算](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140944581/01_68ba04fb5a38a718bb30cee99a68a599.jpeg) Edge computing refers to an open platform that integrates core capabilities in networking, computing, storage, and applications on the side closer to the physical objects or data sources, providing services at the nearest point. Simply put, it means that after computing and processing data locally at the point of data collection (e.g., timestamping, data formatting, classifying events and process data), "on-site" decisions are made based on the results, followed by operations such as storing the processed --- ## Domestically Produced Gpixel Image Sensor + FPGA + AI High Frame Rate Machine Vision Industrial Camera Solution - URL: https://intl.sienovo.cn/blog/140932188 - Date: 2024-08-05 - Tags: #AI, #FPGADev, #IndustrialCamera In recent years, machine vision has been widely applied in smart manufacturing, automation, and other equipment to ensure product quality, control production processes, perceive environments, and more. For different application scenarios, inspection systems need to meet various technical specifications. Among these, image sensor resolution and frame rate are two extremely important metrics. High resolution facilitates more precise inspection, while high frame rates can improve overall system efficiency and reduce operating costs. The GMAX series offers low-noise, high-frame-rate global shutter area scan image sensors with various resolutions and aspect ratios, while the GL series consists of line scan image sensors. Some line scan image sensors also support TDI (Time Delay Integration) functionality, which improves sensitivity, enhances imaging quality, and reduces power consumption while maintaining a high line frequency. Flat Panel Display Inspection Semiconductor Inspection PCB / --- ## AIoT Product Solution Based on RK3588 with AI Support for Energy Online Monitoring System Applications - URL: https://intl.sienovo.cn/blog/140909213 - Date: 2024-08-04 - Tags: #Energy, #AI, #PowerMonitoring AIoT Product Solution Supporting Energy Online Monitoring System Applications In recent years, the smart energy industry has shown robust growth, benefiting from national policy support, market demand, and advanced technological backing. To drive the development of smart energy, we have created an AIoT product solution that supports energy online monitoring system applications. ![微信图片_20240428133909.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140909213/01_4a9908d258a591ed7c98718086511096.jpeg) **Market Potential of Energy Online Monitoring Systems** With the rapid development of the social economy, energy demand continues to grow. Notably, China's wind and photovoltaic power generation installed capacity already ranks first globally. China is also one of the world's largest energy consumers. Against this backdrop, promoting energy transformation and building a green, low-carbon, safe, and efficient modern energy system has become a national development strategy f --- ## X86+FPGA-based Modular Computer for Rail Transit, Standard 3U Fanless, Supports Domestic Customization - URL: https://intl.sienovo.cn/blog/140908979 - Date: 2024-08-04 - Tags: #AI, #EmbeddedHardware, #FPGADev, #RailComputer #### Supports Intel Socket G2 Mobile Sandy/Ivy Bridge i7/i5/i3 Processors, Intel QM67/QM77, 2\*LAN, 2\*USB2.0, 2\*USB3.0, 3\*COM, 3U ◆ Supports Intel Socket G2 Mobile Sandy/Ivy Bridge i7/i5/i3 Processors, Intel QM67/QM77 ◆ 1\*DDR3 SO-DIMM Memory ◆ 1\* VGA, 1\*HDMI ◆ 2\*LAN, 2\*USB2.0, 2\*USB3.0, 3\*COM ◆ Supports PCIe and PCI Expansion CPU Intel Socket G2 Mobile Sandy/Ivy Bridge i7/i5/i3 Chipset Intel QM67/QM77 Memory 1\*DDR3 SO-DIMM Memory Slot Storage RTM: SATA2-2.5-inch Hard Drive / CF Card (Optional) Display Interface VGA+HDMI Motherboard Module External Interface 1\*VGA, 1\*HDMI Network 1\*Intel WG82574 Gigabit Ethernet Port, 1\*Intel Wg82577 Gigabit Ethernet Port USB Interface 2\*USB2.0, 2\*USB3.0 COM Port 3\*COM I/O Interfaces PBP-09C05: AT or ATX Power Supply, 5\* Expansion Slots PBP-09C05P: ATX Power Supply, 5\* Expansion Slots, Supports PCIe and PCI Expansion AFC-964 Backplane: 2\*USB, 1\*Serial Port, 1\*VGA, 1\*SPEAK-OUT, 1\*MIC-IN, 1\*POWERSW, --- ## Huawei Atlas 500 Intelligent Edge Station + HarmonyOS AI High-Performance Edge Computing Solution - URL: https://intl.sienovo.cn/blog/140878241 - Date: 2024-08-02 - Tags: #harmonyos, #Huawei, #EmbeddedHardware, #AI ## Atlas 500 Intelligent Edge Station + HarmonyOS High-Performance Solution ## Technical Specifications ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140878241/01_b7a6604fd34147daa314c817fdd41916.png) Table 3-1 Technical Specifications **Item** **Description** Processor HiSilicon Hi3559A Processor * Dual-core ARM Cortex A73@1.6GHz, 32KB I-Cache, 64KB D-Cache / 512KB L2 cache * Dual-core ARM Cortex A53@1.2GHz, 32KB I-Cache, 32KB D-Cache / 256KB L2 cache * Single-core ARM Cortex A53@1.2GHz, 32KB I-Cache, 32KB D-Cache / 128KB L2 cache * Dual-core ARM Mali G71@900MHz, 256KB cache Processor Memory Specifications DDR4 4GB/8GB, 64bit, 2400Mbps Processor Encoding Capabilities * H.264 BP/MP/HP * H.265 Main Profile/Main 10 Profile * H.264/H.265 supports I/P/B frames * Supports MJPEG/JPEG Baseline encoding * H.264 encoding supports a maximum resolution of 8192 x 8640 pixels * H.265 encoding supports a maximum resolution of 16384 x 8640 pixels * H. --- ## FPGA-based 6U VPX Data Storage Board for Radar and In-Vehicle Signal Processing - URL: https://intl.sienovo.cn/blog/140866662 - Date: 2024-08-02 - Tags: #Architecture, #FPGADev, #AI This is a removable high-performance data storage board based on the 6U VPX bus architecture. The board uses one Xilinx Kintex-7 series FPGA as the main control unit, with an embedded RAID controller. It supports up to four mSATA SSDs, offering a maximum storage capacity of 8 TByte. The sustained data write bandwidth can reach 1.6 GByte/s, and the sustained read bandwidth can reach 1.7 GByte/s. The board features one SerialRapidIO x4 interface for backplane interconnection and one QSFP+ optical fiber interface for data interaction with external devices. This board separates the storage controller from the storage module, interconnecting them via high-speed connectors. It is particularly suitable for airborne and in-vehicle applications, allowing the storage module to be detached separately for data extraction on the ground or in a laboratory. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140866662/01_215cbbe61cb1d3ea74f4aac4178f390b.jpeg) * Supports up to 4 mSATA dr --- ## FPGA+DSP Architecture-based Intermediate Frequency Signal Acquisition, Processing, and Remote Optical Fiber Transmission System for Radar Applications - URL: https://intl.sienovo.cn/blog/140866489 - Date: 2024-08-02 - Tags: #FPGADev, #Networking This is a high-performance radar signal real-time acquisition and processing platform based on optical fiber transmission. The platform integrates an I/O unit, a signal processing unit, and a remote transmission unit, enabling real-time acquisition, real-time processing, high-speed transmission, and high-speed storage of radar signals. The system platform consists of one signal processing platform card and one 4-channel optical fiber acquisition card, as shown in Figure 1. The signal processing platform is equipped with one 8-channel, 250 MSPS sampling rate, 16-bit AD acquisition FMC daughter card. The system's operating principle is as follows: 8 channels of analog AD signals (from the antenna array) enter four high-speed ADCs via SSMC interfaces. The FPGA drives these four high-speed ADCs and completes real-time synchronous data acquisition of analog intermediate frequency signals. The FPGA features large-capacity on-board caching and performs complex algorithm processing, precisely --- ## Software Defined Radio Processing Platform Based on ZYNQ SOC + AD9361 - URL: https://intl.sienovo.cn/blog/140866349 - Date: 2024-08-02 - Tags: #AI, #EmbeddedHardware, #Inference This is a Software Defined Radio (SDR) processing platform based on Xilinx ZYNQ SOC. The platform utilizes a single Xilinx high-performance ZYNQ series SOC, the XC7Z020, to achieve 2-channel AD9361 RF signal transmission and reception. It is widely applicable in SDR (Software Defined Radio), mobile base stations, Wi-Fi, wireless local area networks, and specialized or general-purpose wireless equipment, among other applications. The ZYNQ 7000 is an extensible processing platform introduced by Xilinx. The ZYNQ SOC integrates a dual-core ARM Cortex-A9 processor, perfectly coupling the programmability of the FPGA with ARM's video and multimedia interfaces, making it suitable for low-power, low-cost signal processing products. Data interaction between the PS (Processing System) and PL (Programmable Logic) of this SOC is achieved via high-speed HP (High Performance) interfaces. The PS side can run operating systems like Linux and features an embedded Gigabit Ethernet protocol stack, facili --- ## Integrated EtherCAT+ADC+IO Testing Solution Based on ARM+FPGA - URL: https://intl.sienovo.cn/blog/140851296 - Date: 2024-08-01 - Tags: #FPGADev, #ARMDev Supported Hardware Standards and Custom Platforms: X86: INTEL ARM: RK3568/RK3588/TI/NXP/ Raspberry Pi /Allwinner T3/A40i, etc. FPGA: Xilinx A7/K7/SPARTAN6, Anlogic, Unigroup, etc. Some time ago, I shared Schneider's first EtherCAT bus-supported motion controller developed based on CODESYS. CODESYS + EtherCAT + X86 hardware platform: the standard configuration for high-performance motion control. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140851296/01_3f17b5377f17433397bfc1c95e746761.png) My first exposure to CODESYS was over ten years ago when using Beckhoff controllers. Later, around 2015, I gradually encountered some domestic controllers developed based on CODESYS. To be honest, at that time, there weren't many stable domestic controllers based on the CODESYS platform available. In the past two years, motion controllers based on CODESYS+EtherCAT+X86 hardware platforms have been emerging like mushrooms after rain. Especially after adopting X86 industrial PCs, --- ## Integrated Display and Control Solution Based on CODESYS Software + RK3568/T3/A40i, Customizable - URL: https://intl.sienovo.cn/blog/140850516 - Date: 2024-08-01 - Tags: #EmbeddedHardware, #AI, #FPGADev Xinmai VS Weintek, close partners of **CODESYS**, have once again launched a significant solution. It not only supports IoT communication protocols like MQTT / OPC UA, which facilitate digital factory transformation, but also enables a control solution where HMIs can replace PLCs at the field execution layer. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140850516/01_54c49b851b8b924dd4978754e5e43b8b.jpeg) **Distributed I/O Application** In factory automation, whether for product manufacturing, processing equipment, or entire flexible production lines, designers typically utilize HMIs, PLCs, and I/O modules for development, testing, and program debugging to control various digital and analog components like sensors, motors, and signal lights. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140850516/02_0f500271900eccaf5b288b987613c1c2.jpeg) **One Machine, Multiple Tasks: Your HMI is Your PLC** To meet market demand, we offer a programmable control --- ## Hardware Solution for Power Plant DCS Automatic Control Systems Featuring RK3568/RK3588 and Domestic FPGAs - URL: https://intl.sienovo.cn/blog/140829585 - Date: 2024-07-31 - Tags: #EmbeddedHardware, #AI, #FPGADev, #Power Hardware Solution for Power Plant DCS Automatic Control Systems As technology advances, intelligent technologies are increasingly being adopted in the power generation sector. Most power plants have fully implemented DCS automatic control systems to enhance safety and improve production efficiency in their power generation processes. Focusing on the intelligent development of power plants, we have developed dedicated industrial PCs for DCS automatic control systems. **Power Plant DCS Automatic Control System** The DCS automatic control system, also known as a Distributed Control System or Distributed Computer Control System, is a new generation of instrumentation and control system developed based on microprocessors. It adheres to design principles of distributed control functions, centralized display and operation, and balancing autonomous subsystems with integrated coordination. Implementing this system allows for monitoring various parameters in the power plant production proces --- ## Building a Robust Power Inspection Robot Controller Based on RK3588 + YOLO Model - URL: https://intl.sienovo.cn/blog/140829220 - Date: 2024-07-31 - Tags: #AI, #RK3588, #Robotics Innovatively Developing Computer Product Solutions for Power Inspection Robots Currently, the construction of smart grids and the enhancement of power supply reliability have become national strategies. This has fully unleashed the immense demand for monitoring, operation, and maintenance of China's vast power infrastructure, leading to a surge in market demand for substation and distribution station inspection robots. **1. Market Advantages of Power Inspection Robots** Intelligent inspection of power systems is a crucial means to ensure the healthy operation of power equipment and guarantee power supply safety. With the continuous development and implementation of large-capacity, ultra-high voltage, and long-distance power transmission projects in China, the shortcomings of traditional "manual inspection + fixed-point inspection with testing instruments" methods—such as poor inspection quality, high labor intensity, and low O&M efficiency—are becoming increasingly apparent. Couple --- ## RK3588J-based Embedded AI Motherboard for Power Inspection Robot System Control - URL: https://intl.sienovo.cn/blog/140823675 - Date: 2024-07-31 - Tags: #Robotics, #AI Smart Inspection ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140823675/01_2d86b7176bb28b4dcd528e2cf346d59b.jpeg) Sienovo provides computer hardware such as core boards, 3.5-inch boards, Mini-ITX motherboards, Micro-ATX motherboards, and embedded barebones systems based on Intel, Rockchip, and Phytium platforms. The products feature compact size and low power consumption design, offering rich I/O interfaces including serial ports, USB, LAN, and Mini-PCIe expansion slots. They boast excellent expandability and high stability, making them suitable for real-time inspection management system equipment such as power inspection robots and inspection drones. Promoting the Implementation of Embedded AI Applications to Safeguard Digital Transformation of Power Stations In the construction of smart grid systems, a key focus is on achieving machine-assisted operations and intelligent O&M through power station digitalization. By expanding the smart grid domain with embedded AI --- ## RK3588 + MIPI + 8-Channel AHD + AI Analysis Camera Application in Sanitation and Construction Vehicles - URL: https://intl.sienovo.cn/blog/140694293 - Date: 2024-07-30 - Tags: #AI, #RK3588, #AHD Common camera interfaces typically include MIPI, USB, DVP, etc. However, MIPI cameras are limited by the transmission distance of high-speed signals, which means traces cannot be too long. This severely restricts their use in security monitoring, automotive, and other fields. Therefore, technologies are introduced to extend the camera's data transmission distance, such as the serdes mentioned in previous articles. This article primarily focuses on debugging AHD cameras with the RK3588. (1) AHD Camera There are many introductions to AHD cameras online, so I won't elaborate here. It's worth noting that AHD cameras are somewhat similar to the serdes I introduced previously, with one goal being to increase transmission distance. They are commonly used in automotive, security, and other fields. AHD is an analog camera, so an AD conversion chip is required to convert the signal and output a digital signal for the main controller to receive. (2) Conversion Chip The aforementioned AHD came --- ## RDC x86 CPU+FPGA Module, Supporting WinCE 5.0, WinCE 6.0, DOS, Win2000, WinXP, Linux, QNX, and Other Operating Systems - URL: https://intl.sienovo.cn/blog/140766800 - Date: 2024-07-29 - Tags: #FPGADev, #linux, #DevOps ## RDC 3306-Based SOM Express Module: A Compact x86+FPGA Platform for Industrial Computing When a design requires the familiar x86 instruction set in a ruggedized, space-constrained form factor, the SOM Express module built around the RDC 3306 processor is worth a close look. This article walks through the module's hardware architecture, key peripheral set, FPGA integration, and broad operating-system support — giving engineers enough detail to evaluate it for embedded industrial, automation, or HMI applications. ## The RDC 3306 Processor The RDC 3306 is an x86-architecture SoC from RDC Semiconductor designed specifically for embedded and industrial use. Running at 1 GHz, it integrates CPU, memory controller, and peripheral logic into a single chip, reducing board complexity and power draw compared to a traditional chipset-based PC design. The x86 ISA means that mature toolchains, BSPs, and commercial operating systems can target the platform without porting effort — a meaningful ad --- ## RDC CPU + FPGA PC/104 Module, Supporting WinCE5.0, WinCE6.0, DOS, Win2000, WinXP, Linux, QNX, and Other Operating Systems - URL: https://intl.sienovo.cn/blog/140766520 - Date: 2024-07-29 - Tags: #EmbeddedHardware, #AI, #RDC ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140766520/01_493ce0d6c4ac4c368f42f26c74380466.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140766520/02_7fa079af03de429990d5bdbde434928f.png) This is a PC/104 embedded motherboard based on the RDC 3308. The RDC 3308 X86-architecture CPU is widely applicable in industrial fields, especially in harsh environments. The EB-9460 features pin-header breakouts for all I/O interfaces, enhancing convenience and stability during use. To improve usability, the EB-9460 is equipped with three USB ports, one of which supports hot-swapping under DOS. Specifications Product Type PC/104 Embedded Motherboard Chipset SOC CPU RDC 3308 1GHz Processor Memory Onboard 128MB DDRII Memory Display TTL, VGA. VGA supports a maximum resolution of 1024×768 Storage 1×44-pin IDE USB 3×USB 2.0, one supporting hot-swapping under DOS Serial Ports 2×RS-232 1×RS-485 1×RS-232/422/485 LPT 1×LPT PS/2 PS/2 Keyboard/Mouse I --- ## Celeron® J1900/N2807/2930 +FPGA PCI104 Module, Supports WinXP (no hardware graphics acceleration) OS, Wide Temperature - URL: https://intl.sienovo.cn/blog/140766308 - Date: 2024-07-29 - Tags: #EmbeddedHardware, #RDC, #PC104 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140766308/01_33b71b55ea5b45efba55a7113be502c1.png) ## Celeron® J1900/N2807/2930 PCI104 Module Specifications Product Type PCI 104 Embedded Motherboard Chipset SOC CPU Intel® Celeron® Processor J1900/N2807/2930 Memory Onboard 2GB DDR3L Dual-Channel Memory BIOS AMI Display LVDS 18/24-bit, VGA LVDS supports max resolution of 1366×768, VGA supports max resolution of 2048×1024 Supports dual independent displays Storage 1×SATA II HDD Interface, 1×Mini SATA USB 4×USB 2.0 Serial Port 3×RS-232, 1×RS-232/485 Audio HD Audio Input/Output Network Port 1×10/100/1000Mbps Intel® 82574L Ethernet Expansion 1×PCI104 (PCI Signal) Power Supply N2807: DC 5V/12V≤6W N2930: DC 5V/12V≤9W J1900: DC 5V/12V ≤12W GPIO 16-bit Input / Output (multiplexed with LPT) Operating Temperature -20~60℃ Storage Temperature -40~85℃, 0%~95% RH, non-condensing Dimensions 116mm × 96mm OS Supports Win7, Win8, Linux, QNX and other ope --- ## 3U/6U CPCI System Core Modules for Power, Rail Transit, and Other Fields - URL: https://intl.sienovo.cn/blog/140725536 - Date: 2024-07-26 - Tags: #FPGADev, #EmbeddedHardware, #AI **I. 3U CPCI Core Module** Offering CPCI series products, featuring high performance, flexible application expansion, X86 software compatibility, fanless design, wide operating temperature range, and a long embedded lifecycle, to meet diverse customer needs. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140725536/01_ae3c808721c54cf6909a8a7666335475.png) ### Product Features Intel Pentium M(Dothan)/Celeron M(Dothan) Processor Series Standard 3U CPCI Architecture Ultra-low power consumption High reliability ### Product Specifications #### Hardware Pentium M(Dothan)/Celeron M(Dothan) (Clock speed 600MHz~2GHz) Intel 85X Chipset 256M/512M SDRAM Intel Integrated Display Controller supporting independent dual display Graphics memory up to 32MB UMA DVI-I Interface 4x USB2.0 Interfaces Onboard CF Card Socket ICH4 Built-in Dual Channel IDE (UMDA33/66/100) 10/100 Base-T Ethernet Controller AC97 Compatible Audio Controller 2x RS232 Serial Ports Supports PS/2 K --- ## Intel x86 + FPGA + AI-based Multi-Network, Multi-Serial Power Gateway and Power Communication Controller - URL: https://intl.sienovo.cn/blog/140725368 - Date: 2024-07-26 - Tags: #FPGADev, #Power * 3U processor module supports Intel Atom single-core or dual-core processors, PM single-core 600MHz-1.4GHz, with optional Core i3, i5, i7. * Backplane: Compatible with PICMG 2.0 R3.0 specification Power Supply: 3U form factor power supply Specifications: Input Voltage: AC 160-260V, DC 160-300V Chassis: 19-inch rack-mount, 3U high chassis NIC: Supports 2-4 100M Ethernet ports Serial Port Card: Provides 4-8 optional RS232, RS485, RS422 serial ports ### Product Specifications #### Hardware Intel® Atom™ Processor N455/D525 Series Fanless Design Up to 1.5GB DDR3 Onboard Memory 1 VGA Port Audio Interface PS/2 Keyboard and Mouse 18 Serial Ports 6 Gigabit Ethernet Ports 4 USB 2.0 Ports #### Software Operating System: Supports Linux, VxWorks, Windows, etc. #### Other Power Supply: AC 220V Operating Temperature: -40～+70℃ ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140725368/01_08630c3105514b1084ad63ce82314a09.png) **II. An easy-to-inst --- ## Embedded Computer System Based on Phytium FT2000 - URL: https://intl.sienovo.cn/blog/140721701 - Date: 2024-07-26 - Tags: #AI, #Computer As a leading manufacturer of embedded computers in China, we were among the first to enter the rail transit sector. Our industrial-grade AFC embedded computer series products fully embody the characteristics of the new generation of mainstream AFC technologies for rail transit, providing an excellent system platform for the upgrade and replacement of rail transit AFC systems. * ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140721701/01_18c12413abf496c0153e8c770ee50684.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140721701/02_f631b3dca5eedbb41b8a98bf75aa5c84.png) #### Standardization Utilizing Intel's new generation mainstream low-power embedded processors with an open architecture, we were the first in the industry to achieve a standardized design on a single system platform, adaptable to various machine types within AFC systems. * ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140721701/03_4a0725b36c1ae1db34134a4 --- ## Industrial PCs for Locomotive Monitoring Systems (WIN CE/Win2000/QNX/VxWorks, etc.) - URL: https://intl.sienovo.cn/blog/140721560 - Date: 2024-07-26 - Tags: #MCU, #EmbeddedHardware The basic components of a locomotive monitoring system primarily consist of: Monitoring host, display screen, accident status recorder, speed sensor, pressure sensor, locomotive horn recording interface device, GPS information receiver, bus expansion box, main/auxiliary switching device, and leveling signal interface box. * ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140721560/01_06c66eb0d5e386e05aafe6d0c08409d8.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140721560/02_d90b5bf9b6342c1dc010706a6062907e.png) #### High-Reliability Touchscreen Features a high-reliability touchscreen with a built-in adaptive backlight brightness controller, ensuring uniform illumination of the display in any environment. * ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140721560/03_4e6721f2bba862c49d126f2babf13843.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140721560/04_e728783cdd7325072 --- ## Industrial All-in-One PC Based on Intel x86+FPGA+AI, Supporting Medical CT Scanner Applications - URL: https://intl.sienovo.cn/blog/140709820 - Date: 2024-07-26 - Tags: #FPGADev, #AI It is widely recognized that medical imaging equipment is one of the most promising sub-sectors in the medical device industry. CT scanners (referred to as CT), for example, are an ideal choice for doctors in clinical examination and diagnosis of various diseases. **Development Potential and Challenges of Medical CT Scanners** CT, or Computed Tomography, uses a computer to control and adjust X-ray beams, ultrasound, etc. High-sensitivity detectors scan the human body layer by layer from all angles to generate digital signals, which are then integrated on a computer platform to produce a detailed image of the human body. It features fast scanning times, comprehensive data, and clear images, capable of revealing minute lesions in organs, abnormalities in bone density, and more. This assists doctors in more efficient and accurate lesion diagnosis and treatment planning, leading to its widespread use. ![1672276699854795.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/1407 --- ## Intel X86 + FPGA + AI Industrial PC: Supporting Medical Imaging Equipment Applications in Ultrasound Scanners, CT Machines, and MRI Systems - URL: https://intl.sienovo.cn/blog/140709533 - Date: 2024-07-26 - Tags: #AI, #BigData, #EmbeddedHardware, #MedicalDevice Medical Imaging ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140709533/01_d44061477cd586d9811a64057ee6fc1a.jpeg) Xinmai Technology provides computer hardware such as core boards, Mini-ITX motherboards, PICO-ITX motherboards, and industrial PCs based on Intel, Hisilicon, NXP, and Rockchip platforms. The products feature onboard memory, integrate ultra-HD encoding/decoding video engines, possess excellent data processing and graphics processing capabilities, and offer highly integrated functionality. They can be applied in medical imaging equipment such as ultrasound scanners, CT machines, magnetic resonance imaging systems, and digital X-ray imaging systems. Embedded Product Solutions Based on 10th Gen Intel Core Processors Support Medical Imaging Equipment Applications In recent years, China's medical imaging equipment market has developed rapidly. Actively expanding into the medical imaging equipment industry, we have launched a series of embedded computing produc --- ## Industrial Panel PCs with Intel 10th Gen Core Processors for Medical Equipment - URL: https://intl.sienovo.cn/blog/140709162 - Date: 2024-07-26 - Tags: #Computer, #AI, #EmbeddedHardware, #MedicalTablet ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140709162/01_d5d7a681e3ce85bed9e1b1990f8a18b4.jpeg) Sienovo Technology offers computer hardware based on Intel, Hisilicon, NXP, and Rockchip platforms, including core boards, Mini-ITX motherboards, PICO-ITX motherboards, and industrial complete systems. These products feature onboard memory and integrated ultra-high-definition video encoding/decoding engines, delivering excellent data and graphics processing capabilities. With high functional integration, they are suitable for medical imaging equipment such as ultrasound machines, CT scanners, MRI systems, and digital X-ray imaging systems. Industrial Panel PCs with Intel 10th Gen Core Processor Series for Medical Applications Currently, emerging information technologies such as artificial intelligence, big data, and the Internet of Things are being deeply integrated into the healthcare industry, driving continuous advancements in hospital informatization. As a result, --- ## RK3568+GMSL+ADAS Multi-Channel In-Vehicle Camera Low-Cost Solution - URL: https://intl.sienovo.cn/blog/140705408 - Date: 2024-07-26 - Tags: #AI The RK3568, as the most widely used domestically produced low-cost, high-performance SOC currently available on the market, boasts powerful hardware configurations. In the rapidly developing smart automotive industry, with increasing demands for image data processing, efficiently collecting data or running AI applications has become a critical need. Our newly launched 4/8-channel GMSL acquisition/edge computing box product addresses these requirements. Rich Interface Options All-aluminum alloy, robust heat dissipation, fanless design Driven by innovation in a new generation of information technology and supported by national policies, the ultra-high-definition video industry is increasingly active, forming a large-scale emerging industrial cluster. Continuously creating new application scenarios, we have developed industrial control motherboards and complete industrial PC solutions based on the Rockchip RK3568 processor to meet the demands of 8K ultra-high-definition video display --- ## Loongson 2K1000 + Centec CTC7132 Fully Domestically Produced VPX Switch Board: 48 Gigabit Ethernet Ports and 8 SFP+ 10 Gigabit Optical Ports - URL: https://intl.sienovo.cn/blog/140696817 - Date: 2024-07-25 - Tags: #EmbeddedHardware, #VPX, #NetworkSwitch, #Loongson 一、概述 The XMSW9118 fully domestically produced switch board provides a maximum of 48 10/100/1000BASE-T Ethernet interfaces and 8 SFP+ 10 Gigabit optical ports. It can achieve full-port wire-speed forwarding of data packets, supporting unicast, multicast, and broadcast packet types. It provides network port indicators, power indicators, and system operation indicators. The 48 10/100/1000BASE-T Ethernet interfaces use VPX connectors, and the 8 SFP+ 10 Gigabit optical ports use standard 10 Gigabit optical interfaces. 二、原理框图 The block diagram of the switch board is shown below, mainly composed of the CPU system, CTC7132 switching system, clock and power system, and other parts. It provides 48 10/100/1000BASE-T Ethernet interfaces and 8 SFP+ 10 Gigabit optical ports. The CPU system uses Loongson 2K1000I as the processor, achieving control and management of the entire switch module through interfaces such as PCIe, management Ethernet port, debug serial port, and I2C. The switching subsy --- ## RK3588 + MIPI + GMSL + AI Camera: Automotive 4/8-Channel GMSL Capture & Edge Computing Box Solution - URL: https://intl.sienovo.cn/blog/140695659 - Date: 2024-07-25 - Tags: #AI, #RK3588 The RK3588, as the most powerful domestic SoC currently available on the market, boasts powerful hardware configurations. With the rapid development of smart vehicles and increasing demands for vast amounts of image data, efficiently collecting data or running AI applications has become a critical need. Our newly launched 4/8-channel GMSL capture / edge computing box product meets these demands. Extensive Connectivity ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140695659/01_91c2c2ff694e4264bea9150d9473c710.png) All-aluminum alloy, robust fanless cooling Driven by innovation in new-generation information technology and supported by national policies, the ultra-high-definition (UHD) video industry is becoming increasingly active, forming a large-scale emerging industrial cluster. Continuously creating new application scenarios, we have developed industrial control motherboards and complete industrial PC solutions based on the Rockchip RK3588 processor, which meet t --- ## x86+FPGA+AI: Face-Scan Entry Across the Entire Subway Network, Dedicated Computers for Subway Smart Ticketing Systems - URL: https://intl.sienovo.cn/blog/140583056 - Date: 2024-07-21 - Tags: #AI, #FPGADev Face-scan entry for the entire subway network | Dedicated computers for subway smart ticketing systems available Recently, Chengdu Metro officially launched its "Smart Ticketing" system across its entire network of subway stations. The full-channel contactless "face-scan entry while wearing a mask" method has optimized passenger travel efficiency and reduced the risk of cross-infection during the pandemic, thus receiving widespread praise! **01、Innovative Development of Subway Ticketing Systems** Ticketing management systems are a crucial component of urban rail transit construction. They leverage electronic technology, automatic control technology, wireless transmission technology, computer network technology, and more, to achieve seamless integration between terminal devices such as automatic ticket vending machines (TVMs) and smart gates, and electronic ticketing and settlement systems. This enables intelligent functions such as computer network-based ticket sales, ticket inspec --- ## AFC Automatic Fare Collection System Controller Based on x86+FPGA+AI Fanless Barebone System - URL: https://intl.sienovo.cn/blog/140582981 - Date: 2024-07-21 - Tags: #AI, #RailTransit Icewing Fanless Barebone System: The Ideal Choice for AFC Automatic Fare Collection System Development Against the backdrop of building a strong transportation nation and smart transportation infrastructure, artificial intelligence, big data, computer, and network technologies are rapidly integrating and being applied in the transportation sector, helping to enhance the intelligence and automation levels of travel services. The application of Automatic Fare Collection (AFC) systems in the rail transit sector is one such typical example. ![1677562673586946.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140582981/01_4a3820dbd288c2fc3900fdaf8bc71a51.jpeg) Image source: Qiantu.com The Automatic Fare Collection (AFC) system is an intelligent system that automates the entire process of ticketing, fare collection, statistics, and management in rail transit. It integrates computer technology, mechanical manufacturing technology, and more, consisting of system workstations, --- ## Domestically Produced Industrial PC for Rail Transit: AFC System Controller Implementation Based on Phytium E2000Q - URL: https://intl.sienovo.cn/blog/140582892 - Date: 2024-07-21 - Tags: #SignalProcessing, #AI, #RailTransit AFC System ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140582892/01_032c00fac246f73a3929fb04e956cf1e.jpeg) We offer computer hardware such as core boards, PICO-ITX boards, 3.5-inch boards, Mini-ITX motherboards, and embedded barebones systems based on Intel, NXP, and Rockchip platforms. The products feature excellent data transmission and processing capabilities, onboard memory, CPU-integrated graphics control, and rich I/O interfaces including serial ports, USB, LAN, and PCIe expansion slots. They can be applied in areas such as rail transit ticketing systems, consumption statistics systems, and access control systems. An Ideal Choice for AFC System Control China has become the country with the largest urban rail transit operating mileage globally. AFC system applications are showing a development trend towards widespread adoption, high efficiency, and intelligence. In response to this major trend, we have developed a series of industrial PCs capable of AFC syste --- ## [Medical Imaging] X86+FPGA: Industrial Motherboard Supporting AI Medical Imaging Equipment Applications, Empowering CT, MRI, X-ray, Ultrasound, and Other Medical Imaging Devices - URL: https://intl.sienovo.cn/blog/140547972 - Date: 2024-07-19 - Tags: #AI, #SignalProcessing, #FPGADev Industrial Motherboard Supporting AI Medical Imaging Equipment Applications In the context of China's accelerating aging population, continuously growing demand for diagnostic imaging, and the successive introduction of national regulations and policies favorable to the development of the high-end medical imaging market, the AI medical imaging equipment industry is entering a golden period of development. Keeping pace with this development trend, we have developed a motherboard suitable for AI medical imaging equipment, based on 12th/13th generation Intel Core processors. ![1702618251956614.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140547972/01_c70c2c13a09206ebeac02569327beafa.jpeg) AI medical imaging is one of the most mature technological fields in the "Healthcare + AI" development. Enhanced by technologies such as computer-aided diagnosis, AI-assisted treatment, and AI quantitative analysis, it enables medical imaging equipment like CT, MRI, X-ray, and ultras --- ## [Medical Imaging] RK3588 + FPGA: Meeting the 8K Audio/Video Encoding/Decoding and High-Efficiency Transmission Requirements of Telemedicine Systems - URL: https://intl.sienovo.cn/blog/140547420 - Date: 2024-07-19 - Tags: #ARMDev, #FPGADev, #VideoCodec, #IVD, #MedicalImaging Medical imaging and telemedicine are among the most demanding application domains for embedded computing hardware. High-resolution diagnostic imagery, real-time video consultation, and AI-assisted diagnosis all impose simultaneous burdens on compute, memory bandwidth, codec throughput, and network I/O. This post examines how Rockchip RK3588-based industrial boards address those burdens in two concrete use cases: telemedicine video systems and medical imaging information systems (MIIS). ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140547420/01_882602ef9c9e15233bd551957a249b20.jpeg) Sienovo supplies computer hardware — Computer-on-Modules (CoMs), Mini-ITX motherboards, PICO-ITX motherboards, and industrial PCs — built on Intel, NXP, and Rockchip platforms. Each integrates ultra-high-definition encode/decode video engines and is qualified for use inside ultrasound machines, CT scanners, MRI systems, and digital X-ray imaging systems. ## Meeting the 8K Audio/Video Encodi --- ## In Vitro Diagnostics: Applications of ARM/X86 + FPGA Embedded Computers in Immunoassay Equipment - URL: https://intl.sienovo.cn/blog/140545841 - Date: 2024-07-19 - Tags: #Networking, #IVD, #AI In Vitro Diagnostics ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140545841/01_57621e6fc24d5c2384b428cdf9261d02.jpeg) Xinmai provides computer hardware such as core boards, 2.5-inch motherboards, Mini-ITX motherboards, 4-inch motherboards, PICO-ITX motherboards, and embedded barebones systems based on Intel, AMD, and NXP platforms. Our products support independent dual displays like VGA+HDMI, offer rich I/O interfaces such as serial ports, USB, GPIO, and PCIe expansion slots, boast strong expandability, and feature ultra-high stability and reliability. They are suitable for various in vitro diagnostic instruments, including biochemical analyzers, immunoassay analyzers, and electrolyte and blood gas analyzers. **Applications of Embedded Computers in Immunoassay Equipment** Immunoassay equipment is a type of in vitro diagnostic instrument that is increasingly applied in various clinical fields, meeting the needs of the developing medical testing industry. Fully autom --- ## [IVD] Applications of ARM/X86 + FPGA Embedded Computers in Medical CT Scanners - URL: https://intl.sienovo.cn/blog/140545771 - Date: 2024-07-19 - Tags: #AI, #SignalProcessing, #IVD CT scanning relies on precise measurements of how different tissues absorb X-rays — and turning those raw attenuation measurements into a clinically useful cross-sectional image demands serious computing power at every stage of the signal chain. This post examines how ARM- and x86-based embedded computers, paired with FPGA-capable expansion, address the real-time data acquisition, image reconstruction, and display requirements inside modern medical CT systems, and why the same hardware family serves the broader in-vitro diagnostics (IVD) market. ## How a CT Scanner Uses Its Computing Subsystem CT (Computed Tomography) combines advanced X-ray imaging with digital signal processing. The scanner emits X-rays that pass through the body; detector arrays measure the attenuated signal from hundreds of angles as the gantry rotates. Each detector reading represents how much energy a particular tissue column absorbed. The raw sinogram data is then back-projected and filtered — a mathematically --- ## In Vitro Diagnostics: Applications of ARM+FPGA Embedded Computers in Fully Automatic Blood Gas Analyzers and Automatic Biochemical Analyzers - URL: https://intl.sienovo.cn/blog/140543149 - Date: 2024-07-19 - Tags: #AI, #IVD In Vitro Diagnostics ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140543149/01_1fe80b8a3fb4b8199511583bd452fa4b.jpeg) We provide computer hardware such as core boards, 2.5-inch motherboards, Mini-ITX motherboards, 4-inch motherboards, PICO-ITX motherboards, and embedded barebone systems based on Intel, AMD, and NXP platforms. Our products support independent dual displays like VGA+HDMI and offer a rich array of I/O interfaces including serial ports, USB, GPIO, and PCIe expansion slots. With strong expandability, ultra-high stability, and reliability, they are suitable for various in vitro diagnostic instruments, such as biochemical analyzers, immunoassay analyzers, and electrolyte and blood gas analyzers. ## **Applications of Embedded Computers in Fully Automatic Blood Gas Analyzers** In recent years, driven by the rapid advancements in the internet, computer technology, and laboratory medicine, China's in vitro diagnostics industry has become increasingly active. --- ## X86+FPGA+AI-Based Digital Medical Devices: Fully Automatic Urine Sediment Analyzer - URL: https://intl.sienovo.cn/blog/140529210 - Date: 2024-07-18 - Tags: #FPGADev, #AI Empowering the development of digital healthcare, Xinmai offers dedicated computers for fully automatic urine sediment analyzers. With the continuous advancement of information technology, healthcare has entered a brand new digital era. The digitization of medical devices, in particular, has greatly enriched the content and capacity of medical information, presenting broad market development prospects. **Digital Medical Devices: Fully Automatic Urine Sediment Analyzer** The digitization of medical devices, as it is called, is a new modern medical approach that leverages computer technology and integrates advanced techniques like big data analytics and artificial intelligence recognition. It automates processes such as data acquisition, storage, transmission, and processing, enabling dynamic visualization of data and real-time sharing of analysis results. For instance, the advent of fully automatic urine sediment analyzers, as highly intelligent and fully automated instruments for a --- ## X86+FPGA+AI-based Telemedicine System Supporting 12th/13th Gen Intel Core Processors - URL: https://intl.sienovo.cn/blog/140528952 - Date: 2024-07-18 - Tags: #AI Industrial Motherboard: Supports 12th/13th Gen Intel Core Processors, Suitable for Telemedicine Systems In response to the trends of digitalization, networking, and intelligentization, China's healthcare industry reform is actively progressing. New models and business forms such as telemedicine and smart healthcare are innovating and developing, and the market space is continuously expanding. Industrial motherboards built on 12th/13th Gen Intel Core processors support telemedicine system applications. **Widespread Application of Telemedicine Technology** Telemedicine, in essence, is a new medical service model that relies on computer technology, sensor technology, remote sensing/telemetry/remote control technology, etc., to effectively connect medical resources with patients, achieving resource sharing and optimized allocation for hospitals. It can break geographical and temporal limitations, bringing higher-quality medical technologies and methods from large hospitals or specialize --- ## Railway Train Control and Management System (TCMS) Integrated Display Unit, DDU Driver Display Unit, Compliant with European Railway Application Standard EN50155 - URL: https://intl.sienovo.cn/blog/140528618 - Date: 2024-07-18 - Tags: #SignalProcessing, #AI, #TCMS ### Railway TCMS System Integrated Display Unit The DDU, also known as the Driver Display Unit, is used to show the driver the operating status of the signaling system and traction system, and is widely applied in metro and railway rolling stock. This is a railway TCMS system integrated display unit, featuring an Intel@ ATOM™ N2600 processor. It is designed for operation in TX temperature environments ranging from -40 to +70ºC and meets the electromagnetic compatibility, shock, and vibration test requirements of the European railway application standard EN50155. It is a hardware display unit specifically designed for Railway Train Control and Management Systems (TCMS). * High-brightness, sunlight-readable touchscreen display with automatic brightness adjustment based on ambient light. * Intel@ ATOM™ N2600 dual-core processor, 2GB DDR3 memory. * Die-cast magnesium-aluminum alloy enclosure, front panel IP65, rear IP42. * 2 x M12-D 10/100Mb Ethernet ports, upgradeable to 1000M --- ## 3U 19-inch Rackmount System for Railway and Metro Passenger Information Systems (PIS), Meeting European Railway Application Standards - URL: https://intl.sienovo.cn/blog/140528507 - Date: 2024-07-18 - Tags: #linux, #DevOps, #Server A 3U 19-inch rackmount system, featuring a high-performance, low-power i5 processor, capable of operating in environments with a temperature range (TX: -25 to +55º C), and meeting the requirements of European railway application standard EN50155 for electromagnetic compatibility, shock, and vibration testing. It is a product designed for railway and metro Passenger Information Systems (PIS). * * 3U 19-inch Rackmount System * High-performance, low-power i5 processor * Large-capacity 4GB DDR3 high-speed memory * 2 x M12-D 10/100Mb Ethernet ports, upgradable to 1000Mb (M12-A) * PCI, PCI-E, MiniPCIe expansion slots, supporting various applications such as video encoding cards, 3G, and WiFi * 4 x DB9 isolated serial ports (2 x RS232, 2 x RS485) * 8-channel isolated I/O, remote switch signal input * DC 60V～160V input, meeting railway vehicle power supply requirements * Fully compliant with EN50155 standard ![](https://pub-048dcb96257f476 --- ## Rack-mount System for Railway and Metro Passenger Information Systems (PIS), Featuring Railway-Specific M12 Network Interfaces and Compliance with European Railway Application Standards - URL: https://intl.sienovo.cn/blog/140527850 - Date: 2024-07-18 - Tags: #EmbeddedHardware, #SignalProcessing, #AI, #Railway ### Rack-mount System This 2U 19-inch rack-mount system features a high-performance, low-power processor, capable of operating in wide temperature environments. It meets the requirements of European railway application standard EN50155 for electromagnetic compatibility, shock, and vibration tests, making it an ideal product for railway and metro Passenger Information Systems (PIS). * * 6th generation embedded low-power, high-performance platform * High-quality railway-specific M12 network interfaces * Easy-maintenance, fully removable expansion bay design * Compliant with EN50155 European railway standard * High-reliability, long-life supercapacitor ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140527850/01_3217e5fe260248f4a035b2df2686ead7.png) System Configuration Processor Onboard Intel® Core™ i7-6822EQ 2.0GHz (Max 2.8GHz) Quad-core, Eight-thread Onboard Intel® Core™ i5-6442EQ 1.9GHz (Max 2.7GHz) Quad-core, Four-thread Chipset Intel --- ## DianHong (Power Harmony) Based Edge Computing Gateway, Supports Customization - URL: https://intl.sienovo.cn/blog/140523159 - Date: 2024-07-18 - Tags: #PowerHarmonyOS, #HarmonyOS 1 Product Information The edge computing gateway, based on the T-Head TH1520 chip, supports the OpenHarmony small system. It is a crucial hub connecting IoT devices and cloud platforms, applicable for data collection and forwarding in scenarios such as urban infrastructure, smart factories, smart buildings, business outlets, and operation service centers. 2 Product Highlights ● Powerful Edge Computing Capabilities Quad-core Xuantie C910 CPU with a maximum frequency of 2.5GHz, 64-bit LPDDR4X-3733, and 4 TOPs empower the gateway's edge computing capabilities. It enables IoT edge real-time response, fast connectivity, intelligent applications, and effectively reduces cloud computing workload. ● Reliable Network Connectivity with Multiple Protocols Multiple internet access options: Supports Fast Ethernet, Wi-Fi, and 3G/LTE CAT4/LTE CAT1 networks. Compatible with a wide range of mainstream protocols, including: Zigbee 3.0, LoRaWAN, Matter, BLE 5.0, Modbus. ● Comprehensive Security P --- ## 【Data Center Accelerator Card】PCIe Bus Architecture-based 20G Ethernet Real-time Packet Capture and Storage Card, Featuring Analysis, Filtering, Encryption Processing, and Other Algorithms. Supports Fully Domestic Customization - URL: https://intl.sienovo.cn/blog/140451432 - Date: 2024-07-15 - Tags: #FPGADev, #Server, #AI, #SignalProcessing * 2-channel 10G SFP+ Fiber Optic Interfaces * PCIe x8 Host Interface, System Bandwidth 3.2 GByte/s * 10 Gigabit Network Protocol * Supports Packet Lengths: 64B~1518 Bytes * Supports Hardware Playback * Storage Bandwidth: 800 MByte/s ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140451432/01_1c2986af2aac41d687a5d7918f5951e6.png) This 20G Ethernet real-time packet capture and storage card, based on PCIe bus architecture, is a half-height, half-length PCIe card, suitable for mainstream half-height server chassis or micro-workstations. The board utilizes an FPGA controller, enabling real-time transmission and reception of 20G Ethernet data. It applies algorithms for analysis, filtering, and encryption processing to Ethernet packets, stores the data in real-time, and can also perform real-time playback of recorded data files. It offers high stability, reliability, and real-time performance. This card can be widely used in data centers, servers, and other applic --- ## Data Center Accelerator Card: K7 Series FPGA 40G Fibre Channel Adapter Based on PCIe Bus Architecture - URL: https://intl.sienovo.cn/blog/140451306 - Date: 2024-07-15 - Tags: #FPGADev, #SignalProcessing, #AI, #Server * 2x 40G QSFP+ Fibre Channel * PCIe x8 Host Interface, supporting 5Gbps/lane, system bandwidth 4GByte/s * Fibre Channel supports RapidIO, Aurora, and other protocol standards, up to 10Gbps/lane * Independent DDR4 SDRAM Cache, operating clock frequency 1200MHz * 1 Digital Discrete I/O Interface * High-Performance Clock Management Unit ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140451306/01_8636f08f8ebd4ce59145cdbd79c88c6c.png) This 4-channel 10G Fibre Channel adapter, based on PCIe bus architecture, features four SFP+ 10 Gigabit optical interfaces and an x8 PCIe host interface. It includes one group of 64-bit DDR3 SDRAM as high-speed cache, enabling high-speed acquisition, real-time recording, and broadband playback of 4-channel optical network data. The card also features four SATA interfaces, enabling high-speed storage of optical fiber data. It supports the SATA 3.0 standard, with a maximum storage bandwidth of 1.6 GByte/s. This card is a standard ful --- ## [Data Center Accelerator Card] Virtex UltraScale+ Series FPGA XCVU3P+ 100G Data Center Processing Accelerator Card - URL: https://intl.sienovo.cn/blog/140451228 - Date: 2024-07-15 - Tags: #MCU, #EmbeddedHardware, #SignalProcessing, #AI, #Server * 4x 100G QSFP28 Optical Fiber Channels * PCIe x16 Host Interface, supporting XDMA and Scatter-Gather DMA * Optical fiber channels support Aurora and other protocol standards, up to 25Gbps/lane * 2 independent sets of DDR4 SDRAM memory, operating at 1200MHz clock frequency * Multiple digital discrete I/O interfaces * High-performance clock management unit ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140451228/01_d0753ce950d34317a9f5d4d7c0e4d98c.png) This 4-channel QSFP28 100G optical fiber channel adapter, based on a PCIe bus architecture, features one PCIe Gen3x16 host interface and a total of four QSFP28 100G optical fiber interfaces. It enables real-time data acquisition, real-time buffering, and high-speed PCIe transmission for four QSFP28 100G optical fiber channels. The board utilizes Xilinx's high-performance Virtex UltraScale+ series FPGA XCVU3P as its main processor and includes two independent 80-bit DDR4 SDRAM large-capacity data buffers. The b --- ## High-Performance Data Preprocessing Platform with Multi-FPGA PCIe Bus Architecture Based on 5 K7 FPGAs - URL: https://intl.sienovo.cn/blog/140423364 - Date: 2024-07-14 - Tags: #Networking * Onboard FPGA Real-time Processor: XCKU060-2FFVA1517 * 2 QSFP+ Optical Interfaces, supporting up to 10Gbps/lane * Onboard DMA Controller for high-speed bidirectional DMA transfers * Supports x8 PCIe Host Interface, system bandwidth 5GByte/s * 1 RJ45 Adaptive Gigabit Ethernet Port * 1 FMC+ Daughter Card Expansion Interface ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140423364/01_4c4512cf04214bb39bc9c20f978e2997.png) This high-performance data preprocessing FMC carrier board is based on a PCIe bus architecture. The board features 1 FMC+ (HPC) interface, 1 PCIe x8 host interface, 1 RJ45 Gigabit Ethernet port, and 2 QSFP+ 40G optical fiber interfaces. It utilizes Xilinx's high-performance Kintex UltraScale series FPGA as a real-time processor to enable FMC interface data acquisition, processing, and backplane interface interconnection. The board includes two independent 72-bit DDR4 SDRAM large-capacity caches. By integrating various FMC daughter cards, this --- ## [AI Server] 2-Port 10G Fibre Channel Adapter Based on PCIe Bus Architecture - URL: https://intl.sienovo.cn/blog/140423317 - Date: 2024-07-14 - Tags: #Server, #Architecture, #FPGADev * 2-Port 10G SFP+ Fibre Channel * PCIe x8 Host Interface, supports 5Gbps/lane, system bandwidth 4GByte/s * Fibre Channel supports RapidIO, Aurora, and other protocol standards, up to 10Gbps/lane * Features 1 independent DDR3 SDRAM cache, operating clock frequency 500MHz * Features a high-performance clock management unit * Supports 8-channel digital discrete I/O ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140423317/01_0adfa47ecb384ee4a09bc93fa09344ce.png) A 2-port 10G Fibre Channel adapter based on PCI Express bus architecture. This product is a half-height, half-length PCIe card, suitable for mainstream half-height server chassis or micro-workstations. The board uses a Xilinx 28nm Kintex-7 series FPGA as the main processor, features one 64-bit DDR3 SDRAM as high-speed cache, and the front panel has two SFP+ optical transceivers, providing 2x 10G Fibre Channel or Ethernet data transceiver capabilities. The board uses air cooling and has temperature monit --- ## [AI Servers] FPGA (K7) + PCIe Bus Architecture-based 4-Channel 10G Fiber Optic Adapter - URL: https://intl.sienovo.cn/blog/140423250 - Date: 2024-07-14 - Tags: #Architecture, #FPGADev, #Server, #AI, #SignalProcessing * 4-channel 10G SFP+ Fiber Optic Channels * PCIe x8 Host Interface, supports 5Gbps/lane, system bandwidth 4GByte/s * Fiber Optic Channels support RapidIO, Aurora, and other protocol standards, up to 10Gbps/lane * Independent DDR3 SDRAM cache, operating clock frequency 500MHz * 4-channel SATA 3.0 interface * High-performance clock management unit ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140423250/01_2e308b7669274c1d88d120c95260b3df.png) A 4-channel 10G fiber optic adapter based on a PCI Express bus architecture, the board features four SFP+ 10 Gigabit fiber optic interfaces, an x8 PCIe host interface, and one group of 64-bit DDR3 SDRAM as high-speed cache, enabling high-speed acquisition, real-time recording, and broadband playback of 4-channel fiber optic network data. The board also features four SATA interfaces, enabling high-speed storage of fiber optic data, supporting the SATA 3.0 standard, with a maximum storage bandwidth of up to 1.6 GByte/s. T --- ## 4-Channel Cameralink Base Image Emulator Based on FPGA (K7) and PXIe Bus Architecture - URL: https://intl.sienovo.cn/blog/140423180 - Date: 2024-07-14 - Tags: #Architecture, #FPGADev, #SignalProcessing, #AI #### Software Support * Optional integrated board-level software development kit (BSP); 1. FPGA low-level interface drivers; 2. Board-level interconnect interface drivers; * Customized algorithms and system integration can be provided according to customer requirements: #### Application Areas * Software-defined radio (SDR); * Radar and baseband signal processing; * High-speed image and graphics processing; * Standard 3U PXIe form factor * Supports 4-channel Cameralink Base image output * Onboard 1 XC7K325T FPGA processor * Supports x8 PCIe host interface, system bandwidth 4 GByte/s * Onboard HJ30J connector, supports 4 Cameralink interfaces * Supports RS232/RS422/RS485 interfaces ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140423180/01_5ae258ee8bd84b58b807d997ea129215.png) A 4-channel Cameralink Base image emulator based on the PXI Express bus architecture. This board features one FMC (HPC) interface and one x8 PCIe host interface --- ## Fudan Micro FPGA and FMC Standard-based 1-channel CameraLink Full Input, 1-channel DVI Output Mezzanine Card Module - URL: https://intl.sienovo.cn/blog/140423105 - Date: 2024-07-14 - Tags: #MCU, #EmbeddedHardware * Standard FMC mezzanine card, compliant with VITA57 specification * Supports 1-channel CameraLink Full mode or 2-channel CameraLink Base mode input * Supports 80-bit Deca mode (Full Plus mode), with a maximum bandwidth of 850 MByte/s * CameraLink receiver chip supports up to 85MHz clock frequency * Features 1-channel RS232/RS422/RS485 interface * Features 1-channel DVI display output interface, supports 1080P resolution ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140423105/01_214d611c60ac49c892287cd1fa41c9ed.png) This mezzanine card module is based on the FMC interface standard, featuring 1-channel CameraLink Full mode (or 2-channel CameraLink Base mode) acquisition and 1-channel HDMI (DVI) video output. The module has two CameraLink ports (SDR, 26PIN) that can be hardware configured for 1-channel Full input or 2-channel Base mode input. The CameraLink interface supports 80-bit Deca mode (i.e., Full Plus mode). This module supports 1-channel DVI video o --- ## FMC-Standard-Based 1-Channel FPGA + CameraLink Full Output Mezzanine Card Module - URL: https://intl.sienovo.cn/blog/140423026 - Date: 2024-07-14 - Tags: #EmbeddedHardware, #AI, #SignalProcessing * Standard FMC mezzanine card, compliant with VITA57 specification * Supports 1-channel CameraLink Full mode or 2-channel CameraLink Base mode * Supports 80-bit Deca mode (Full Plus mode), with a maximum bandwidth of 850 MByte/s * CameraLink transmitter chip supports a maximum clock frequency of 85 MHz * Features 1-channel RS232/RS422/RS485 interface * Features 8-channel digital discrete I/O interfaces ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140423026/01_df8548b1d7e748ab887a356a0810f623.png) This CameraLink Transmitter FMC Mezzanine Card Module supports image signal output in either 2-channel CameraLink Base mode or 1-channel CameraLink Full mode. The board features two CameraLink ports (SDR26), which can serve as outputs for simulated cameras. #### Technical Specifications * Image Interface Performance: 1. Supports 2-channel CameraLink Base digital camera output; 2. Supports 1-channel CameraLink Full mode output; 3. Supports 80-bi --- ## 16-Channel Dynamic Signal Acquisition Card Based on FPGA+AD+PXIe Bus Architecture - URL: https://intl.sienovo.cn/blog/140408122 - Date: 2024-07-13 - Tags: #Networking, #FMSH, #AI * Standard 3U PXIe Specification * Onboard FPGA Real-time Processor: XCKU060-2FFVA1517I * Onboard 1 set of DDR4 SDRAM high-speed data buffer * Supports x8 PCIe Host Interface, System Bandwidth 5 GByte/s * Supports 1-channel RJ45 Gigabit Ethernet Interface * Supports 2-channel RS485 Interfaces ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140408122/01_7c100d269f35476ca10966cf90b0ed52.png)A high-performance 16-channel high-precision dynamic signal acquisition card based on PXI Express bus architecture. This card is specifically designed for sound and vibration applications. A single board features 16 synchronous analog input channels with 24-bit resolution, and the maximum sampling rate per channel can reach 150 KSPS. Each channel integrates an independent IEPE excitation source, enabling signal conditioning for accelerometer sensors and microphones. It supports AC/DC coupling, can be independently configured via software, and supports zero-point calibration. --- ## Rackmount 4U Height 6U 6-Slot VPX System Platform - URL: https://intl.sienovo.cn/blog/140408065 - Date: 2024-07-13 - Tags: #Networking, #AI, #FPGADev A high-performance, high-reliability application system platform based on the 6U VPX bus architecture, supporting VPX and OpenVPX protocol standards. This system platform utilizes a high-performance 6-slot 6U VPX backplane with a highly optimized topology, capable of providing users with various high-speed serial bus interconnections. The platform supports standard VPX plug-in power supplies and high-power module power supplies, offering maximum design support for VPX system power. This platform supports rear plug-in card design, facilitating user IO expansion. This system platform can be widely used for real-time data acquisition, processing, transmission, and storage in harsh environments such as laboratories, field operations, and aircraft cabins, making it suitable for aerospace, aviation, marine, and other application scenarios. * Standard 4U height VPX system platform, supporting rackmount and desktop applications * Compliant with OpenVPX/VPX standards, conforming to VITA46 --- ## 6U VPX Bus Real-time Signal Processing Platform Based on XC7VX690T FPGA + ZU15EG SOC (Supports 4 Optical Fiber Channels) - URL: https://intl.sienovo.cn/blog/140407985 - Date: 2024-07-13 - Tags: #FPGADev, #SignalProcessing * 6U VPX architecture, compliant with VITA 46 specification * Onboard high-performance FPGA processor: XC7VX690T-2FFG1927I * Onboard 1 high-performance MPSoC: XCZU15EG-2FFVB1156I * Onboard 1 MCU for health management, clock configuration, etc. * V7 FPGA connected to 2 FMC+ interfaces * Interconnection between the two FPGAs via high-speed GTH transceivers ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140407985/01_496d5d33bc6e4b07b880c84129abfb6e.png) A general-purpose real-time signal processing platform based on the 6U VPX bus architecture. This platform utilizes a high-performance Xilinx Virtex series FPGA (XC7VX690T-2FFG1927I) as a pre-processing unit, with 2 external FMC+ expansion interfaces for data acquisition, data playback, and real-time signal processing algorithms. A high-performance embedded processor, the ZYNQ UltraScale series ZU15EG, with an ARM core, is used as the main processor to implement communication, management, and other functions. T --- ## Fully Localized FPGA+AI Artificial Intelligence Heterogeneous Computing Platform Based on Fudan Micro JFMQL100TAI, Compatible with XC7Z045-2FFG900I - URL: https://intl.sienovo.cn/blog/140407817 - Date: 2024-07-13 - Tags: #FPGADev, #AI A fully localized ARM core board based on Shanghai Fudan Microelectronics FMQL45T900. This core board integrates the minimal system of Fudan Micro's FMQL45T900 (compatible with XILINX's XC7Z045-2FFG900I) onto an 87*117mm core board. It can serve as a core module for functional expansion, enabling rapid construction of a signal processing platform and facilitating user product development. The core board features DDR3 SDRAM, eMMC, SPI Flash, Ethernet PHY chips, and more. I/O expansion for the PL (Programmable Logic) side is achieved through two board-to-board FMC connectors. The FMQL45T900 is an all-programmable SoC developed by Fudan Microelectronics. It integrates a Processing System (PS) based on a feature-rich quad-core processor and Programmable Logic (PL) on a single chip, utilizing an advanced 28nm process. Coupled with corresponding development software, it enables an integrated hardware and software platform, facilitating user development, shortening development cycles, and re --- ## 4x 100G Optical Fiber Accelerator Card based on V7 FPGA, Applicable to Server-Based Fibre Channel Data Acquisition, Data Transmission, and Other Scenarios - URL: https://intl.sienovo.cn/blog/140264754 - Date: 2024-07-08 - Tags: #MCU, #EmbeddedHardware * 4x 100G QSFP28 Fiber Channels * PCIe x16 Host Interface, supports XDMA, supports SG DMA * Fiber channels support Aurora and other protocol standards, up to 25Gbps/lane * 2 independent sets of DDR4 SDRAM buffers, operating clock frequency 1200MHz * Multiple digital discrete I/O interfaces * High-performance clock management unit ![](https://pub-048dcb96257f476697b113fcb5939cb7.r2.dev/blog/140264754/01_6b7e34f3e79d43de96c13e970617dc3d.png) #### Functional Block Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb7.r2.dev/blog/140264754/02_4802b108b731f7c6268749eb5b2a4b74.png) A 4-channel QSFP28 100G Fibre Channel adapter based on a PCIe bus architecture. The card features one PCIe Gen3x16 host interface and a total of four QSFP28 100G fiber interfaces, enabling real-time data acquisition, real-time buffering, and high-speed PCIe transmission for four QSFP28 100G fiber channels. The card uses Xilinx's high-performance Virtex UltraScale+ series FPGA XCVU3P as the main --- ## Fully Domesticated Data Acquisition and AI Platform based on Fudan Micro V7 690T FPGA, ARM/Hygon X86, and AI - URL: https://intl.sienovo.cn/blog/140263606 - Date: 2024-07-08 - Tags: #FPGADev, #FMSH, #AI * Domestic FPGA: JFM7VX690T80 * Host Interface: PCIe Gen3 x8 @ 8Gbps/lane * Fiber Optic Channels: 4 SFP+ fiber channels on front panel, 1 QSFP+ fiber channel on rear panel * 2 independent DDR3 SDRAM memory banks, operating clock frequency 800MHz * 2 FMC+ expansion interfaces: Each supports 16 GTH lanes, line rate 10Gbps/lane * 1 RJ45 Gigabit Ethernet interface ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140263606/01_6bf1114d0d5749b5a05a6683bf10df33.png) #### Functional Block Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140263606/02_b6f7ba33f43870486579f5ab90a90cf4.png) This is a fully domesticated 8-channel fiber optic dual-FMC interface data preprocessing platform based on a domestic 28nm 7-series FPGA 7VX690T. The board utilizes a high-performance 7-series FPGA as a real-time processor, implementing 4-channel 10G SFP+ fiber optic and 1-channel QSFP+ communication interfaces, and providing 1-channel x8 PCIe data transmission. I --- ## AI Data Processing Platform Based on Fully Domestically Produced Fudan Micro JFM7K325T + ARM - URL: https://intl.sienovo.cn/blog/140262005 - Date: 2024-07-08 - Tags: #FMSHJFM7K325T, #AI #### Fudan Micro can be integrated with ARM platforms such as: RK3588/TI AM62X/ NXP IMX.8P/FeiTeng FT2000, etc. #### Product Overview        This high-performance data pre-processing FMC carrier board is based on a PCIe bus architecture. The board utilizes Fudan Micro's JFM7K325T FPGA as a real-time processor to enable interconnection between various interfaces. This board can achieve 100% domestic production. It features one FMC (HPC) interface, one PCIe x8 host interface, and an onboard 64-bit DDR3 SDRAM large-capacity cache. The board supports one 1000BASE-T Gigabit Ethernet interface and four RS422 interfaces, as well as GPIO input and output. By integrating different FMC daughter cards, this board can quickly establish a server-based hardware platform for data acquisition, real-time processing, and high-performance storage. The board is a standard full-height PCI Express size, making it suitable for current mainstream servers or workstations. It can be widely applied in scenari --- ## X86/ARM Industrial PC + K7 FPGA AI Data Processing Platform, Applicable to Radar and IF Signal Acquisition, Video Image Acquisition and Transmission, and Other Application Scenarios. - URL: https://intl.sienovo.cn/blog/140261724 - Date: 2024-07-08 - Tags: #Architecture, #ARM+K7 #### Product Overview This high-performance data pre-processing FMC carrier board is based on a PCI Express bus architecture. The board features one FMC (HPC) interface and one x8 PCIe host interface. It utilizes a Xilinx high-performance Kintex-7 series FPGA as the real-time processor to achieve data acquisition and processing from the FMC interface, as well as conversion for the PCI Express bus interface. An independent 64-bit DDR3 SDRAM large-capacity cache is onboard. By integrating different FMC daughter cards, this board can quickly establish a PCI Express bus-based verification platform. As a standard full-height, half-length PCIe card, it is suitable for use in PCIe industrial PCs and applicable to scenarios such as radar and IF signal acquisition, and video image acquisition and transmission. * Standard PCIe full-height, half-length card * 1 FMC (HPC) interface, compliant with VITA57 specification * Onboard 1 XC7K325T FPGA processor * Supports x8 PCIe host interface --- ## Fudan Micro JFMVU3P-2FFVC1517 FPGA+AI Fully Localized AI Data Processing Platform, Suitable for Radar and IF Signal Acquisition, Video and Image Acquisition - URL: https://intl.sienovo.cn/blog/140261409 - Date: 2024-07-08 - Tags: #FPGADev, #AI ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140261409/01_553d8ed0ddb34b50afc40e13067a4bd6.png) * Onboard FPGA Real-time Processor: JFMVU3P-2FFVC1517 * Supports 1 FMC (HPC) Expansion Interface * Supports 2 QSFP+ Optical Fiber Interfaces * Supports x8 Gen3 PCIe Host Interface, System Bandwidth > 5 GByte/s * Supports 1 RJ45 Adaptive Gigabit Ethernet Port * Supports 1 GPIO/RS422 Interface A fully localized high-performance data pre-processing platform based on Fudan Micro's 16nm process JFM9VU3P FPGA with a PCIe bus architecture. The board features one FMC+ (HPC) interface, one PCIe x8 host interface, one RJ45 Gigabit Ethernet port, and two QSFP+ 40G optical fiber interfaces. The board utilizes Fudan Micro's high-performance 9-series FPGA as a real-time processor to achieve functions such as FMC interface data acquisition, processing, and transmission. Its SerDes interfaces support speeds up to 28Gbps, enabling ultra-high-speed bus protocols like JESD204C an --- ## x86 Chip Customization, EtherCAT Chip Customization, IP Services, for Motion Control, Industrial Bus, and other Integrated Hardware-Software Systems - URL: https://intl.sienovo.cn/blog/140161967 - Date: 2024-07-08 - Tags: #FPGADev, #AI x86 Chip Customization, EtherCAT Chip Customization ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140161967/01_7bb0d53a45f127d0270fa77abb7359ef.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140161967/02_108592b702252d3d0408b867e93b75d6.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140161967/03_890db8b354c58328326e5051780966d1.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140161967/04_3fe026e00f946928907a3f7ca8ba9b24.jpeg) **X86 Platform** Our R&D engineers have accumulated extensive experience in motherboard and complete system design. We can align with your product specification and scenario requirements, and quickly deliver prototypes, including products in various forms such as motherboards, BOX PCs, tablet PCs, and CPCI. Cost reduction, long lifecycle, rapid delivery, and timely response are our strengths. ® Custom Integrated Circuit Services Flexible Services, Complete Solutions Custom Instruction S --- ## X86 + PC104 + Support for WinCE 5.0, WinCE 6.0, DOS, WinXP, QNX, and other operating systems, Industrial Control Data Acquisition Core Module Board Customization - URL: https://intl.sienovo.cn/blog/140159352 - Date: 2024-07-03 - Tags: #FPGADev ## CPU Module This is an SOM Express module based on the RDC 3306. The RDC 3306 X86-architecture CPU is a high-performance, highly stable processor. It is a flexible and compact mainboard (measuring 91.8mm × 68.6mm) that can be flexibly integrated into a user's baseboard, saving development costs. The module's connectors use a pin header design to ensure stability during use. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140159352/01_db4805a806dde6079057910bb64026aa.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140159352/02_e51efce1edf3414e4bb6289e73b418f2.png) Specifications Product Type SOM Express Module Chipset SOC CPU RDC 3306 1GHz Processor Memory Onboard 512MB DDRⅡ Memory Display LVDS 18-bit, TTL, VGA. LVDS and VGA support a maximum resolution of 1024×768 USB 4×USB 2.0, 1×USB Device Interface Serial Ports 3×RS-232, programmable baud rate from 50 to 460.8K bps Audio Standard Audio Input/Output Ethernet 1×10/100Mbps Etherne --- ## X86 + PC104 + Supporting Operating Systems like WinCE5.0, WinCE6.0, DOS, Win2000, WinXP, Linux, QNX, etc., Industrial Control Board Customization - URL: https://intl.sienovo.cn/blog/140159206 - Date: 2024-07-03 - Tags: #linux, #DevOps, #Server ## Celeron® N2807 PC104 Module ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140159206/01_6db837ce5a9ededde5ab1eeec3503e85.png)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140159206/02_192a22ee30ed9e5ac3de249ad3703cd4.png) Specifications Product Type PC/104 Motherboard Chipset SOC CPU Intel® Celeron® N2807 1.58 GHz Memory Onboard 2GB DDR3L Dual-Channel Memory BIOS AMI Display LVDS 18/24-bit, VGA LVDS supports a maximum resolution of 1366×768, VGA supports a maximum resolution of 2048×1024 Supports Dual Independent Displays Storage 1×Mini SAT USB 4×USB 2.0 Serial Ports 4×RS-232, 1 channel optional RS485 PS/2 PS/2 Keyboard/Mouse Interface Network Ports 2×Intel® 82574L Expansion 1×PC104 Power Supply DC 12V Watchdog Software GPIO 8/16-channel Input/Output Operating Temperature -20~60℃ Storage Temperature -40~85℃, 0%~95% RH, non-condensing Dimensions 1 1 6 m m×9 6 m m OS Supports operating systems such as QNX, Linux, Wi --- ## Effortless Localized Private Deployment of Large Models – AIBOX 1684X Computing Box, Suitable for Multi-Channel Vision Industrial Inspection and Other Scenarios - URL: https://intl.sienovo.cn/blog/140106336 - Date: 2024-07-01 - Tags: #FPGADev, #VisionInspection The AIBOX 1684X features the SOPHON BM1684X AI processor, configurable with 16GB large memory and 128GB eMMC; it supports a peak computing power of 32 TOPS (INT8), 16 TFLOPS (FP16/BF16) computing power, and 2 TFLOPS (FP32) high-precision computing power; it supports 32-channel H.265/H.264 1080p@25fps video decoding; it supports mainstream programming frameworks, with a complete and user-friendly toolchain, and low algorithm migration cost; it is applicable to various AI computing scenarios such as visual computing, edge computing, general computing services, smart transportation, unmanned supermarkets, and drones. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140106336/01_5ddf6ddf195e16d9cedcad6a791b326d.jpeg) 01 Rich Algorithms, Comprehensive AI Private Deployment Rich algorithms, #HotspotEngineProgram# comprehensive AI private deployment 02 Supports private deployment of ultra-large parameter models under Transformer architecture, such as large language models lik --- ## Exploring the Advanced Technology of Industrial AI Smart Cameras - URL: https://intl.sienovo.cn/blog/140102017 - Date: 2024-07-01 - Tags: #AI, #Technology In today's rapidly evolving field of industrial intelligence, the Industrial AI Smart Camera series is gaining significant attention both domestically and internationally for its exceptional performance and versatility (a review link from an international engineer is available at the end of this post). Powered by Raspberry Pi CM4, it is designed for a wide range of applications, covering everything from simple barcode scanning to AI-based defect detection in industrial environments. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140102017/01_6d865a77bd7466af0be31f2409ec0be9.png) This camera series features a powerful quad-core Cortex-A72 (ARM v8) 64-bit SoC, clocked at up to 1.5GHz. It offers versatile storage options, providing 8GB, 16GB, and 32GB eMMC models to meet diverse data requirements. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140102017/02_3e5b921241392a56588de57bf8315395.png) _System Block Diagram of the CM4 AI Smart Camera_ At its core --- ## X86+FPGA+AI-based Control Solution for Cutting Machines and Six-Axis Robots - URL: https://intl.sienovo.cn/blog/140100142 - Date: 2024-07-01 - Tags: #FPGADev, #VisionInspection, #AI 一、智能设备控制 应用场景 Intelligent Manufacturing (IM) is a human-machine integrated intelligent system composed of intelligent machines and human experts. It can perform intelligent activities such as analysis, reasoning, judgment, conception, and decision-making during the manufacturing process. Through collaboration between humans and intelligent machines, it expands, extends, and partially replaces the mental labor of human experts in the manufacturing process. It updates the concept of manufacturing automation, extending it to flexibility, intelligence, and high integration. Intelligent control systems include Fieldbus Distributed Control Systems (FCS), large-scale integrated network control systems, high-end Programmable Logic Controllers (PLCs), equipment-oriented embedded control systems, and functional safety monitoring systems. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140100142/01_0ea5fa0675ced45de5246bbc88a756c9.png) ##### 客户需求 Dual Gigabit Ethernet ports Ser --- ## X86+FPGA+AI-Based Chip Defect Detection Solution - URL: https://intl.sienovo.cn/blog/140100015 - Date: 2024-07-01 - Tags: #AI, #VisionInspection Application Scenarios With the advancement of semiconductor technology, the demand for higher chip yield rates is increasing. However, the manufacturing process for integrated circuit chips is complex, and many defects often arise during their production. Therefore, defect detection is an essential process in integrated circuit manufacturing. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140100015/01_e2644f63267ad7a7f2c73ee584b859ba.png) ##### Customer Requirements Compact size, low power consumption 2 x USB, 1 x LAN Fanless Core-i platform system Supports -10~60°C operating temperature Ensures 24/7 uninterrupted operation ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140100015/02_49867c79da4d1a357f3fb197ab800579.png) ### Product Features Onboard Intel® Celeron 4305UE CPU, with a maximum clock speed of 2.0GHz Supports single-channel DDR4 1866/2133MHz SO-DIMM memory slot, with a maximum memory capacity of 32GB Supports 3 Gigabit Ethernet ports Suppo --- ## X86+FPGA+AI-based Smart Warehousing AGV Robot Solution - URL: https://intl.sienovo.cn/blog/140099802 - Date: 2024-07-01 - Tags: #FPGADev Application Scenarios Smart warehousing is a segment of the logistics process. The application of smart warehousing ensures the speed and accuracy of data input at various stages of goods and warehouse management, allowing enterprises to promptly and accurately grasp real-time inventory data, and to reasonably maintain and control their inventory. Currently, the handling process largely employs AGVs. AGV intelligent handling robots automatically transport items to designated locations using special landmark navigation. The most common guidance methods include magnetic strip guidance, laser guidance, and RFID guidance. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140099802/01_bb18904aac9c9a08206c8b022e6de990.png) ##### Client Requirements Ultra-thin, low power consumption, fanless, capable of supporting operating temperatures from -10~60°C, and requiring high shock resistance. Supports bus interfaces such as USB, COM, and LAN. Additionally, it supports expansion fun --- ## X86+FPGA-Based Solution for Precision Machining and Inspection Equipment - URL: https://intl.sienovo.cn/blog/140099665 - Date: 2024-07-01 - Tags: #FPGADev Application Scenarios With the development of high-tech industries and national defense modernization in China, there is an increasing demand for large optoelectronic devices in fields such as aviation and aerospace, micro-devices in micro-electromechanical and optoelectronic information fields, and the processing of complex parts. All these applications necessitate the use of precision, or even ultra-precision, machining and inspection equipment. ##### Customer Requirements High precision, high efficiency ##### Product Features Intel® 6th/7th Gen Core™ i7/i5/i3/Pentium®/Celeron® Processors, supporting up to 95W TDP, with Intel vPro support; Dual-channel, 4-slot DDR4 2133/2400MHz, up to 64GB; Supports VGA, DVI-D, DP++ triple display; Supports dual Intel GbEs, USB3.0, 16-bit GPIO; Supports 4 SATA3.0, RAID0/1/5/10; Supports 2 x RS-232/422/485, 2 x RS-232/485, and 2 x RS-232 serial ports, with 5V/12V voltage output; Supports 2 PCIe X16, 3 PCIe X4, 2 PCI; Supports 6 USB3.0, 6 USB2.0, --- ## Smart Process Defect Detection Based on x86/ARM + FPGA + AI Industrial Cameras, Capable of Detecting Point, Line, and Surface Defects - URL: https://intl.sienovo.cn/blog/140099548 - Date: 2024-07-01 - Tags: #ARMDev, #FPGADev Application Scenarios Defect detection plays an extremely important role in the manufacturing process of products. Smart industrial defect detection can replace traditional manual inspection, reduce human error and omissions, significantly improve product quality, and simultaneously lower factory labor costs. Smart process defect detection technology can detect point, line, and surface defects, enabling faster identification of product surface flaws and defects, thereby promoting product quality in enterprises and factories, and advancing intelligent automation in manufacturing. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140099548/01_05d95997e5a3d9961828e3d1c22d830f.png) ##### Customer Requirements High performance, high-speed operation Equipped with 2 or more expansion slots for adding image data acquisition cards Supports communication with multiple serial ports and acquisition modules Supports various display interfaces ##### Product Features High performanc --- ## x86+FPGA+AI-based Bearing Defect Visual Inspection System, Bogie Spring Smart Inspection System - URL: https://intl.sienovo.cn/blog/140098713 - Date: 2024-07-01 - Tags: #CameraModule 一、Bearing Defect Visual Inspection System Application Scenarios Automatic inspection equipment for shaft parts, integrating advanced technologies such as optics, mechanics, software, hardware, and intelligent image processing. It utilizes algorithms like contour feature matching, object detection and positioning, region selection, edge extraction, and fuzzy logic to achieve high-efficiency and high-precision parameter measurement of shaft parts through artificial intelligence, making the shaft parameter measurement process simple, efficient, and precise. This system meets the needs of industrial bearings and large-volume inspection, improves product quality, ensures continuous long-term operation with consistent inspection standards, and completely eliminates misjudgments caused by human eye fatigue. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140098713/01_f9c5d1bfd65122de9b8b43cefac7dd96.png) ##### Customer Requirements Connect to industrial cameras, support mul --- ## [Nvidia + AI Camera] Coating Vision Inspection Solution Focused on Enhancing Lithium-Ion Battery Quality Control Standards - URL: https://intl.sienovo.cn/blog/140092682 - Date: 2024-07-01 - Tags: #AI, #DigitalCamera, #VisionInspection The quality of lithium-ion battery cells is crucial across various manufacturing sectors, especially in industries like new energy vehicles and high-end consumer electronics. Products in these sectors heavily rely on lithium-ion batteries for continuous, stable power supply. High-quality lithium-ion battery cells not only enhance product performance and user experience but also ensure operational safety. Therefore, guaranteeing the quality of lithium-ion battery cells is essential for ensuring product competitiveness, meeting market demands, and safeguarding consumer safety. **Key Steps in Lithium-Ion Battery Manufacturing** The coating process using slurry is a critical step in lithium-ion battery manufacturing, and its quality directly impacts the overall performance of the battery cell. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140092682/01_aeb9c4b0551e32aa5c92dc72755acbc8.jpeg) **Multiple Challenges in Coating Inspection** Firstly, with coating speeds in --- ## IEC61850 + RK3568 + FPGA + AD Multi-channel Synchronous Data Acquisition: A Fully Domestic Solution - URL: https://intl.sienovo.cn/blog/140047940 - Date: 2024-06-28 - Tags: #IEC61850, #RK3568, #FPGA IEC61850 is a communication protocol used in power automation systems, defining standardized communication and data models to support data exchange and interoperability between devices and systems. The protocol is widely applied in power system automation and digital transformation, especially in smart grids and distributed energy resource management. Its main features include standardization, flexibility, scalability, efficiency, and security. IEC61850 protocol communication solutions have been implemented based on various processor platforms, reducing development difficulty and R&D time. What is the IEC61850 Protocol? IEC61850 is a communication protocol used for data exchange and control in power automation systems. It defines a standardized communication and data model to support data exchange and interoperability between devices and systems. The IEC61850 protocol is widely applied in power system automation and digital transformation, particularly in smart grids and distribute --- ## Nvidia Jetson Orin/RK3588 + AI Bio-inspired Event Camera - URL: https://intl.sienovo.cn/blog/140035288 - Date: 2024-06-28 - Tags: #DigitalCamera **EVS Event Camera** Speed, performance, efficiency, and safety, bringing new heights to autonomous driving, automation, and high-speed motion. Featuring the SONY IMX646 EVS image sensor, based on PROPHESEE METAVISION technology. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140035288/01_8b2300e34bc5008e8ab86818f1f79f2b.gif) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140035288/02_4fee6869b937fb9e677c278c10884794.gif) **High Speed, 120dB High Dynamic Range** Achieving high speed and high temporal resolution. The concept of frame rate is now obsolete. It fully leverages events, which are distinct from frames, to reveal the invisible hidden within ultra-high-speed and transient dynamic scenes. **Product Advantages** 1 **Speed** 800us latency output at 1K lux, achieving high speed and high temporal resolution. The concept of frame rate is now obsolete. It fully leverages events, which are distinct from frames, to reveal the invisible hidden with --- ## Nvidia Jetson/RK3588+AI Binocular Stereo Camera, Suitable for Various Robotic Lawnmowers, Robot Vacuums, AGVs, and Other Applications - URL: https://intl.sienovo.cn/blog/140034564 - Date: 2024-06-28 - Tags: #DigitalCamera Binocular stereo vision is based on the principle of parallax, acquiring images of an object from different positions using imaging devices, matching the positional offsets of corresponding points to obtain disparity data, and then calculating the object's spatial three-dimensional information. We offer a high-image-quality binocular stereo camera, featuring advantages such as high resolution, low power consumption, and long range, making it suitable for various applications like robotic lawnmowers, robot vacuums, and AGVs. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140034564/01_5aa0f47a26d44bfaa374ae617bf56c19.png) This camera module is a depth camera that performs 3D imaging based on active binocular structured light. It consists of two IR image sensors, one RGB image sensor, one infrared speckle projector, and one IMU, making it suitable for applications such as obstacle avoidance and navigation in robots, AGVs, AMRs, and drones. Resolution 1280H*800V Frame Ra --- ## RK3588-based GMSL, FPDLink, VByone, and MIPI Camera Modules for Automotive, Robotics & Industrial Image Recognition - URL: https://intl.sienovo.cn/blog/140033842 - Date: 2024-06-28 - Tags: #Robotics, #CameraModule, #VehicleCamera **Robotics & Industrial Cameras** For robotic vision and industrial inspection vision, Xinmai independently develops and produces various camera modules such as GMSL, FPDLink, VByone, and MIPI, offering multiple field-of-view angles and lenses for different application scenarios. With an experienced team of image algorithm and ISP experts, we are capable of software driver layer development, ISP algorithm development, FPGA algorithm integration, and ISP image tuning for various scenarios adapting to different SOC platforms, providing customers with the highest quality imaging products and services. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140033842/01_951ef9fa5d654efd841201d3652d3c6b.png) GMSL is a high-speed serial interface introduced by Maxim, suitable for transmitting video, audio, and control signals, with a range of 15m or more when using 50Ω coaxial cable or 100Ω shielded twisted pair (STP) cable. Maxim's solutions are divided into GMSL, GMSL2, and GMSL3. --- ## Nvidia Jetson Orin/Nano + Smart Cockpit Camera for Automotive AI Vision - URL: https://intl.sienovo.cn/blog/140032841 - Date: 2024-06-28 - Tags: #AI, #ImageProcessing Smart cockpit systems include Driver Monitoring System (DMS) and Occupant Monitoring System (OMS). By installing cameras inside the vehicle, these systems perceive driver and passenger behavior as well as in-cabin conditions. DMS cameras enable functions such as driver fatigue monitoring, driver attention monitoring, dangerous driving behavior detection, and driver identification. OMS cameras can detect occupant-related data within the cockpit to further enhance safety. The in-cabin behavior recognition task aims to identify the behaviors of drivers and passengers within the vehicle cockpit, providing technical support to improve the driving and riding experience, thereby offering drivers and passengers a better experience and safer travel. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140032841/01_937b972cb9ee424eb3af63a92d5a156e.png) Our smart cockpit cameras utilize high-dynamic range (HDR) automotive-grade image sensors, paired with mainstream serial transmission --- ## CODESYS+EtherCAT+X86/ARM Hardware Platform: The Standard for High-Performance Motion Control, Customizable - URL: https://intl.sienovo.cn/blog/140017151 - Date: 2024-06-27 - Tags: #codesys, #canopen, #softmotion, #ethercat Supported Hardware Standards and Custom Platforms: X86: INTEL ARM: RK3568/RK3588/TI/NXP/Raspberry Pi/Allwinner T3/A40i, etc. A while ago, I shared about Schneider Electric's first EtherCAT-bus-enabled motion controller developed with CODESYS, the CODESYS+EtherCAT+X86 hardware platform: the standard for high-performance motion control. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140017151/01_5a6674d4a46859983510963fbfd73e80.png) My first encounter with CODESYS was over a decade ago when I used Beckhoff controllers. Later, around 2015, I gradually came across some domestic controllers developed with CODESYS. To be honest, at that time, there weren't many stable domestic controllers based on the CODESYS platform available. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140017151/02_5799a6965d3b23e0d99b316ba30b45eb.png) In the past two years, motion controllers based on the CODESYS+EtherCAT+X86 hardware platform have been emerging like mushrooms a --- ## HarmonyOS Smart Surveillance Solution: Comprising AI Vision Box, Network Cameras, Management Backend, Mobile App, NVR, and More - URL: https://intl.sienovo.cn/blog/140017014 - Date: 2024-06-27 - Tags: #harmonyos, #Huawei **Solution Architecture** The overall technical architecture consists of an AI Vision Box, network cameras, a management backend, a mobile app, an NVR, and other components, providing a complete closed-loop solution from front-end intelligent monitoring to back-end data processing. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140017014/01_937b0fec734a44996bd969f6bd281a87.png) **Solution Value** **01/Reduced Labor Costs** ① AI algorithms perform real-time intelligent detection of surveillance content with high accuracy, effectively reducing errors and omissions, eliminating the need for multiple manual guards. ② Automatic alarms are triggered upon detection of abnormal states, with real-time upload of alarm information, effectively reducing the workload of inspection personnel. ③ Automatic analysis of surveillance content, self-tagging, and cloud storage of effective surveillance information effectively reduce the workload for surveillance queries. **02/Enhanc --- ## 【Nvidia+智能相机】NVIDIA Orin/Nano Edge High Compute Power + High Dynamic Range 4-Lane CSI-2 Camera for Machine Vision, Industrial Inspection, and Other Scenarios - URL: https://intl.sienovo.cn/blog/140014935 - Date: 2024-06-27 - Tags: #DigitalCamera In the era of intelligence, various imaging and vision technologies are playing an increasingly vital role in autonomous driving, industrial automation, robotics, and the Internet of Things. They are also key drivers for recognition and perception systems, and for vision-based artificial intelligence. As a technology-driven innovation company focused on imaging and vision technologies, specializing in the R&D and application of imaging products and vision solutions, the company recently launched a 120dB high dynamic range 4-lane CSI-2 MIPI camera based on NVIDIA Jetson Orin, suitable for applications such as machine vision and industrial inspection. **High Dynamic Range 4-Lane CSI-2 MIPI Camera** The camera is a high dynamic range MIPI camera independently developed by Xinmai, utilizing a SONY IMX390 RGGB image sensor with a 1/2.7-inch sensor and 3.0 µm pixel size. This camera achieves a dynamic range greater than 120dB, effortlessly capturing stable, high-detail images even in sce --- ## Empowering Autonomous Driving: NVIDIA DRIVE Orin Platform with 16-Channel Digital Coaxial GMSL2 Camera Module Solution - URL: https://intl.sienovo.cn/blog/140008978 - Date: 2024-06-27 - Tags: #FPGADev, #AI, #ImageProcessing Recently, a series of independently developed GMSL2 camera modules have been successfully adapted to the NVIDIA DRIVE AGX Orin platform, offering developers camera solutions with long-distance transmission, high data rates, and strong anti-interference capabilities. A technology innovation company specializing in imaging and vision recently officially released a series of camera products compatible with the NVIDIA DRIVE AGX Orin platform. These independently developed digital coaxial GMSL2 camera modules are designed to meet the high-quality imaging requirements of intelligent vehicles. Currently, 11 camera models compatible with the NVIDIA DRIVE AGX Orin platform have been launched. These products incorporate image sensors from various manufacturers such as ON Semiconductor, Sony, and OmniVision, offering resolutions from 2 to 8 megapixels. They can output YUV/RAW data formats and support features like High Dynamic Range (HDR) and LED flicker mitigation. These camera products feat --- ## FPDLink III Automotive Camera Solution Based on TI AM62A + FPGA - URL: https://intl.sienovo.cn/blog/140008814 - Date: 2024-06-27 - Tags: #AI As a technology innovation enterprise focused on imaging and vision technology, and an ecosystem partner of global leading semiconductor company Texas Instruments (TI), Xinmai recently launched a compatible 2-megapixel to 3-megapixel FPDLink III smart camera solution based on the TI AM62A kit. FPDLink III Camera FPDLink III is a high-speed serial interface standard introduced by TI, used to connect image sensors and processors. It supports high-resolution and high-frame-rate image transmission. Xinmai's independently developed FPDLink camera can transmit uncompressed video, control signals, and power over a single low-latency cable. It supports full 1080p, 2k, and 3k HD displays, as well as device-level HDCP keys, while also providing adaptive equalization to compensate for cable aging and temperature variations. ![20231104](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140008814/01_dabe96019a5ace005507999a8331792a.jpeg) This time, FPDLink III cameras were launched base --- ## Fully Domestically Produced Phytium + FPGA Architecture, Supporting B-code, 12 Ethernet Ports, and Multi-Serial Power Communication Management Solution - URL: https://intl.sienovo.cn/blog/140008402 - Date: 2024-06-27 - Tags: #FPGADev GMSL Camera ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/140008402/01_05469d96cd3acf501b5be7e1fa5be9e2.png) GMSL is a high-speed serial interface introduced by Maxim, suitable for transmitting video, audio, and control signals over distances of 15m or more using 50Ω coaxial cables or 100Ω shielded twisted-pair (STP) cables. Maxim's solutions are categorized into GMSL, GMSL2, and GMSL3. GMSL2 is compatible with GMSL (first generation), allowing transceivers to be freely paired in Maxim's Camera SerDes solutions. The new GMSL3 standard (12 Gbit/s) is ADI's third-generation gigabit multimedia serial link. With this interface, image sensors can operate under the full MIPI CSI-2/D-PHY v1.2 specification (4 lanes, 2.5 Gbps each), enabling vision systems to transmit uncompressed, smooth video streams at up to 15MP@36fps or 4K@60fps over a single coaxial cable (PoC), thereby achieving smooth and clear sensor fusion, real-time imaging, or stereo 3D imaging. Taking ADAS camera --- ## RK3568-based In-Vehicle Computers Empower Japanese Bus Company to Efficiently Deploy Bus Arrival System Project - URL: https://intl.sienovo.cn/blog/139994697 - Date: 2024-06-26 - Tags: #Computer ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139994697/01_fc0a70f784171cf08cd823ae4a57cca1.jpeg) Ubiquitous Internet of Things (IoT) technology has permeated every corner of human life. For example, its application is perfectly demonstrated in the buses we take for daily commutes! It connects the in-vehicle computer network on buses with central control room servers to monitor and manage bus routes in real-time. At the same time, it can share data with digital signboards at various bus stops, providing waiting passengers with real-time bus arrival times and announcements. These systematic applications not only significantly improve bus operational efficiency but also enhance passenger safety and comfort. **Customer Background:** A city in Japan, known for its rich historical sites and architecture, attracts a large number of domestic and international tourists. To facilitate travel for both tourists and residents, providing reliable transportation service quality --- ## X86+FPGA, NXP+FPGA: The Rugged Choice for Industrial Control, Enabling New Transformations in Smart Rail Transit with CPCI/VPX - URL: https://intl.sienovo.cn/blog/139867853 - Date: 2024-06-21 - Tags: #Networking, #RailTransit Industrial PCs face opportunities in the current era, but also many challenges. In the rail transit sector, industrial PCs must possess high reliability and stability, capable of long-term, fault-free operation in complex and harsh working environments. They need to meet stringent real-time and response performance requirements, ensuring quick and accurate processing of sensor signals and control commands. **Reality and Challenges** High-speed rail transit applications demand a higher-performance, more reliable computing platform. This platform must be able to withstand high-intensity vibration environments, be easily expandable, and have a shorter Mean Time To Repair (MTTR). Traditional IPCs cannot meet these demanding application environments. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139867853/01_cd4ff0367df29be86e59371188f0096a.png) **"Ultra-High Performance, Super Ruggedized"** The 3U CPCI-Serial product series encompasses blade motherboards, backplanes, p --- ## Managed Board-Type Industrial Ethernet Switch for Rail Transit Applications - URL: https://intl.sienovo.cn/blog/139867813 - Date: 2024-06-21 - Tags: #Networking, #RailSwitch ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139867813/01_c0635726ec2a7329edacda264bcb3ea2.jpeg) This is a managed CompactPCI board-type redundant ring network switch. The front panel features six 10/100/1000Base-T(X) M12 interfaces. The rear CPCI interface provides eight 10/100/1000Base-T(X) Ethernet interfaces. It is a rugged switch specifically designed to meet the EN50155 standard requirements for the rail transit industry. It also possesses the following features: ● Supports 2-wire Ethernet distance extension ports, saving cabling costs. ● Media Redundancy Protocol (MRP) allows switches in a ring network to recover quickly upon signal failure, achieving faster recovery times than Spanning Tree Protocol networks. ● Provides advanced IP-based bandwidth management: Users can now set the maximum bandwidth for each IP device. When using IP cameras and NVRs, bandwidth management can allocate greater bandwidth to them. ● Supports application-level QoS: Application-l --- ## NXP LS1046 + FPGA Series CPCI Architecture Board for Rail Transit - URL: https://intl.sienovo.cn/blog/139867675 - Date: 2024-06-21 - Tags: #AI, #FPGADev, #RailTransit This CPCI architecture rail transit board, based on the NXP LS1046 series, is a highly reliable, fanless CPCI architecture board. It utilizes the NXP LS1046A system platform as its CPU, supporting operating systems such as embedded Linux, standard Ubuntu Linux, and 凝思. Designed to meet rail transit EMC and wide temperature range standards, it features multiple onboard M12 high-speed Ethernet interfaces, making it suitable for rail transit and other fields. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139867675/01_cc03e757e90826381a7afd3b8b4cfcf8.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139867675/02_aeeaff10a661b633f6e00c81a9659bf3.png) Key Features ◆ Based on NXP's LS1046A processor, an ARM Cortex-A72 64-bit quad-core, with an entirely fanless board design ◆ Supports 4 to 6 2.5G M12 Ethernet interfaces; features onboard memory, NAND Flash or Nor Flash, IRIG-B, etc. ◆ Supports operation in wide temperature (-40℃ ~ 80℃), high humidity, high h --- ## FPGA+Nvidia Orin NX+AI Heterogeneous Video and Image Processing Development Platform: Applications in High-End Medical and Industrial Inspection, Supporting Customization and Localization - URL: https://intl.sienovo.cn/blog/139863645 - Date: 2024-06-21 - Tags: #FPGADev, #ImageProcessing, #AI An FPGA+GPU heterogeneous architecture video and image processing development platform, it combines the powerful capabilities of AMD Zynq UltraScale+ MPSoC (FPGA) and NVIDIA Jetson Orin NX (GPU), and is applicable to industries with stringent requirements for image precision and real-time performance. **Zynq UltraScale+ MPSoC XCZU19EG** **16 GB** **PL-side DDR4** **8GB** **PS-side DDR4** **128MB** **QSPI Flash** **32GB** **eMMC Flash** **1143K** **Logic Cells** **1045K** **Flip-Flops** **NVIDIA Jetson ORIN** **70T/100T** **AI Performance** **765/918MHz** **Max GPU Frequency** **6/8 Cores** **Arm Cortex-A78AE** **2GHz** **Max CPU Frequency** **32x 1024 Cores** **Tensor Cores, NVIDIA Ampere Architecture** **Rich Interface Resources** **2x** **100G Optical Fiber** **8x** **12G-SDI** **……** **4x** **HDMI 2.1 Input/Output** **FMC HPC Interface** **Medical Endoscopy and Surgical Robotics Solutions** In applications for medical endoscopy and surgical roboti --- ## RK3588J + Electric Power HarmonyOS + Electric Power Certified AI Edge Computing Solution - URL: https://intl.sienovo.cn/blog/139856755 - Date: 2024-06-21 - Tags: #AI, #harmonyos, #Huawei, #PowerHarmonyOS Electric Power HarmonyOS is China's first electric power IoT operating system jointly released by China Southern Power Grid (CSG) and the OpenAtom Open Source Foundation. **China's First Electric Power HarmonyOS Deployed** Previously, domestic IoT operating systems exhibited a "fragmented" characteristic, with numerous types of IoT operating systems, meaning inconsistent protocols, specifications, and security. There were also issues such as single-business focus, single-scenario application, and lack of multi-service support. Du Shaohui, Manager of the Hardware R&D Department at CSG Digital Grid Technology (Guangdong) Co., Ltd., stated: "To enable freer connections between devices and achieve the Internet of Everything, a unified system and unified standards are required." Against this backdrop, China Southern Power Grid and the OpenAtom Open Source Foundation jointly released "DianHong," an open-source operating system targeting edge computing scenarios and IoT terminal embedded --- ## 【FPGA + Nvidia/Sophon GPU + AI】Autonomous Driving Multi-core Heterogeneous Implementation: 16-channel Automotive Camera Real-time AI Analysis Solution - URL: https://intl.sienovo.cn/blog/139854589 - Date: 2024-06-21 - Tags: #FPGADev, #AI Designed based on Xilinx ZYNQ Ultrascale+ MPSoC series FPGA chips, this solution is applied in autonomous driving fields such as unmanned driving, low-speed special vehicles, data acquisition vehicles, and in-vehicle simulation testing systems. Autonomous Driving: 16-channel Automotive Camera PCIe Capture Card Solution. #### * ##### ·16-channel Cameras Supports up to 16 channels of GMSL1/2 camera input * ##### ·8MP Cameras Supports up to 8 channels of 8MP resolution cameras * ##### ·PCIe 3.0 Bus Supports PCIe 3.0 x8, x4, x1 modes, compatible with PCIe 2.0, with a maximum theoretical bandwidth of 8GB/s * ##### ·Multi-platform Support Intel CPU platforms, AMD CPU platforms, NVIDIA Jetson platforms, Sophon BM1684X platforms ![_K4A9650.jpg](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139854589/06_fce11547e12b15bab65861a5cdd2ad30.jpeg) ![车载摄像头采集卡.png](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/1 --- ## 【STM32+FPGA】Advanced Computing Power + Robust Security + Edge AI: 64-bit STM32MP2 Focuses on Industrial 4.0 Applications - URL: https://intl.sienovo.cn/blog/139854068 - Date: 2024-06-21 - Tags: #stm32, #FPGADev, #Security The degree of digitalization and intelligence in industrial applications is an important criterion for measuring new quality productive forces. STM32's latest generation 64-bit microprocessor, the STM32MP2, with its advanced computing power, rich interfaces, and high security, empowers high-performance and highly interconnected Industrial 4.0 applications. **Four Key Features of STM32MP2 Empowering Industrial 4.0 Applications** The first product in the STM32MP2 series, the STM32MP25, is now in mass production. It features a junction temperature range of -40 to 125 degrees Celsius, supports 10 years of 100% uptime, and, like other STM32 products, offers a 10-year rolling supply guarantee. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139854068/01_22fa71e472852cb0e549a56478de4a3d.png) ▲ Diagram: STM32MP25 Block Diagram The STM32MP2 features a heterogeneous architecture and excellent performance, robust security features, advanced edge AI capabilities and multimedia --- ## 【RK3588/Sophon/Nvidia Smart Box】AI Algorithms Applied to Intelligent Monitoring of China National Biotec Group Vaccine Production, Empowering Production Safety and Enhancing Quality Control - URL: https://intl.sienovo.cn/blog/139790228 - Date: 2024-06-19 - Tags: #AI, #Security **Frequent Food and Drug Quality Incidents Due to Operational Errors** **Computer Vision Detection Technology Offers New Approaches to Regulation** In recent years, various food and drug quality incidents caused by human operational errors have occurred frequently. For example, an employee failing to perform a dual verification when retrieving raw materials and confirming weight led to "medication mix-ups"; an employee failing to sterilize raw milk according to production steps resulted in cheese contamination; and an employee mistakenly mixing up two vaccine raw material components led to 15 million doses of vaccine being scrapped. All these incidents caused severe and irreversible consequences. The requirements for environmental hygiene, process flow, and product quality in food and drug production are becoming increasingly stringent. As computer vision detection technology continues to mature, **it can not only detect product defects, packaging label information defects, etc., b --- ## 【RK3588/Sophon/Nvidia Smart Boxes】Tackling 'No Power, No Network' AI Algorithm Deployment to Ensure Safety at Daya Bay Quanmei Petrochemical Terminal Construction Site - URL: https://intl.sienovo.cn/blog/139785438 - Date: 2024-06-18 - Tags: #AI, #Security “Above the vast expanse of blue waves, a thousand-meter steel trestle bridge winds its way into the sea like a dragon emerging from water. Project builders on the steel trestle are working diligently, striving to accelerate Huizhou Daya Bay's development into a world-class green petrochemical base.” This is how Beijing Daily recently described the Quanmei Petrochemical Terminal construction site in Quanwan Port Area, Huizhou Port, Daya Bay. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139785438/01_13e592d8d7240f3bffeafc98182e6963.jpeg) △ Image source: Beijing Daily Quanmei Petrochemical is a wholly-owned subsidiary of ExxonMobil, the world's largest oil and gas producer. Reportedly, this terminal project will serve the high-volume inbound and outbound demands for bulk commodities and raw materials such as petroleum products and chemicals in the Daya Bay Petrochemical Zone. **With a large workforce, tight deadlines, and heavy tasks, how can the engineering constru --- ## 【RK3588/Sophon/Nvidia Smart Box】AI-powered Oversight: Regulating Parking, Fire Hazards, and Charging Irregularities at EV Charging Stations - URL: https://intl.sienovo.cn/blog/139785390 - Date: 2024-06-18 - Tags: #AI, #Automotive In recent years, China's new energy vehicle (NEV) industry has experienced rapid development, with its production ranking first globally for 8 consecutive years. According to data from the China Charging Alliance, as of June 2023, the number of NEVs in operation reached 16.2 million, and the cumulative number of charging infrastructure units nationwide was 6.652 million, with a vehicle-to-charger ratio of approximately 2.5:1. While the imbalance between NEV and charging pile supply and demand is the fundamental reason for the "difficulty in finding a charger," what if, after finally finding a charger, we discover a gasoline vehicle occupying the spot, or even an EV parked across multiple spots, or an EV that has finished charging but is slow to leave? Wouldn't you be tempted to file a complaint? Faced with the current situation of numerous complaints and low revenue at charging stations due to supply-demand imbalance and inadequate management, through in-depth on-site research and c --- ## RK3588/SOPHON/Nvidia Smart Boxes: Accelerating Shanxi Aluminum's Intelligent Transformation and Ensuring Safe, Stable Operation of Mining Conveyor Belts - URL: https://intl.sienovo.cn/blog/139785335 - Date: 2024-06-18 - Tags: #Security, #AI In recent years, frequent mining accidents have exposed numerous issues across traditional mining operations. With key coal-producing provinces across China successively issuing relevant policy documents, the pace of intelligent mine construction has accelerated. Upgrading conveyor belt transmission systems is a critical component of mine intelligence and a key direction for cost reduction and efficiency improvement. △ Policies on intelligent mining from various provinces Conveyor belt transmission systems face several industry-wide challenges. For example, low automation levels, inspection blind spots, and prolonged worker exposure to high-dust environments increase both safety and occupational health risks. To address these issues, a **"Smart Mining All-in-One Machine" has been developed based on SOPHON computing products, establishing a "Conveyor Belt Intelligent Video Monitoring System." This system has been deployed in Shanxi Aluminum’s intelligent transformation project, signi --- ## RK3588/Sophon/Nvidia Smart Box: "AI Smart Gas Station" – Safety as the Foundation, Empowering Precise Operations - URL: https://intl.sienovo.cn/blog/139785276 - Date: 2024-06-18 - Tags: #AI, #Security In September 2021, the Shandong Provincial Department of Emergency Management issued a notice regarding the "Provincial Work Plan for the Informatization Construction and Application of Hazardous Chemical Safety Production (2021-2022)," requiring the acceleration of informatization and intelligent construction and application for hazardous chemical safety production across the province, and the establishment and improvement of a provincial hazardous chemical safety production risk monitoring and early warning system. In 2022, **a strategic partnership was formed with NewLink**, dedicated to combining energy digitalization scenarios with computer vision algorithms. This partnership aims to create **energy digitalization industry + AI products and solutions** for scenarios such as gas stations, charging stations, and integrated energy ports under NewLink and NewLink Zhidian. Focusing on three major directions—safety management, precise operations, and employee service standards for ene --- ## AI Smart Box Drives Benchmark AI Applications in Waste-to-Energy! - URL: https://intl.sienovo.cn/blog/139785056 - Date: 2024-06-18 - Tags: #AI Waste incineration for power generation, as a new type of waste treatment method, converts waste into electrical energy, achieving resource reuse and becoming one of the important ways to achieve energy saving and environmental protection. To effectively implement its Environmental, Health, Safety, and Social Responsibility (EHSS) management system, Everbright Environment Energy, a renowned waste-to-energy investment operator, is committed to extensively leveraging technology to enhance the operational efficiency of all its plant systems. Following multi-stage discussions and project pilots, **multiple project companies under Everbright Environment Energy have reached a deep cooperation with Xinmai, jointly exploring new directions for AI-driven intelligent management in waste-to-energy plants.** **01** **Everbright Environment Energy** **Establishes the 'Halo Cloud Guardian' Smart Security System Management Platform** After multiple on-site inspections and demand assessments, a s --- ## AI Intelligent Box Empowers Sinosteel Tianyuan Equipment Factory to Upgrade Safety Protection - URL: https://intl.sienovo.cn/blog/139784997 - Date: 2024-06-18 - Tags: #AI, #Security, #BigData Sinosteel Anhui Tianyuan Technology Co., Ltd., established on March 27, 2002, is a listed company controlled by China Sinosteel Corporation, a central state-owned enterprise. Its main products include permanent magnet ferrite devices, NdFeB devices, trimanganese tetraoxide, strontium ferrite pre-sintered materials, and various magnetic separators. During Sinosteel Tianyuan's intelligent upgrade process, **a series of algorithms for factory safety management and control were adopted and custom-developed.** ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139784997/01_a76384d2404c27bdb10c0835e2db7e50.jpeg) △Sinosteel Tianyuan AI Algorithm Platform **Efficient Custom Development of New Algorithms** Steel equipment factories have vast areas, numerous heavy machinery, and complex environments. Operating personnel can easily be obscured, creating blind spots for safety monitoring. If only fixed cameras are used, they can suffer from perspective distortion, leading to misj --- ## 【Nvidia + AI Camera】Stereo Vision Camera for Robots - URL: https://intl.sienovo.cn/blog/139751276 - Date: 2024-06-17 - Tags: #AI, #Robotics, #DigitalCamera With the continuous development of artificial intelligence and robotics technology, stereo depth cameras, as crucial sensors, are being widely applied in various robotic systems. As indispensable perception devices for robots, their high-precision depth information provides robots with capabilities such as environmental perception, stereo vision, and pose recognition, enabling robots to achieve tasks like intelligent navigation, human-robot interaction, and object tracking. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139751276/01_7df15258a0dc0e95d6e3013881735950.png) **Stereo Vision Camera** Recently, leveraging its technical accumulation and product experience in high-quality AI imaging, the company has launched a series of stereo vision cameras applicable to robots. This product consists of two IR image sensors, one RGB image sensor, one infrared speckle projector, and one IMU, and is a 3D stereo camera supported by a USB3.0 interface. The stereo vision camera a --- ## [Nvidia+AI Automotive Camera] Ultra-Small 3-Megapixel Automotive Surround View Camera Solution - URL: https://intl.sienovo.cn/blog/139751180 - Date: 2024-06-17 - Tags: #VehicleComputer, #AI, #AudioVideo ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139751180/01_2bc8b4fba9b320478932da045a91802f.png) As a technology innovation company dedicated to imaging and vision technologies, we recently launched an ultra-small automotive surround view camera module based on ON Semiconductor's 3-megapixel AR0341AT image sensor. This module helps improve driving safety metrics, effectively addresses the demand for excellent HDR performance and image quality in high-speed autonomous driving, and reduces system development costs. **ON Semiconductor Ultra-Small AR0341AT Image Sensor** The AR0341AT is among the first products in ON Semiconductor's new Hyperlux image sensor series. It is equipped with second-generation Super Exposure pixel technology, featuring industry-leading 150 dB High Dynamic Range (HDR) and LED Flicker Mitigation (LFM) capabilities. This pixel technology eliminates the need for automatic exposure control operations, significantly reducing latency in critical aut --- ## All-Domestic AI HD Video Surveillance System for Urban Rail Transit Operations and Public Security - URL: https://intl.sienovo.cn/blog/139732062 - Date: 2024-06-17 - Tags: #AI, #VehicleAV, #VehicleComputer **Solution Overview** The Urban Rail Transit Operations and Public Security HD Video Surveillance System Solution addresses the security needs of both operational departments and public security agencies. It utilizes various front-end, video encoding/decoding, and control products from Huawei Vision, providing video surveillance services and intelligent applications through a unified platform. This meets the demands of rail transit operators for passenger organization and emergency command, as well as the needs of subway public security for real-time on-site images and evidence for case investigation. **Background and Challenges** With the development of China's economy and population growth, traffic conditions in major cities are deteriorating. Developing rail transit and building an intensive transportation network has become the direction for traffic development in China's large and medium-sized cities. National planning designates urban rail transit as a key investment area in --- ## [In-Vehicle Audio/Video AI Computer] Railway Video Surveillance System Solution - URL: https://intl.sienovo.cn/blog/139731748 - Date: 2024-06-17 - Tags: #AudioVideo, #AI **Solution Overview** The Railway Video Surveillance System Solution addresses the safety and operational assurance needs of the railway industry. In accordance with the technical specifications of China Railway Corporation, and based on the railway system's IP network, it adopts advanced video surveillance technology to build a complete digital, intelligent, and distributed integrated railway video surveillance system. This system achieves sharing of video network resources and information resources, meeting the video application requirements for various operations such as dispatch, rolling stock management, freight, passenger transport, locomotive maintenance, engineering, vehicle maintenance, public security, track protection, disaster prevention, traction power supply, emergency rescue, and emergency management. **Background and Challenges** In recent years, China's railway construction has entered a period of rapid development. To ensure the safe operation of railways, video s --- ## [In-vehicle Audio/Video PC] AI In-vehicle Terminal Application System Solution for Key Passenger and Hazardous Goods Vehicles - URL: https://intl.sienovo.cn/blog/139731666 - Date: 2024-06-17 - Tags: #VehicleAV, #VehicleComputer, #AI **Solution Overview** The In-vehicle Terminal Application System for Key Passenger and Hazardous Goods Vehicles addresses road traffic safety issues currently faced by such vehicles during operation. It utilizes an intelligent supervision system that integrates government regulatory platforms, enterprise intelligent supervision centers, in-vehicle terminals, and communication networks. Through the interconnection of these components, it achieves business management, data interaction, and sharing, providing powerful supervision and monitoring means for the "three excesses" (over-speeding, overloading, and excessive fatigue driving) during the transportation process of key passenger and hazardous goods vehicles. **Background and Challenges** With the continuous development of the national economy, road transport has always been a vital component of the transportation system. Currently, China faces a severe road traffic safety situation, with road traffic accidents and major accidents --- ## Onboard Audio/Video AI PC: All-Domestic Maritime Shipborne Video Surveillance System Solution - URL: https://intl.sienovo.cn/blog/139731560 - Date: 2024-06-17 - Tags: #VehicleAV The Maritime Shipborne Video Surveillance System Solution addresses the challenges of navigation safety and shipping regulation in China's rapidly developing inland, coastal, and ocean shipping sectors. It provides ship operators and government regulatory authorities with a comprehensive video surveillance system integrating video acquisition, storage, and playback/retrieval. This system monitors critical internal areas and the external environment of medium to large vessels during operation, and can be used for vessel navigation safety analysis, ensuring maritime safety, and meeting the needs of shipping development in the new era. **Background and Challenges** With the rapid development of China's social economy, shipping, as a convenient and low-cost mode of transport, is continuously increasing its share in the transportation industry structure. The vessel traffic volume in inland, coastal, and ocean shipping is growing steadily. Concurrently, with the public's pursuit of qualit --- ## Domestically Produced + AI Port Video Management and Monitoring System - URL: https://intl.sienovo.cn/blog/139653647 - Date: 2024-06-17 - Tags: #VehicleAV, #VehicleComputer The Port Video Management and Monitoring System addresses port operations, port area safety, and the regulatory requirements of superior authorities such as port authorities, customs, tax authorities, maritime affairs, border inspection, and public security. Utilizing modern information technology, it organically integrates terminal operation areas, anchorages, waterways, berths, container yards, gatehouses, warehouses, port perimeters, road surveillance, gate control, entrance/exit surveillance, and building surveillance. This creates a video management system with "unified encoding and decoding standards, unified networking protocols, unified control protocols, unified numbering rules, unified image annotation, and unified location identification." It integrates video and image resources from various sources and formats to achieve network-wide sharing of video and image information, meeting the 24-hour monitoring and evidence collection needs of various business units. **Background --- ## Fully Domestic + AI Bus Vehicle-Mounted Video Surveillance System Solution - URL: https://intl.sienovo.cn/blog/139653169 - Date: 2024-06-17 - Tags: #AudioVideo The bus vehicle-mounted video surveillance system is based on the iVMS-7200 Mobile Video Surveillance Management Platform. It connects to vehicle-mounted front-end devices via 3G/4G networks, enabling functions such as real-time monitoring, video playback, GIS map positioning, track playback, device status inquiry, and emergency alarms. Vehicle-mounted front-end devices include a Vehicle-mounted Hard Disk Video Recorder (referred to as Vehicle DVR or MDVR), vehicle-specific cameras, a vehicle-mounted LCD display, an alarm button and status display terminal, a full-duplex voice intercom box, a vehicle-specific fireproof storage box, and accompanying cables and wiring. The Vehicle DVR has built-in wireless network communication modules, as well as GPS and Beidou positioning modules. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139653169/01_27359e973284bd4f957e1e072d51eb4d.png) **Solution Advantages** **1) Fanless, Fully Enclosed Design** The casing of the Vehicle DV --- ## Fudan Micro FMQL20SM Fully Domestically Produced ARM+FPGA Core Board, Replacing Xilinx ZYNQ7020 Series - URL: https://intl.sienovo.cn/blog/139652986 - Date: 2024-06-13 - Tags: #FMSH The FMQL20SM core board is a fully domestically produced industrial core board. It is designed based on Fudan Micro FMQL20S400M heterogeneous multi-core SoC processor, which features a quad-core ARM Cortex-A7 (PS side) and FPGA programmable logic resources (PL side). The PS side clock speed is up to 1GHz. Core Board Introduction The FMQL20SM core board is a fully domestically produced industrial core board. It is designed based on Fudan Micro FMQL20S400M heterogeneous multi-core SoC processor, which features a quad-core ARM Cortex-A7 (PS side) and FPGA programmable logic resources (PL side). The PS side clock speed is up to 1GHz. All components of the core board, such as the CPU, RAM, ROM, power supply, crystal oscillator, and connectors, adopt domestically produced industrial-grade solutions, achieving a 100% localization rate. A localization rate certification report can also be provided. The core board exposes interfaces such as Gigabit Ethernet, SDIO, USB, CAN, UART, SPI, and I --- ## 【Onboard AI Audio/Video Computer】Intelligent Driving Monitoring System: AI Analysis and Monitoring Solutions for School Buses / Police Cars / Trucks / Tankers - URL: https://intl.sienovo.cn/blog/139645852 - Date: 2024-06-13 - Tags: #AI, #VehicleAV, #VehicleComputer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139645852/01_70f67dc8cadeb2fa426ec0754f0d9b05.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139645852/02_aa884d2965b1840767937f0a34dccb54.png) **School Bus Monitoring Solution** 1. Real-time video monitoring, school bus location inquiry, video playback, and route playback. 2. Preset school bus routes; generate an alarm if deviation occurs. 3. Preset school bus speed; generate an alarm if speeding occurs. 4. Preset student alighting detection, capture images and upload to the supervision center, preventing children from being trapped inside the vehicle. 5. Store data in the cloud via cloud storage, allowing users to access cloud data anytime, anywhere. Administrators can view vehicle videos, locations, student boarding/alighting status, etc., in real-time via a web browser. 6. Cloud data can be reported to the government monitoring center in real-time. 7. Automatically push student boarding/aligh --- ## In-vehicle AI Audio/Video Computer: HD Vehicle Camera, Vehicle PTZ Camera - URL: https://intl.sienovo.cn/blog/139645562 - Date: 2024-06-13 - Tags: #AI, #VehicleAV ＊ 1/3 SONY CMOS. AHD 1MP, 2MP optional ＊ Low-light, IR night vision function ＊ 2.8mm fixed lens (2.8/3.6/4/6/8mm lenses optional) ＊ Dedicated in-vehicle solution ＊ Vibration-resistant, IP66/67 waterproof, dustproof, explosion-proof design. ＊ Audio optional ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139645562/01_0f3507b6769891ca2bd724749719d040.png) **Vehicle IP Camera** ★1/3” Progressive scan CMOS image sensor ★Utilizes ROI, SVC video compression technology, high compression bit rate; ★High resolution (1.3 megapixels), supports dual stream; ★Supports two-way audio, built-in microphone and audio output optional; ★Supports IP66 waterproof rating; ★Supports various optional lenses, day/night monitoring; ★Supports optimized wide dynamic range (WDR) video effects and standard universal Onvif protocol ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139645562/02_3e38b72562e632a132cf54f81834c466.png) **Vehicle PTZ Camera** 1. High-strength alumi --- ## [In-vehicle AI Audio/Video Computer] In-vehicle Management Software, Route Playback, Remote Video Playback, Location Tracking - URL: https://intl.sienovo.cn/blog/139645196 - Date: 2024-06-13 - Tags: #AI ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139645196/01_2787abd76502867c18a3647c3e371898.png) **Key Features**: ● 3/4G real-time video surveillance, smooth and fast ● GPS vehicle/personnel map positioning ● CMSV6 platform, information-based management philosophy ● Route playback, remote video playback ● Comprehensive features including fuel consumption settings, 3G data limit, etc. ● Image snapshot ● Comprehensive reporting ● Driver behavior analysis **Open Integration, Supports Rapid Docking with Customer Platforms**: **Middleware**: Middleware supports B/S mode and C/S mode. Users can invoke the middleware as a standard component based on business requirements, quickly integrating it into their own systems to build industry-oriented application systems. **Open API**: Provides a unified HTTP interface call and interaction specification for third-party applications to access platform services. **Fully Compatible with PC, Mobile, and Web Clients**: The m --- ## 2-Megapixel Mini All-in-One In-vehicle AI Audio/Video Computer - URL: https://intl.sienovo.cn/blog/139645037 - Date: 2024-06-13 - Tags: #AI, #Computer, #VehicleComputer Fleet operators and commercial vehicle managers face a persistent challenge: deploying reliable, tamper-resistant surveillance and telematics hardware in cars, vans, and trucks without expensive installation downtime or fragile wiring setups. Sienovo's 2-megapixel mini all-in-one in-vehicle AI audio/video computer addresses that problem with an integrated design that combines HD recording, real-time remote preview, multi-constellation connectivity, and event-driven alarm upload into a single compact unit. This post walks through the key hardware capabilities and explains why each design choice matters for real-world fleet deployments. ## Installation Without Drilling Traditional vehicle DVRs require bracket mounting, dash-panel cutouts, or dedicated wiring harnesses — work that typically demands a technician and takes an hour or more per vehicle. This unit ships ready for windshield-mount deployment using industrial-grade 3M adhesive, placing the device directly on the front glass wh --- ## [In-Vehicle Audio/Video Computer] Embedded AI Analysis In-Vehicle DVR, Supports 8-Channel 1080P - URL: https://intl.sienovo.cn/blog/139643362 - Date: 2024-06-13 - Tags: #AudioVideo, #Computer ****Product Features**** Adopts H.265 & H.264 codecs, saving storage space and transmission bandwidth; High Resolution: Supports 8-channel 1080P\*15FPS / 4-channel 1080P\*30FPS, 720P, D1 and other encoding/decoding; Supports 1 SATA hard drive, easy to access, meeting large-capacity storage requirements; Supports 1 SD card for recording and 1 USB interface; Supports 1 SIM card for dial-up internet access; Supports 6-channel IO alarm input, supports RS232, RS485 functions; Optional support for WIFI, 4G, GPS and other functions; Supports mobile APP, client software, and platform software for video preview and parameter configuration; Proprietary file system, improving disk read/write efficiency and recording stability; Built-in AI intelligent algorithms, supporting ADAS, DMS, BSD detection; Industrial-grade appearance design, aluminum alloy casing, lightweight and robust product with good heat dissipation; ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139643362 --- ## In-Vehicle Audio/Video PC: Dual SD Card Dashcam with AI Recognition and Analysis, Supporting 4-Channel AHD 1080p HD Input - URL: https://intl.sienovo.cn/blog/139643046 - Date: 2024-06-13 - Tags: #Computer, #VehicleAV ****I. Product Appearance**** Patented design, aluminum alloy material for good heat dissipation, compact, and easy to install; plastic front panel, aesthetic, simple, and elegant, with an independent lock. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139643046/01_74afbfc431bb45bce655ad05ae96c4cf.png) ****II. Product Features**** Supports 4-channel AHD HD input at 1080P*30FPS, 720P, D1, CIF resolutions, etc.; supports connecting IPC via network port; Video files use H.265 & H.264 codecs, saving storage space and transmission bandwidth; Supports 4-channel audio input, 1-channel audio output; 1-channel voice intercom; external speaker support; Supports 1-channel CVBS video output (optional 1-channel VGA video output); Supports manual or scheduled recording to 2 SD cards, with a maximum capacity of 512GB; Supports 1 USB 2.0 interface for exporting video files and mouse operation; Supports 1 SIM card for 4G communication and internet access; supports Beidou 3 / G --- ## Vehicle-mounted MDVR (Main Unit) for Multi-channel Video Surveillance Systems in Buses, Trains, and Other Applications - URL: https://intl.sienovo.cn/blog/139642333 - Date: 2024-06-13 - Tags: #DevOps ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139642333/01_03175b3cf945dbb6b3c53f5d7b62d977.png) The vehicle-mounted MDVR (main unit) is a cost-effective and highly scalable device specifically developed for multi-channel video surveillance and remote monitoring applications in buses, trains, and similar vehicles. It is developed using a high-speed processor and an embedded Linux platform, integrating the most advanced H.265 video compression/decompression technology in the IT industry. Utilizing ****dual hard drives**** + SD card (for mirror recording) as storage media, the MDVR can achieve audio/video recording with 8-channel analog HD video input + 4-channel digital HD IPC input formats, as well as vehicle driving information recording functions. It features ****dual 4G/5G modules**** and ****dual supercapacitors****. The MDVR product boasts a concise design, excellent vibration resistance, flexible and convenient installation, powerful functions, and high reliabili --- ## 4/8-Channel HDD/SSD 1080P Mobile NVR, HD Mobile Video Recorder (8-Channel 1080P DVR) - URL: https://intl.sienovo.cn/blog/139641992 - Date: 2024-06-13 - Tags: #AudioVideo, #VehicleComputer, #VehicleRecorder **4/8-Channel HDD/SSD 1080P Mobile NVR** **Key Product Features:** - Supports 4/8 channels of real-time HD digital 1080P recording. - Hard disk data recording (supports up to 2TB). - Supports GPS global positioning, optional module. - Supports high-speed Wi-Fi automatic download function, optional module. - Built-in 3G/4G module for real-time preview and remote management, optional module. - Standard VGA output. - Built-in acceleration sensor. - Built-in supercapacitor, etc. **Functional Features:** * Built-in HiSilicon high-performance image processing chip, H.264 encoding, high compression ratio, clear image. * Supports 8 channels of digital megapixel HD / analog standard definition video and audio input, 1 channel of synchronized video and audio output, 1 channel of VGA output. * Supports 8 channels of 1080P digital HD real-time local recording. **Power Supply:** * Professional vehicle power supply design with 8-32V DC wide voltage input. * Multiple protection circu --- ## Maritime Law Enforcement Vessel Video Surveillance System Solution - URL: https://intl.sienovo.cn/blog/139641928 - Date: 2024-06-13 - Tags: #AudioVideo The Maritime Law Enforcement Vessel Video Surveillance System Solution addresses the operational needs of maritime law enforcement evidence collection and emergency command. It provides a comprehensive video surveillance system for law enforcement vessels, integrating high-definition video surveillance technology, remote wireless transmission technology, and portable individual device technology. This system not only enhances maritime law enforcement capabilities, creates a deterrent effect, and raises awareness among vessel operators for compliant navigation, thereby reducing illegal vessel activities and ensuring safety of life and property on water, but also improves the public image of maritime law enforcement teams, establishing an efficient and orderly maritime supervision and enforcement mechanism. **Background and Challenges** In recent years, with socio-economic development, some "unlawful elements" engage in illegal activities such as smuggling to achieve "quick riches." A --- ## 【In-vehicle AI Audio/Video Computer】4/8 Channel AHD 2MP Vehicle PC SD Card DVR - URL: https://intl.sienovo.cn/blog/139641863 - Date: 2024-06-13 - Tags: #AudioVideo Modern fleet operations demand reliable, high-definition video evidence from every angle of a vehicle — whether for incident reconstruction, driver coaching, or regulatory compliance. This post covers a purpose-built in-vehicle AI audio/video computer that supports 4 or 8 channels of AHD 2MP recording, designed for harsh mobile environments where power reliability, compact storage, and remote connectivity all matter simultaneously. ## AHD Video Recording: Why It Matters for Vehicle DVRs Analog High Definition (AHD) is a coaxial-based video transmission standard that delivers 1080P resolution over the same RG59 cable infrastructure used in legacy CCTV systems. For vehicle installations this is a practical advantage: coax is mechanically robust, tolerates the vibration and temperature swings of a moving platform, and eliminates the IP-camera complexity of managed Ethernet switches inside a vehicle cabin. Each of the four (or eight) channels on this unit records at full HD 1080P in real --- ## 【Vehicle PC】4/8-Channel AHD 1.3 Megapixel Mobile Digital Video Recorder - URL: https://intl.sienovo.cn/blog/139641815 - Date: 2024-06-13 - Tags: #VehicleAV Fleet managers and system integrators evaluating in-vehicle recording solutions frequently face the same trade-off: consumer dashcams are cheap but lack the channel count, storage depth, and remote-management capabilities that commercial vehicle fleets require. The 4/8-channel AHD 1.3-megapixel Mobile DVR described here is purpose-built for that gap — offering multi-camera HD recording, cellular connectivity, GPS tracking, and rugged hard-drive storage in a single vehicle-mounted unit. ## AHD Video: Why It Matters for Fleet Cameras Analog High Definition (AHD) is a coax-based video standard that carries HD signals over the same RG59 cable used for legacy analog CCTV. In a vehicle environment this matters enormously: coax is mechanically robust, immune to the noise and impedance issues that plague long USB or IP cable runs, and does not require per-camera encoding hardware. The DVR receives raw AHD signals from up to 4 or 8 cameras simultaneously and handles all encoding internally, s --- ## [In-vehicle AI Audio/Video PC] 4-Channel AHD 1.3 Megapixel Dual-Card Vehicle DVR - URL: https://intl.sienovo.cn/blog/139641744 - Date: 2024-06-13 - Tags: #ffmpeg, #AI, #SpeechRecognition ## In-vehicle AI Audio/Video PC: 4-Channel AHD 1.3 Megapixel Dual-Card Vehicle DVR In this article, we will explore the key product features and technical specifications of the 4-Channel AHD 1.3 Megapixel Dual-Card Vehicle DVR, a cutting-edge in-vehicle AI audio/video PC designed for real-time video recording and remote management. This device supports advanced features such as GPS global positioning, high-speed Wi-Fi automatic download, and built-in 3/4G modules for real-time preview and remote management. ### Key Product Features - **4-channel real-time HD AHD 720P recording**: The device supports simultaneous recording of four channels of high-definition AHD 720P video, making it ideal for applications that require high-quality video evidence. - **SD card data recording**: The device allows for data recording on two high-capacity SD cards, with a maximum storage capacity of 256GB per card. This ensures that recorded video data can be stored securely and efficiently. - **GPS globa --- ## Plug-in Instrument Module: Data Logging Module - URL: https://intl.sienovo.cn/blog/139566794 - Date: 2024-06-09 - Tags: #DataAcquisition, #FPGADev ## Plug-in Instrument Module: Data Logging Module In this article, we will explore the features and specifications of a plug-in instrument module designed for data logging applications. This module is particularly useful for engineers and researchers who require precise measurements and real-time data acquisition capabilities. ### Key Features - **32-bit Resolution**: The module boasts a high resolution of 32 bits, allowing for extremely precise measurements. This is crucial in applications where small changes in voltage or current need to be detected. - **250 kSPS Sampling Rate**: With a sampling rate of 250 kSPS (kilo-samples per second), the module can capture data quickly and accurately, making it suitable for dynamic systems where rapid changes occur. - **Simultaneous and Continuous Recording**: The module can record two voltage input channels simultaneously and continuously. This feature is essential for applications that require the monitoring of multiple signals at the sa --- ## Plug-in Instrument Module: Audio Analysis Module (Plug-in) - URL: https://intl.sienovo.cn/blog/139566784 - Date: 2024-06-09 - Tags: #AudioVideo, #DataAcquisition, #FPGADev • 24-bit Resolution • 192 kHz Sampling Rate • Supports input/output of various analog audio signals ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139566784/01_b72fa9520781defb10f1eb9eaa6f2ee0.png) ##### **Application Scenarios** • Audio Signal Analysis: Metrics such as amplitude, frequency, signal-to-noise ratio (SNR), THD, THD+N • Analog Audio Testing: Headphone, microphone, speaker testing, crosstalk measurement ##### **Audio Analyzer** Input Impedance 10 TΩ 10 TΩ Input Range 3.5 Vrms 2 Vrms Coupling DC AC Bandwidth 20 kHz 75 kHz ADC Resolution 24 Bits 24 Bits Sampling Rate ≤ 192 kHz ≤ 192 kHz THD Measurement ≤ -106 dB (2 Vrms @ 1 kHz) ≤ -106 dB (2 Vrms @ 1 kHz) THD+N Measurement ≤ -82 dB (2 Vrms @ 1 kHz) ≤ -83 dB (2 Vrms @ 1 kHz) Measurement Accuracy Voltage 100 mVrms:± (1% of Reading + 0.005% of F.S.) 100 mVrms:± (1% of Reading + 0.02% of F.S.) 3.5 Vrms: ± (0.3% of Reading + 0.005% of F.S.) 2 Vrms:± (0.7% of Reading + 0.005% of F --- ## Plug-in Instrument Module: Waveform Generator Module - URL: https://intl.sienovo.cn/blog/139566774 - Date: 2024-06-09 - Tags: #DataAcquisition, #FPGADev ## Plug-in Instrument Module: Waveform Generator Module The waveform generator module is a crucial component in various industrial and scientific applications, including data acquisition, testing, and simulation. In this article, we will explore the features and capabilities of the plug-in instrument module's waveform generator module, highlighting its key specifications and potential uses. ### Key Specifications The waveform generator module boasts an impressive set of features, including: * **16-bit resolution**: Providing high accuracy and precision in waveform generation * **125 MHz refresh rate**: Enabling fast and smooth waveform updates * **Supports FSK/ASK signal generation**: Facilitating the creation of frequency-shift keying (FSK) and amplitude-shift keying (ASK) signals * **Generates arbitrary standard or user-defined waveforms**: Allowing for the creation of custom waveforms tailored to specific applications * **Simulates specific waveforms in special protocol communic --- ## Plug-in Instrument Module: Oscilloscope Module (Plug-in) - URL: https://intl.sienovo.cn/blog/139566750 - Date: 2024-06-09 - Tags: #DataAcquisition, #FPGADev Sienovo's plug-in oscilloscope module brings bench-grade waveform capture directly into a modular instrument chassis, giving embedded and power engineers a portable, software-driven alternative to a standalone scope. This post walks through the module's key specifications, explains the tradeoffs between the single-channel and dual-channel configurations, and covers the practical measurement scenarios each variant is best suited for. ## What Is a Plug-in Oscilloscope Module? Plug-in instrument modules follow the same philosophy as PXI and VXI: instead of a rack of dedicated benchtop instruments, a single chassis hosts interchangeable function-specific cards. The oscilloscope module described here occupies one slot and connects to the host system over a high-speed backplane interface. Because the digitiser, front-end conditioning, and signal path are all self-contained on the plug-in card, you get repeatable, calibrated measurements without the setup overhead of a full benchtop scope. --- ## Plug-in Instrument Module: Digital Multimeter Module (Plug-in Type) - URL: https://intl.sienovo.cn/blog/139566735 - Date: 2024-06-09 - Tags: #DataAcquisition, #FPGADev Plug-in instrument modules bring the precision of bench-top test equipment directly into embedded and FPGA-based data acquisition systems. This post covers the specification details of a plug-in digital multimeter (DMM) module, explaining what each parameter means in practice and how engineers can use this module for high-accuracy electrical measurement across voltage, current, resistance, inductance, and capacitance. ## What Is a Plug-in DMM Module? Unlike stand-alone benchtop multimeters, plug-in DMM modules are designed to seat into a chassis backplane — common in PXI, CompactDAQ, or proprietary modular instrument systems. This form factor lets you combine multiple measurement channels into a single controlled environment, synchronize acquisitions across modules, and automate test sequences without manual probe intervention. The module described here offers a 6½-digit display equivalent, meaning it can resolve readings to seven significant digits in display terms — on par with mid --- ## Embedded Instrument Modules: DMM & LCR & SMU and Automated Test Software - URL: https://intl.sienovo.cn/blog/139566706 - Date: 2024-06-09 - Tags: #DataAcquisition, #FPGADev • 6½ Digit Display • 24-bit Resolution • 250 kSPS Sampling Rate • Power and Digital I/O utilize isolated noise reduction technology ##### **Application Scenarios** • High-precision measurement of voltage, current, resistance, inductance, and capacitance • Diode/Transistor Testing Channels 1x 2x 2x 2x Input Impedance Voltage 10 MΩ High-Z, 10 MΩ High-Z Current 10 Ω 50 mΩ / 2 Ω / 2 KΩ 2 KΩ / 2 MΩ Input Range Voltage ± 5 V 0–60 V ± 20 V Current ± 2 mA 1 nA – 3 A ± 1 mA Resistance 1 MΩ – 100 MΩ Coupling DC DC DC DC ADC Resolution 24 Bits 24 Bits 24 Bits 24 Bits Sampling Rate 250 kSPS 250 kSPS 250 kSPS 250 kSPS Measurement Accuracy Voltage ± (0.018% of Reading + 0.0015% of F.S.) 6 mVDC:± (0.06% of Reading +0.075% of F.S.) 200 mVDC:± (0.01% of Reading +0.05% of F.S.) 6 VDC:± (0.018% of Reading +0.0013% of F.S.) 2 VDC:± (0.015% of Reading +0.007% of F.S.) 60 VDC:± (0.03% of Reading +0.001% of F.S.) 20 VDC:± (0.01% of Reading +0.003% of F. --- ## Domestically Developed Embedded Instrument Modules: Electronic Load Modules and Automated Test Software - URL: https://intl.sienovo.cn/blog/139566672 - Date: 2024-06-09 - Tags: #FPGADev, #DataAcquisition • Input current linearly adjustable within 0–5 A • Maximum power up to 150 W, suitable for various customized applications • Supports multiple operating modes: CC/CR/CV • Supports various auxiliary modules (e.g., PD control, signal modulation, QR code scanning) ##### **Application Scenarios** • Load capacity testing (power supply or signal) • Overvoltage/overcurrent protection testing for power management ICs | | Channels | Operating Mode | Input Range | Setting Resolution | Setting Accuracy | Measurement Resolution | Measurement Accuracy | Operating Voltage | Digital Interface | Dimensions (mm) | | :--- | :--- | :--- | :--- | :--- | :--- | :--- | :--- | :--- | :--- | :--- | | | 2× | CC/CV/CR | Voltage: 0.5–15 V | Voltage: 0.1 mV | Voltage: ± (0.1% of Reading + 0.1% of F.S.) | Voltage: 0.1 mV | Voltage: ± (0.1% of Reading + 0.1% of F.S.) | ± 12 VDC / 5 VDC | I²C, SPI | 100 × 72 × 34 (L) | | | 4× | CC | Voltage: 0.5–5 V | Current: 0.1 mA | Current: ± (0.1% of Reading + 0.02% of --- ## Embedded Instrument Module: Data Logging Module and Automated Test Software - URL: https://intl.sienovo.cn/blog/139566662 - Date: 2024-06-09 - Tags: #DataAcquisition, #FPGADev • 32-bit Resolution • 250 kSPS Sampling Rate • Simultaneously and continuously records two voltage input channels • Real-time raw data upload to PC Channel 2 2 Input Impedance Voltage 22 kΩ 10 MΩ Current 0.2 Ω Input Range Voltage ± 250 mV ± 4.5 V Current 1.5 A Coupling DC DC Bandwidth 450 Hz 385 Hz ADC Resolution 32 Bits 24 Bits Sampling Rate 10 kSPS 250 kSPS Measurement Resolution Voltage 1 nV 0.3 μV Current 1 nA Measurement Accuracy Voltage ± (0.1% of Reading + 0.006% of F.S.) ± (0.1% of Reading + 0.006% of F.S.) Current ± (0.1% of Reading + 0.002% of F.S.) ### Automated Test Software ****Core Features**** * Instrument Management * Test IP Development and Management * Test Plan Development and Management * Test Reports ****Application Scenarios**** * FCT (Functional Test) Testing * Chip Testing and Module Testing * Automated Production Lines ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139566662/01_d66bdeb --- ## Embedded Instrument Module: Audio Analyzer and Automated Test Software - URL: https://intl.sienovo.cn/blog/139566651 - Date: 2024-06-09 - Tags: #AudioVideo • 24-bit Resolution • 192 KHz Sampling Rate • Supports various analog/digital audio signal input/output ****Application Scenarios**** • Audio Signal Analysis: Amplitude, Frequency, Duty Cycle, THD, THD+N, and other metrics • Analog Audio Testing: Headphone, Microphone, Speaker testing, Crosstalk testing • Digital Audio Testing: PDM/TDM testing for tablets, laptops, and wearable devices **Audio Analyzer** Input Impedance 10 TΩ 10 TΩ 1 MΩ Input Range 3.5 Vrms 2 Vrms Single-Ended: 20 Vrms Differential: 35 Vrms Coupling DC AC DC Bandwidth 20 kHz 75 kHz Single-Ended: 300 kHz – 1 MHz Differential: 20 kHz ADC Resolution 24 Bits 24 Bits Single-Ended: 12 Bits Differential: 24 Bits Sampling Rate ≤ 192 kHz ≤ 192 kHz Single-Ended: ≤ 40 MHz Differential: ≤ 192 kHz THD Measurement ≤ -106 dB (2 Vrms @ 1 kHz) ≤ -106 dB (2 Vrms @ 1 kHz) ≤ -95 dB (2 Vrms @ 1 kHz) THD+N Measurement ≤ -82 dB (2 Vrms @ 1 kHz) ≤ -83 dB (2 Vrms @ 1 kHz) ≤ -82 dB (2 Vrms @ 1 kHz) Measu --- ## Embedded Instrument Module: Waveform Generator Module (Embedded) - URL: https://intl.sienovo.cn/blog/139566628 - Date: 2024-06-09 - Tags: #DataAcquisition, #FPGADev Embedded waveform generator modules bring the capability of a bench-top arbitrary waveform generator (AWG) onto a compact PCB that can be integrated directly into an instrument rack, test fixture, or edge-computing enclosure. This post introduces a family of embedded waveform generator modules designed for industrial and embedded applications, compares their key specifications, and walks through the scenarios where each variant makes the most sense. ## What Is an Embedded Waveform Generator Module? Traditional signal generators are standalone benchtop instruments — convenient for a lab but impractical when you need signal generation embedded inside a larger system. An embedded waveform generator module solves this by integrating a DAC (Digital-to-Analog Converter), analog output stage, and digital control interface onto a small PCB that accepts standard logic-level commands over I²C or a parallel bus. The result is a subsystem that an FPGA, microcontroller, or SBC can control progra --- ## Embedded Instrument Modules: Oscilloscope Modules and Automated Test Software - URL: https://intl.sienovo.cn/blog/139566603 - Date: 2024-06-09 - Tags: #DataAcquisition, #FPGADev ### Oscilloscope Modules • 32-bit Resolution • 125 MSPS Sampling Rate • Supports Single-Channel/Dual-Channel Module Selection • Low-speed mode enables real-time power distribution and overall device power detection • High-speed mode enables signal analysis and power-up timing measurements ##### **Application Scenarios** • Capture and analyze waveform parameters such as period, amplitude, and anomalous signals • Power ripple and noise analysis • Signal template comparison • Wireless charging (signal demodulation) | Channel | Input | Impedance | Voltage | Current | Output Range | Voltage | Current | Coupling | Bandwidth | ADC Resolution | Sampling Rate | Measurement Resolution | Voltage | Current | Measurement Accuracy | Voltage | Current | Operating Voltage | Digital Interface | Dimensions (mm) | |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| | 1 | High-Z, 1 MΩ | | | | ± 1 V / ± 10 V | | AC/DC | 18 MHz | 12 Bits | 40 MSPS | 0.48 mV / 4. --- ## Zynq7000 Series FPGA Modular Instrument - URL: https://intl.sienovo.cn/blog/139566562 - Date: 2024-06-09 - Tags: #FPGADev • Based on Xilinx XC7Z020 / 010 / 007S • Flexible module combinations • Compact form factor, easy to embed • High-performance ARM Cortex processor • Mature FPGA programmable logic, IP core-based software library ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139566562/01_2fae361c6d656268247045d9619ab744.png) The Zynq7000 series FPGA controller modules are System-on-Module (SOM) boards based on Xilinx XC7Z020/010/007S All Programmable System-on-Chip (SoC), belonging to the Xilinx ZYNQ-7000 series, featuring an integrated dual-core ARM Cortex-A9 processor with Xilinx 7 Series FPGA logic. The modules feature up to 1GB DDR3 SDRAM with a x32 data bus width, 4GB eMMC, 16MB quad-SPI flash, Gigabit Ethernet PHY, USB PHY, and an onboard USB-to-UART converter. It provides a large number of I/O signals for ARM peripherals and FPGA I/O via two 0.8mm pitch, 120-pin board-to-board connectors, making it ideal for your next embedded design. Customization services are also availabl --- ## UltraScale+ Series Modular Instrument: Simultaneously a Controller, Algorithm Accelerator, and High-Speed Digital Signal Processor - URL: https://intl.sienovo.cn/blog/139566519 - Date: 2024-06-09 - Tags: #FPGADev Based on XCZU7EG / XCZU4EG / XCZU2EG • Flexible Module Combinations • Compact Form Factor for Easy Embedding • High-Performance ARM Cortex Processors • Proven FPGA Programmable Logic, IP Core-Based Software Libraries Leveraging FPGA technology based on Xilinx Zynq UltraScale+ MPSoC, it utilizes Xilinx Zynq UltraScale+ to integrate multi-core ARM Cortex processors, abundant FPGA resources, and high-speed SerDes channels. It can simultaneously serve as a controller, algorithm accelerator, and high-speed digital signal processor. We provide ODM services covering R&D, verification, and mass production, as well as customization services to assist customers with hardware, logic, firmware, and software tasks. ##### **Hardware Block Diagram** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139566519/01_fd66714d2985cd9509011edcf16469a7.png) ##### **XCZU7EG FPGA — SOC (ARM+FPGA) Architecture** The Zynq®UltraScale+™ MPSoC family is based on the Xilinx UltraScale™ architectu --- ## NI Alternative: LCR Impedance Test Platform Achieves Measurement Speeds as Fast as 5 ms - URL: https://intl.sienovo.cn/blog/139552208 - Date: 2024-06-08 - Tags: #FPGADev, #DataAcquisition • Supports three test excitation modes: open-circuit voltage, constant voltage, and constant current • Excitation level supports up to 2 Vrms or 20 mArms, with DC bias functionality • Supports a wide frequency measurement range from 20 Hz to 2 MHz • Basic impedance measurement accuracy better than 0.1% • Up to 19 types of parameter measurements • Measurement speed as fast as 5 ms • Compact and modular, suitable for multi-channel parallel measurements ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139552208/01_01ce020ef16e2e92b6af25d374669733.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139552208/02_b00e41f98cd973ae747ec891cc06e66a.png) The LCR Impedance Test Platform is a precision LCR meter with a basic measurement accuracy of up to 0.1%. It supports various test excitation modes and features a wide, continuously adjustable test frequency range from 20 Hz to 2 MHz, along with continuously adjustable test levels from 0 to 2 Vrms or 0 to 20 m --- ## 【NI Domestic Alternative】Production Line Testing: Digital Multimeter (DMM), Power Analyzer, Customizable - URL: https://intl.sienovo.cn/blog/139552164 - Date: 2024-06-08 - Tags: #DataAcquisition, #FPGADev Digital Multimeter (DMM) • 6½-digit display • 24-bit resolution • 5 S/s - 250 kS/s sampling rate • Both power supply and digital I/O utilize isolated noise immunity technology • High-precision measurement of voltage, current, resistance, inductance, and capacitance • Diode/Transistor test ### Power Analyzer * Adjustable output voltage from 0.8V to 14V, with a maximum continuous output current of 8A; * Real-time acquisition of voltage, current, and power data, with graphical display via software; * Supports data acquisition from external power supply devices for external device power analysis; * Multiple devices can be used simultaneously for parallel monitoring; * Supports both USB and network communication methods, as well as local data storage functionality; * Features power-on self-test and multi-faceted protection, including: over-voltage, under-voltage, over-current, and over-temperature protection. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog --- ## 【Domestic NI Alternative】SMU Source Measure Unit: A Source Measure Unit Platform Primarily Used for IVR Testing and Measurement of Semiconductors, Sensors, Modules, etc. - URL: https://intl.sienovo.cn/blog/139552129 - Date: 2024-06-08 - Tags: #DataAcquisition • Integrates the functions of 5 instruments (Digital Multimeter, Voltage Source, Current Source, Electronic Load, and Pulse Generator) into one • Typical output source and measurement accuracy of 0.2%, supports DC/pulse output modes • In pulse output mode, minimum pulse width 100 us, rise time 10 us • Features a high-precision source with pA-level resolution, and supports multi-channel parallel current expansion • Supports 2-wire and 4-wire resistance measurement • Supports SCPI drivers and commands ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139552129/01_5373f8adec5da076ce948b0bf4fa7557.png) A precision Source Measure Unit (SMU) can perform four-quadrant operation, precisely outputting voltage or current while simultaneously measuring voltage, current, and resistance. It integrates the functions of a 6½-digit Digital Multimeter (DMM), a 5½-digit precision voltage source, current source, electronic load, and pulse generator. Its rich features, compact size, and stan --- ## 【NI Domestic Alternative】Production Line Integrated Tester: Lithium Battery Protection Board Tester, Supports Rapid Customization - URL: https://intl.sienovo.cn/blog/139552073 - Date: 2024-06-08 - Tags: #DataAcquisition ## SG2336 Lithium Battery Protection Board Tester: High-Precision Production-Line Testing with Up to 24 Parallel Channels As lithium battery packs become ubiquitous in everything from power tools to electric vehicles, the protection board (BMS protection IC + passive components) sitting between the cells and the load is a safety-critical component that must be validated before every unit ships. Historically, production-line testers for these boards came from vendors like National Instruments, whose platform costs and import lead times made domestic Chinese manufacturers look for alternatives. The SG2336 from Sienovo is one such domestically-developed alternative: a compact, high-integration instrument designed specifically for characterising and stress-testing lithium battery protection boards at both the R&D bench and on the production line. ## What the SG2336 Tests A lithium battery protection board has two broad categories of behaviour that must be verified: **Basic electrical c --- ## NI Domestic Alternative: Battery Simulator for Rapid Simulation of 3C Product Battery Charging and Discharging Functions - URL: https://intl.sienovo.cn/blog/139552039 - Date: 2024-06-08 - Tags: #DataAcquisition ## Battery Simulator for 3C Product Testing: A Domestic Alternative to NI Hardware Testing consumer electronics before the battery supply chain is ready is one of the most common bottlenecks in hardware development. Engineers who have worked in 3C product development — the shorthand for computers, communications, and consumer electronics — know the problem well: functional validation of charging and discharging circuits cannot wait for battery packs to arrive, and using real lithium cells during early bring-up introduces safety risks, variability between cells, and logistical overhead. A dedicated battery simulator solves all three problems by replacing the physical cell with a programmable voltage and current source that faithfully mimics the electrical behavior of a real battery. This post introduces a domestically produced battery simulator series designed as a cost-effective alternative to NI (National Instruments) hardware for exactly this class of test application. ## What Is --- ## 【Domestic Alternative to NI】Production Line Integrated Tester: High-Speed, High-Precision Oscilloscope and Arbitrary Waveform Generator Modules, Versatile DUT Power Supply, High-Precision Multimeter Module - URL: https://intl.sienovo.cn/blog/139552005 - Date: 2024-06-08 - Tags: #FPGADev * Xilinx ZYNQ-7000 Series FPGA Control Module * Versatile DUT Power Supply; High-Precision Multimeter Module * High-Speed, High-Precision Oscilloscope Module and Arbitrary Waveform Generator Module for Measurement * Optional RF Switch, Audio Signal Source, and Audio Analyzer Modules * Rapidly Deployable Test Platform Software, Supporting Test Plan Import, Development, and Execution Management * Good Scalability, Supporting Other Standard Instruments via Plug-in Architecture * Efficient Data Management, Supporting MES Integration, Product Test Data Analysis, and Report Output * Customizable Function Extensions for Professional Users * ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139552005/01_8e013de12f90853c15054d33bb5e1e96.png) The production line integrated tester offers excellent scalability and rich interfaces. Customers can use it with different test fixtures according to the testing requirements of various PCBA products, enabling rapid productio --- ## NI Alternative (Domestic): High-Speed Data Acquisition Module with Max Sampling Rate of 125 Msps, Supporting FPGA Customization - URL: https://intl.sienovo.cn/blog/139551973 - Date: 2024-06-08 - Tags: #FPGADev For engineers working in test and measurement, industrial automation, or RF signal processing, finding a high-performance data acquisition module that matches the capabilities of National Instruments (NI) hardware — without the NI price tag — has historically been a significant challenge. This post covers a domestically produced alternative: a dual-channel, high-speed data acquisition module featuring a maximum sampling rate of 125 Msps, 12-bit ADC resolution, and an FPGA-based architecture that allows deep hardware customization. ## The Case for a Domestic NI Alternative NI's CompactDAQ and PXI data acquisition platforms are industry workhorses, but their cost and lead times can be prohibitive for mid-scale industrial projects, embedded R&D labs, and academic applications. The module described here targets that gap directly, offering comparable core specifications — high sample rate, respectable resolution, and programmable logic — in a form factor suited for both prototyping and pr --- ## 【NI Domestic Alternative】PCIe High-Speed Data Acquisition Card, 8-bit Dual-Channel Digitizer, with a Maximum Sampling Rate of up to 5 GS/s and an Analog Bandwidth of up to 500 MHz - URL: https://intl.sienovo.cn/blog/139551951 - Date: 2024-06-08 - Tags: #DataAcquisition ## Unlocking High-Speed Data Acquisition with Sienovo's PCIe Digitizer In today's rapidly evolving technological landscape, the demand for high-speed, high-fidelity data acquisition (DAQ) is paramount across numerous industries, from scientific research to advanced industrial automation and defense. Engineers and researchers constantly seek robust solutions capable of capturing fast-changing analog signals with precision and efficiency. This article introduces Sienovo's cutting-edge PCIe High-Speed Data Acquisition Card, an 8-bit dual-channel digitizer engineered to meet these demanding requirements. We will delve into its core specifications, architectural advantages, and the flexibility it offers through extensive customization, providing a comprehensive overview of how this powerful instrument can elevate your data acquisition capabilities. ## Core Specifications and Unmatched Performance The Sienovo PCIe High-Speed Data Acquisition Card stands out with a set of impressive specif --- ## 【NI Domestic Alternative】500 MSPS Sampling Rate, 14-bit Resolution Data Acquisition Box - URL: https://intl.sienovo.cn/blog/139551914 - Date: 2024-06-08 - Tags: #EdgeComputing, #DataAcquisition High-speed data acquisition has long been dominated by Western vendors — National Instruments (now NI) chief among them. For engineers in industrial automation, radar signal processing, communications testing, and edge-AI inference pipelines, sourcing a domestically manufactured alternative that matches NI's performance envelope has historically been difficult. Sienovo's high-speed data acquisition box changes that calculus, delivering 500 MSPS sampling, 14-bit resolution, and a rich connectivity stack in a compact form factor purpose-built for demanding field and lab environments. ## Core Acquisition Performance The headline specification is a **500 MSPS (megasamples per second) sampling rate** across **two independent channels**, each resolving signals at **14-bit depth**. Together these figures define the system's Nyquist ceiling and dynamic range floor. - At 500 MSPS, the Nyquist limit is 250 MHz. The device's **200 MHz analog input bandwidth** sits just inside that ceiling, mea --- ## 6 Ethernet Ports, 8 Serial Interfaces, Multiple Communication and Control Interfaces (Relay, DI, IRIG-B), and Support for Bluetooth, GPS, Beidou, Wi-Fi, 2G/3G/4G Functions - URL: https://intl.sienovo.cn/blog/139551567 - Date: 2024-06-08 - Tags: #EdgeComputing ● It is an embedded product based on ARM® Cortex™-A9, with a quad-core CPU clocking up to 1.2GHz, featuring an HD-level video accelerator and achieving optimal energy efficiency through a new integrated power management solution. The hardware integrates 6 Ethernet ports, 8 serial interfaces, multiple communication and control interfaces such as relays, DI (Digital Input), and IRIG-B, and supports functions like Bluetooth, GPS, Beidou, Wi-Fi, 2G/3G/4G. It boasts features such as high reliability, high integration, long lifecycle, and flexible expandability. It adopts a fanless passive cooling system, supporting a wide operating temperature range of -40℃ to +85℃ for long-term stable operation. The product is designed based on the principles of power system relay protection products, meeting the highest industry standards for safety regulations and electromagnetic compatibility (EMC) immunity. It can be widely applied in traditional power systems, smart grids, rail transit, industrial co --- ## Network Packet Recording and Fault Recording Analysis Device for Smart Substations - URL: https://intl.sienovo.cn/blog/139551542 - Date: 2024-06-08 - Tags: #Networking Smart substations rely on high-speed, time-sensitive communication networks — primarily IEC 61850-based Ethernet — to coordinate protection relays, merging units, and intelligent electronic devices (IEDs). When a fault occurs, engineers need millisecond-accurate packet captures and waveform records to reconstruct what happened and why. A general-purpose network tap or software-based packet capture tool is rarely adequate: substation environments demand fanless operation across wide temperature ranges, deterministic real-time capture with no dropped frames, and hardware-grade timestamps that can be correlated with GOOSE trips and sampled-value streams. The device described here is purpose-built to meet exactly those requirements. ## Hardware Foundation: X86, PowerPC, and FPGA Working Together The platform integrates three processor architectures, each assigned to what it does best. **Intel X86** handles the heavy analytical workload: protocol decoding, search and indexing of captured --- ## DIO Control Card, IRIG-B Time Code Card, PCI-E Bus Interface Card, 100Mbps Data Acquisition Card - URL: https://intl.sienovo.cn/blog/139551464 - Date: 2024-06-08 - Tags: #DIOCard DIO Control Card ● 4-channel Relay Output (5A@250VAC) ● 4-channel Digital Input (24VDC) ● 1-channel IDE Interface ● Port Surge Protection![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139551464/01_963b30a0d540c1df0a0010f3c52ee32b.png) ## IRIG-B Time Code Card ● 1-channel IRIG-B Time Synchronization Interface (RS485/Fiber Optic) ● 1-channel IEEE1588 V2 Time Synchronization Interface (RJ45/Fiber Optic) ● PTP Mode Time Synchronization Accuracy: ±100nS ● ETE Mode Time Synchronization Accuracy: ±250nS ● IRIG-B Time Synchronization Accuracy: ±250nS ● Self-holding Time Accuracy up to ±50mS/24 hours ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139551464/02_88d3b2031903e367fa2ac6cdcb4a1823.png) ## PCI-E Bus Interface Card ● Expands 6-channel PCI Express X1 Interfaces ● Cable Connectors with Anti-loosening Structure ● Dedicated High-speed Communication Cables (SFF 8088 Specification) ● Each Communication Port Contains 2-channel PCI Express X1 ![](https://pub --- ## Distribution Network Terminal Communication Management Board, Stability Control Device Communication Management Card, Railway Signal Communication Management Card - URL: https://intl.sienovo.cn/blog/139551386 - Date: 2024-06-08 - Tags: #Networking ## Expanded Article: Distribution Network Terminal Communication Management Board The Distribution Network Terminal Communication Management Board is a critical component in modern industrial control systems, enabling seamless communication between various devices and networks. In this article, we will delve into the specifications and features of this board, which is designed to provide reliable and efficient communication in demanding environments. The Distribution Network Terminal Communication Management Board is powered by an ARM Cortex-A5 processor running at 533MHz, providing a solid foundation for processing and communication tasks. The board is equipped with 256MB of RAM and 512MB of FLASH storage, ensuring that it can handle a range of applications and store necessary data. In terms of networking capabilities, the board boasts two 10/100/1000Mbps LAN ports (RJ45) for high-speed connectivity, as well as six RS232/485 ports with 2500VDC isolation for secure and reliable comm --- ## Nvidia/Sophon + FPGA + High-Compute AI Edge Computing Box: Automated Cleaning Machines - URL: https://intl.sienovo.cn/blog/139529156 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing Outdoor cleaning robots and high-density AI edge boxes represent two converging trends in industrial edge computing: autonomous mobile platforms that must process multi-sensor fusion in real time, and compact appliances that pack data-center-class inference throughput into a fanless enclosure. This post covers both — ViaBot's NVIDIA Jetson-powered cleaning robot and the XM-AIBOX-32, an edge AI box built on Sophon's BM1684X SoC — to show how today's edge silicon makes both possible. ## ViaBot: Modular Outdoor Cleaning Robots on NVIDIA Jetson Silicon Valley-based ViaBot was founded in 2016 when Gregg Ratanaphanyarat and Dawei Ding dropped out of Penn State University to build outdoor cleaning robots for enterprise customers. Their bet is paying off: the company is now running a pilot with a large partner to autonomously clean a Bay Area parking lot, with plans to expand. The insight behind ViaBot is a gap in the facilities-management market. Robotics companies typically target a singl --- ## Nvidia/Sanneng + FPGA + AI High-Performance Edge Computing Box: DJI RoboMaster AI Challenge - URL: https://intl.sienovo.cn/blog/139529106 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing ## **NVIDIA Jetson TX2 Powers Robot Teams to Win RoboMaster AI Challenge Championship and Runner-Up** A competition arena bringing together millions of robotics experts and researchers, a contest combining engineering, strategy, and team challenges – this describes the DJI RoboMaster AI Challenge, which recently concluded at the ICRA conference in Brisbane, Australia. This year's champion, I Hiter, and runner-up, Critical HIT, both built their robot teams based on the modular NVIDIA Jetson TX2 supercomputer. The high-performance Jetson TX2 served as the "brain" for the winning robot teams, endowing them with greater intelligence and stronger combat capabilities, making them invincible in the final showdown. Each RoboMaster team competes with 1 to 2 AI-powered robots. In a 5x8 meter arena filled with obstacles, competing robots must navigate autonomously while firing plastic projectiles at opponent robots. The winner must defeat two advanced AI robots provided by RoboMaster. Each pa --- ## Nvidia/Sophon + FPGA + High AI Compute Edge Computing Box: AI Smart Monitoring for Beach Rescue - URL: https://intl.sienovo.cn/blog/139529071 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing A team in Israel has made a splash with its achievements in the field of artificial intelligence. Their achievements today stem from an idea conceived many years ago. Netanel Eliav and Adam Bismut, old friends from their campus days, wanted to solve a problem that could change the world. The idea came to Bismut when, while floating in the Dead Sea, he realized the lack of lifeguard technological support there, with outdated binoculars being used to scan the sea. These two aspiring entrepreneurs, who recently graduated with MBAs from Ben-Gurion University in southern Israel, saw this as a problem they could solve with artificial intelligence. “As a father of two daughters, I deeply understand the feelings parents have when their children play near the water,” said Eliav, the company’s CEO. In 2018, they co-founded Sightbit with Gadi Kovler and Minna Shezaf, classmates from their time at Ben-Gurion University, to help lifeguards observe dangerous situations and prevent drownings. C --- ## Nvidia/Sophgo +FPGA+AI High-Performance Edge Computing Box: Tunnel and Mine Mapping Equipment - URL: https://intl.sienovo.cn/blog/139529005 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing RockMass is working to break into the niche market of mining and tunnel engineering. This Toronto-based startup is leveraging NVIDIA AI to develop a mapping platform that helps engineers assess the stability of mine shafts and tunnels under construction. Currently, as a safety precaution, geologists and engineers stand five meters away from the rock to visually assess the hazard level of rock formations. However, Shelby Yee, co-founder and CEO of RockMass, believes this is not an ideal way to ensure the accuracy of results. "Using their current assessment method, the entire process takes nearly 90 minutes, whereas our technology can complete it in about 5 minutes," Yee said. RockMass is testing its handheld device, Mapper, with field engineers. The device is applicable in mining, geological exploration, and civil engineering. The startup is developing an AI platform for robots, drones, and handheld devices that capture geological data. Now, the startup's Mapper AI device offers a --- ## [Case Study] Nvidia/Sopon + FPGA + AI High-Performance Edge Computing Box: Vehicle 3D Perception System - URL: https://intl.sienovo.cn/blog/139528963 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing Invested in and participated by CAS Source Computing, the company boasts a top-tier team, decades of research accumulation, and successful technology development and implementation. The core team members have focused on IoT and edge computing research for decades, possessing extensive experience in the R&D and implementation of large-scale intelligent IoT systems and "device-edge-cloud" integrated computing systems. The team has participated in numerous national-level fundamental scientific research projects in the IoT field, earning high recognition both domestically and internationally. Currently, the company holds dozens of intellectual property rights, has obtained qualifications as a National High-tech Enterprise and a Zhongguancun High-tech Enterprise, and received the "Double Soft" certification from the China Software Industry Association. It has been honored with titles such as CAS STS Innovation and Entrepreneurship Guidance Project, Zhongguancun Golden Seed Enterprise, Hai --- ## Nvidia/Sophon + FPGA + High-Performance AI Edge Computing Box: Intelligent Detection in Industrial Production - URL: https://intl.sienovo.cn/blog/139528767 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing With the mission of "Empowering Business Value with Artificial Intelligence," [Company Name] is China's largest "AI + Manufacturing" solution provider and China's third-largest enterprise-level AI solution provider. The company is committed to providing AI products and solutions to enterprises using cutting-edge artificial intelligence technology, including AI platforms, algorithms, software, and AI-enabled equipment, to improve customer operational efficiency and business value, and achieve digital transformation. The group has been awarded the national-level "Little Giant" title for "Specialized, Refined, Unique, and Innovative" enterprises, and five of its subsidiaries have been recognized as provincial/municipal-level "Specialized, Refined, Unique, and Innovative" enterprises. On the path of "Specialized, Refined, Unique, and Innovative" development, AInnovation deeply cultivates and explores the practical application of AI in various subdivided fields such as steel and metallurgy --- ## Nvidia/Sophon + FPGA + High-Performance AI Edge Computing Box: Measurement, Control, and Inspection Smart Robot - URL: https://intl.sienovo.cn/blog/139525548 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing, #Robotics We are a high-tech enterprise integrating R&D, production, manufacturing, and sales, and a technological leader in the field of "conveyor belt intelligent inspection" in China. The company has successively obtained honorary qualifications such as National High-tech Enterprise, Taiyuan Municipal Enterprise Technology Center, Taiyuan Technology Innovation Demonstration Enterprise, Shanxi Private Technology Enterprise, Shanxi "Specialized, Refined, Unique, and Innovative" SME, Shanxi "Four New" SME, Taiyuan Small and Micro Credit Enterprise, Taiyuan High-tech Zone "Double Hundred" Enterprise, and Shanxi Comprehensive Reform Zone Innovation and Entrepreneurship Enterprise. The company currently holds 3 trademark registrations, 4 software copyright patents, and 51 national patent certificates, continuously achieving breakthroughs in the intelligent inspection of conveyor belt safe operation, with its technological level consistently leading the industry's development. ![](https://pub-048d --- ## Intel x86+FPGA: Application of Intelligent AI Computer System in Bronchial Navigation Robots - URL: https://intl.sienovo.cn/blog/139519408 - Date: 2024-06-07 - Tags: #AI, #Robotics ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139519408/01_1f169841fb9d0c160c9afd0d007e1e3c.png) With the rapid development of artificial intelligence, technological breakthroughs, and the gradual expansion of its application fields, medical robots, as a deepening application of the AI era in the medical field, can effectively assist doctors with a range of medical diagnoses and auxiliary treatments, promoting the development of medical informatization while effectively alleviating the strain on medical resources. **Smart Healthcare Scenario Applications** From an application scenario perspective, there is a significant demand for surgical robots in scenarios requiring precise operations, such as neurosurgery, orthopedics, and endoscopic surgery. Surgical robots play a crucial role in clinical and surgical settings. Surgical robots are innovative medical devices invented based on the development of foundational technologies such as minimally invasive surgery and co --- ## X86+FPGA Solution: Application in Smart Video Monitoring System for Railway Freight Car Loading - URL: https://intl.sienovo.cn/blog/139519288 - Date: 2024-06-07 - Tags: #FPGADev If the advent of high-speed rail technology ushered in a "speed revolution" for railway transportation, then the application of artificial intelligence technology will create an "intelligence revolution" for rail travel. Railways are the arteries of the national economy. The safety of railway transportation not only affects the efficiency and benefits of the railway itself but also directly impacts the production, daily life, stability, and harmony of the entire society. Railway freight transportation is a crucial component of railway transport. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139519288/01_027dfa31f5a3cf4465c93146847f5def.jpeg) _**Scenario-Driven Product Innovation**_ **User Application Requirements** In the process of railway freight transportation, timely detection of abnormal issues such as cargo exceeding limits, shifting, or overloading, and identifying vehicles with overloaded or oversized cargo, is of great significance for ensuring operationa --- ## Nvidia/Sophon + FPGA + AI High-Performance Edge Computing Box: Smart Robot for Power Inspection - URL: https://intl.sienovo.cn/blog/139493655 - Date: 2024-06-07 - Tags: #AI, #FPGADev, #EdgeComputing Focusing on the digital economy and dual-carbon economy tracks, we specialize in providing integrated digital and intelligent solutions for centralized new energy power stations and distributed integrated energy systems, adhering to a dual-driven development model of power station digitalization and integrated energy digitalization. Relying on a professional talent team and rich research experience from practical bases, we have built a mature and advanced digital and intelligent new energy R&D platform. In the field of centralized new energy power stations, we focus on the research, innovation, and application of technologies such as machine vision, artificial intelligence, digital twin, big data, and IoT, to uncover the data value of photovoltaic power stations and improve power station operation and maintenance efficiency. We independently develop software products and intelligent equipment such as regional integrated smart O&M platforms, photovoltaic power station production manage --- ## Nvidia/Sophon + FPGA + AI High-Performance Edge Computing Box: Smart Services for Healthcare - URL: https://intl.sienovo.cn/blog/139493221 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing As a leader in domestic sports medicine, dedicated to providing comprehensive clinical solutions for sports medicine, the company is located in the Beijing Economic-Technological Development Area. Over 300 specifications of sports medicine equipment, implants, and surgical instruments for shoulder, knee, foot/ankle, hip, elbow, and hand/wrist joints have received NMPA approval and are clinically applied in thousands of hospitals across 31 provinces, municipalities, and autonomous regions in China. The company has made breakthroughs in several major key technologies, including injection molding, weaving, preparation and processing of absorbable materials, and active device development for sports medicine products. It has established a comprehensive quality management system, with 13 product specifications certified by EU CE, ISO9001, ISO13485, and national GMP, becoming a domestic enterprise capable of providing comprehensive clinical solutions for sports medicine. The company has form --- ## Nvidia Jetson/Orin +FPGA+AI High-Performance Edge Computing Box: Intelligent Finance for Banking Service Systems - URL: https://intl.sienovo.cn/blog/139388752 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing, #Finance **Industrial and Commercial Bank of China (ICBC)** - Established on January 1, 1984. Its head office is located at No. 55 Fuxingmen Inner Street, Beijing. It is a state-owned large commercial bank and a national sub-ministerial level institution. ICBC's fundamental mission is to raise social funds through domestic and international financing activities, strengthen credit fund management, support enterprise production and technological transformation, and serve China's economic construction, all in accordance with national laws and regulations. After the Third Plenary Session of the Eleventh Central Committee of the Communist Party of China was held in December 1978, the pace of financial system reform in China accelerated. With the restoration and establishment of various financial institutions and the diversification of financial service demands, to resolve the contradiction where the People's Bank of China (PBOC) simultaneously performed monetary policy formulation and financial reg --- ## Nvidia Jetson/Orin/SOPHON +FPGA+High-Performance AI Edge Computing Box: Weichai Lovol Smart Agriculture Unmanned Driving - URL: https://intl.sienovo.cn/blog/139388715 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing **Weichai Lovol Smart Agriculture Technology Co., Ltd.** is a crucial strategic business unit of Weichai Group. Its businesses, including harvesting machinery and tractors, have maintained industry leadership for many consecutive years, making it one of the few domestic brands capable of providing comprehensive mechanized solutions for modern agriculture. Following Weichai Group's strategic restructuring of Weichai Lovol Smart Agriculture, Weichai Lovol Smart Agriculture has officially entered a new phase of development. Focusing on two major strategic businesses: intelligent agricultural machinery and smart agriculture, it leverages Weichai Group's advantages in new technology fields such as hydraulic electronic control, CVT powertrains, new energy, and intelligent driving. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139388715/01_ae9b74f94e80b31e1fe9d89293f2507b.png) Weichai Lovol Smart Agriculture continuously breaks through cutting-edge technologies in agricultur --- ## Nvidia Jetson/Orin/Sophon + FPGA + AI High-Performance Edge Computing Box: Gas Station Safety Intelligent Detection System - URL: https://intl.sienovo.cn/blog/139388272 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing, #Security Due to the unique nature of the gas station industry, oil depots and gas stations often store large quantities of refined fuel to meet sales demands, making the safety of personnel and property paramount. Xinmai Technology's Smart Gas Station Solution focuses on gas station safety, based on digital gas stations, to create a one-stop smart safety gas station solution; the solution covers safety management for service areas and refueling operation zones. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139388272/01_290b41c1a5ef4b727243eee2b8afe928.jpeg) This solution utilizes intelligent recognition and analysis technologies, such as AI edge computing boxes and cameras, to analyze real-time video content, detect abnormal information, and predict risks, thereby enhancing gas station safety coefficients in the most efficient and direct way. It performs detection for fire/smoke in operation areas, phone call recognition, personnel intrusion, staff behavior compliance, on-duty --- ## Nvidia Jetson/Orin +FPGA+AI High-Performance Edge Computing Box: Real-time VR Content Creation with 3D Scanners - URL: https://intl.sienovo.cn/blog/139388079 - Date: 2024-06-07 - Tags: #AI, #EdgeComputing, #3d While VR technology has revolutionized various aspects of daily life, such as entertainment, healthcare, architecture, education, and product design, creating VR content remains a challenging hurdle. At the Jetson TX2 launch event held by Nvidia in San Francisco, it was demonstrated how the Jetson TX2 can accelerate AI computing, graphics, and computer vision operations, and power workflows for VR content creation. The Artec Leo, a handheld scanner developed by Artec 3D using the Jetson TX1, can perform real-time 3D capture, fusion, modeling, and visualization on its own display, and can also stream to mobile phones and tablets. The Artec Leo is powered by the ultra-fast, credit card-sized Jetson TX1 platform, scanning 8 million points per second, integrating color and texture data into 3D depth information, to create 3D models with 0.1 mm accuracy in real-time. Artyom Yukhin, President and CEO of Artec, said: "The Artec Leo makes 3D scanning as simple as shooting video. The Jetso --- ## Nvidia Jetson/Orin/SOPHON +FPGA+High-Performance AI Edge Computing Box: Drone Autonomous Flight Software Platform - URL: https://intl.sienovo.cn/blog/139388056 - Date: 2024-06-07 - Tags: #AI, #FPGADev, #EdgeComputing ### **Project Overview** · The Generalized Autonomy Aviation System (GAAS), which we led the development of, is an open-source drone autonomous flight framework designed for unmanned aerial vehicles (UAVs) and Urban Air Mobility (UAM). Through functionalities such as SLAM, path planning, and Global Optimization Graph, it provides UAVs with autonomous flight capabilities in situations without GPS and external communication. · In this case, GAAS, powered by NVIDIA Jetson TX2, achieved on-board processing of visual sensor data on the UAV, assisting the UAV in fully autonomous aircraft inspection. · This case primarily utilized NVIDIA Jetson TX2. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139388056/01_4c8ee23166835ae6d9ea96c27c573207.png) ### **Background** The Generalized Intelligence team comprises experts and scholars from various fields including machine learning, SLAM, and UAVs; and holds multiple leading domestic and international patented technologies. The g --- ## Nvidia/Sophon + FPGA + High-Performance AI Edge Computing Box: Intelligent Early Warning System for Large Machinery - URL: https://intl.sienovo.cn/blog/139493911 - Date: 2024-06-06 - Tags: #AI **Sany Heavy Industry Co., Ltd.**, founded by Sany Group in 1994, rapidly rose by breaking the traditional "technophobia" of the Chinese people and insisting on independent innovation. In July 2011, Sany Heavy Industry, with a market capitalization of US$21.584 billion, was listed among the Financial Times Global 500, making it the only Chinese machinery enterprise to date to make the list. In January 2012, Sany Heavy Industry acquired Putzmeister, the "world's number one concrete machinery brand" from Germany, fundamentally altering the global industry competitive landscape. Sany Heavy Industry's parent company, Sany Group, was officially established in Lianyuan, Hunan, in 1989. The company's name originates from its founding vision: "To build a first-class enterprise, cultivate first-class talent, and make first-class contributions." For many years, Sany has upheld "Quality Changes the World" as its mission, striving to contribute a world-class brand to the Chinese nation. ![](http --- ## Nvidia/Sophon + FPGA + AI High-Performance Edge Computing Box: Smart Agricultural Drone System Aids Modernization Process - URL: https://intl.sienovo.cn/blog/139493795 - Date: 2024-06-06 - Tags: #AI, #EdgeComputing, #UAV We are a domestic R&D, production, and sales company for drone flight controllers, unmanned vehicle main controllers, and smart devices, as well as an industry big data cloud platform solution provider. Our company headquarters is located in Urumqi, Xinjiang, with a branch in Changji, Xinjiang. We have unmanned vehicle and drone testing bases in Beijing and Langfang, Hebei, along with an AI software center and a big data BI center. "Glory Nine Heavens" focuses on exploring automated and intelligent solutions and developing products for industry applications, applying its independently developed AI recognition technology to unmanned vehicles and drone flight controllers. Our independently developed products include: Our R&D team has many years of technical accumulation in drone flight control, intelligent robot main control, and smart product fields, possessing high-level R&D capabilities with independent intellectual property rights, ensuring continuous iteration and upgrade of our pr --- ## Nvidia/Sophon +FPGA+AI High-Compute Edge Computing Box: - URL: https://intl.sienovo.cn/blog/139493719 - Date: 2024-06-06 - Tags: #AI, #EdgeComputing **China University of Petroleum (Huadong)** is a national key university directly under the Ministry of Education, one of the universities included in "Project 211" and the "Innovation Platform for Advantageous Disciplines under Project 985" initiatives, and equipped with a graduate school. The university is jointly built by the Ministry of Education and five major energy enterprise groups, and by the Ministry of Education and the People's Government of Shandong Province. It is an important base for cultivating high-level talents in the petroleum and petrochemical industries, renowned as "the cradle of petroleum technology and management talents." It has now become a university primarily focused on engineering, with distinct petroleum and petrochemical characteristics, and coordinated development across multiple disciplines. It was included in the national "Double First-Class" Initiative in both 2017 and 2022. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139493719/01_ --- ## Nvidia/Sophon +FPGA+AI High-Performance Edge Computing Box: China Ship Research Institute - URL: https://intl.sienovo.cn/blog/139493545 - Date: 2024-06-06 - Tags: #AI, #BigData, #EdgeComputing **China Ship Research Institute**, also known as the Seventh Research Institute of China Shipbuilding Industry Corporation (CSIC), is affiliated with China Shipbuilding Industry Corporation. It is a scientific and technological research institution specializing in ship research, design, and development, serving as CSIC's military product technology research center and scientific and technological development center. Its main activities include strategic research on naval weapon equipment development, top-level technological research on ship systems, system integration and system engineering management, and research and development of dual-use technologies (military and civilian). The China Ship Research Institute's predecessor was the Seventh Research Institute of the Ministry of National Defense, established in June 1961, and it was successively affiliated with the Commission for Science, Technology and Industry for National Defense (COSTIND), the Sixth Ministry of Machine Building I --- ## Nvidia/Sophon + FPGA + AI High-Performance Edge Computing Box: Bridge Structure Safety Monitoring - URL: https://intl.sienovo.cn/blog/139493278 - Date: 2024-06-06 - Tags: #AI, #FPGADev, #EdgeComputing **China Railway Design Group Co., Ltd.** (CRDC), formerly China Railway Third Survey and Design Institute Group Co., Ltd. (CRTSDI), is the sole design enterprise affiliated with China State Railway Group Co., Ltd. Established in 1953 and headquartered in Tianjin, it is a large enterprise group primarily engaged in engineering survey, design, consulting, supervision, EPC (Engineering, Procurement, and Construction) contracting, and product industrialization for railways, urban rail transit, highways, and other projects. It holds a Class A comprehensive engineering design qualification certificate and is one of the first high-tech enterprises recognized by the state. Its comprehensive strength ranks among the top in the industry. In the 2022 ENR rankings, it was ranked 37th among the Top 150 Global Design Firms, 103rd among the Top 225 International Design Firms, 35th among the Top 80 Chinese Contractors, and 5th among the Top 60 Chinese Engineering Design Firms. ![](https://pub-048dcb --- ## High-Performance Network Security Motherboard with Phytium D2000 8-Core, 32GB DDR, Onboard 6 Gigabit Electrical Ports, and 4 Gigabit Optical Ports - URL: https://intl.sienovo.cn/blog/139407722 - Date: 2024-06-03 - Tags: #Security, #PhytiumD2000 ****Chapter 1: Product Introduction**** ****1.1 Product Overview**** The XM-D2000GW is a high-performance network security motherboard based on the Phytium D2000 8-core processor and X100 chipset. The D2000 is Phytium's first 8-core desktop platform processor, supporting dual-channel DDR4-2666 memory. The chip integrates national cryptographic SM2/SM3/SM4/SM9 acceleration engines and supports single-precision and double-precision floating-point instructions, accelerating network data processing. It can be widely applied in fields such as edge computing gateways, intrusion detection, VPNs, network monitoring, and security auditing. ****1.2 Product Features****   Onboard Phytium D-2000 8-core 2.3GHz high-performance processor   Utilizes Phytium X100 chipset   Supports dual-channel DDR4-2666 memory, up to 64GB   Onboard 6 Gigabit electrical ports, supporting 3 sets of third-generation intelligent bypass (optional)   Onboard 4 Gigabit optical ports   The side of the motherboard suppor --- ## Nvidia Jetson/Orin + FPGA + AI High-Performance Edge Computing Box: Rail Transit Monitoring System - URL: https://intl.sienovo.cn/blog/139388639 - Date: 2024-06-02 - Tags: #AI, #FPGADev, #EdgeComputing **CRRC Times Electric Co., Ltd.** (hereinafter referred to as CRRC Times Electric) is a joint-stock enterprise under CRRC Corporation Limited. Its predecessor and parent company, CRRC Zhuzhou Electric Locomotive Research Institute Co., Ltd., was founded in 1959. Rooted in Zhuzhou, CRRC Times Electric has mastered rail-based technologies and expanded beyond them. Adhering to the "dual high, dual efficiency" high-speed traction management model and upholding the "concentric diversification" development strategy, CRRC Times Electric has formed a complete industrial chain structure of "basic components + devices and systems + complete machines and engineering" centered around technology and market. Its industries cover rail transit, new energy power generation, power electronic devices, automotive electric drives, industrial electrical equipment, marine engineering equipment, and other fields. With business spanning over 20 countries and regions worldwide, it has established good cooperat --- ## Nvidia Jetson/Orin +FPGA+AI High-Performance Edge Computing Box: AI Applications in Firefighting - URL: https://intl.sienovo.cn/blog/139388208 - Date: 2024-06-02 - Tags: #AI, #EdgeComputing, #SmartFireProtection **Qingniao Fire Protection Co., Ltd.** was established in June 2001 and was listed on the Shenzhen Stock Exchange in August 2019, becoming the first enterprise in China's fire alarm industry to be listed on the A-share market. The company consistently focuses on fire safety and IoT fields, with its main business involving the R&D, production, and sales of "one-stop" fire safety system products. The company's products cover the entire chain of fire alarm and firefighting: early warning → alarm → fire prevention → evacuation and escape → extinguishing, providing comprehensive protection services for people's lives and property. The company takes safeguarding people's lives and property as its mission, builds its product system with completely independent intellectual property rights, achieves excellent results with a comprehensive market channel network, and wins customers through standardized and rigorous professional services. Qingniao Fire Protection has been actively expanding into --- ## Nvidia Jetson/Orin + FPGA + AI High-Compute Edge Computing Box: Highway Roadside System - URL: https://intl.sienovo.cn/blog/139388105 - Date: 2024-06-02 - Tags: #AI, #EdgeComputing **Sichuan Expressway Construction and Development Group Co., Ltd.** was established in July 1992 with a registered capital of 9.4 billion RMB, and is one of the direct subsidiaries of Shudao Group. Since its establishment, Chuan Gao Company has consistently upheld its responsibility as a state-owned enterprise, actively serving the overall development of the province, and fully promoting the investment, construction, and operation management of expressways and related supporting facilities, striving to improve the province's expressway network and service system. After 30 years of continuous exploration and development, Chuan Gao Company currently has over 60 wholly-owned, controlling, and participating subsidiaries, a total workforce of 14,000 employees, and operates a total of 5,693 kilometers of expressways. Standing at a new era and embarking on a new journey, under the strong leadership of Shudao Group, Chuan Gao Company will adhere to the guidance of Socialism with Chinese Chara --- ## Nvidia Jetson/Orin +FPGA+AI High-Compute Edge AI Box: JD.com Autonomous Delivery Robots - URL: https://intl.sienovo.cn/blog/139388020 - Date: 2024-06-02 - Tags: #AI, #EdgeComputing, #Robotics E-commerce giant JD.com has selected the NVIDIA Jetson AGX Xavier platform as the core AI compute for its next-generation autonomous delivery robots. In the past few decades, China has accounted for over 40% of global e-commerce transactions—approximately hundreds of billions of dollars annually. According to data from the McKinsey Global Institute, this figure already exceeds the combined total of France, Germany, Japan, the UK, and the US. To support this massive growth, major Chinese e-commerce companies are developing AI-powered delivery robots to transport goods between warehouses, accelerate last-mile delivery, and deliver products to consumers and businesses. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139388020/01_c7fcaff7c8b81f6818fcc4fad18e5e2b.jpeg) JD.com is a major Chinese e-commerce company with 300 million active customers and China's largest in-house e-commerce logistics network. It is the world's first e-commerce company to launch fully autonomous --- ## Nvidia Jetson/Orin +FPGA+AI High-Compute Edge AI Box: Meituan Xiaodai Autonomous Delivery Vehicle - URL: https://intl.sienovo.cn/blog/139388000 - Date: 2024-06-02 - Tags: #AI, #EdgeComputing Meituan's Xiaodai autonomous delivery robot represents one of the more ambitious real-world deployments of edge AI in last-mile logistics — a compact, battery-powered vehicle navigating busy urban environments to carry food orders from restaurant to doorstep, powered at its core by the NVIDIA Jetson AGX Xavier. This post looks at the hardware choices behind Xiaodai and why a robot of its size still demands the same computational firepower as a full-scale self-driving car. ## Meituan and the Last-Mile Problem Meituan-Dianping occupies a unique position in Chinese tech: it blends food delivery, local business discovery, and group commerce into a single platform, partnering with more than 400,000 local businesses. In scale and business model it sits somewhere between Uber Eats, Yelp, and Groupon rolled into one. With that kind of delivery volume, even incremental automation of the last-mile segment — the notoriously expensive and labor-intensive stretch between a restaurant and a custom --- ## Nvidia Jetson/Orin +FPGA+AI High-Compute Edge AI Box: Smart Road Inspection Solution - URL: https://intl.sienovo.cn/blog/139387967 - Date: 2024-06-02 - Tags: #AI, #EdgeComputing **Project Background** China's road network is vast, with a total mileage exceeding 5.35 million kilometers, and its expressway mileage ranks among the highest in the world. Facing the continuous growth of infrastructure stock, highway maintenance and management has entered a new era of an integrated approach to construction, management, and maintenance. As maintenance expenditures increase year by year, improving maintenance efficiency and reducing management costs have become urgent issues. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139387967/01_df0f8b88a8f92f591ee86ee80cbb48c7.jpeg) **Challenges Faced** 1. High-Frequency Inspections and Labor Costs: Daily inspection work is arduous, leading to high labor costs. 2. Data Collection and Management: Manual data collection and recording are highly subjective, inefficient, and pose safety risks to personnel. 3. Limitations of Annual Inspections: While reliable, annual inspections are costly and infrequent, failing --- ## Nvidia Jetson/Orin + FPGA + High-Compute AI Edge Box for Smart Landscape Monitoring Solution - URL: https://intl.sienovo.cn/blog/139387897 - Date: 2024-06-02 - Tags: #AI, #EdgeComputing, #Nvidia+FPGA **Project Background** Guided by the concept that "lucid waters and lush mountains are invaluable assets," the nation has put forward the "14th Five-Year Plan for Forestry and Grassland Protection and Development." This plan aims to improve the management level of national parks by conducting surveys, confirming registration, and demarcating boundaries for natural resource assets. It also seeks to establish an integrated "space-air-ground" monitoring system, implement protection and restoration of natural ecosystems, protect flagship species and restore their habitats, construct ecological corridors, and protect and restore natural landscapes and cultural heritage sites. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139387897/01_89cf4caa98b5bff03c261536b1f67cf3.jpeg) **Industry Requirements** 1. Comprehensive resource surveys, dynamic supervision, and performance evaluation. 2. Effective prevention and control of major disasters and harmful organisms. 3. Scientific --- ## Nvidia Jetson/Orin + FPGA + AI Agricultural Transport Robot Solution - URL: https://intl.sienovo.cn/blog/139387854 - Date: 2024-06-02 - Tags: #AI, #Robotics **Project Background** As one of Asia's developed countries, South Korea has recently faced issues such as an aging population and high labor costs, posing severe challenges to its agricultural production and rural economic development. In response to this challenge, South Korea has begun actively exploring the use of robotic technology to replace manual labor, to improve agricultural production efficiency, ensure food safety, and promote the sustainable development of its rural economy. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139387854/01_a9f26aad3c2ded5cd7b392c02c0a792f.jpeg) **Solution** In collaboration with a certain agricultural robotics company in South Korea, an advanced **transport robot solution** has been developed. This solution utilizes "**optical sensors + cameras + ultrasonic sensors**" to develop autonomous transport robots, which follow workers to collect agricultural products and automatically travel back and forth to transport them to colle --- ## RK3588 + FPGA + Sophgo BM1684X: High-Performance AI Edge Computing Box for Video Analytics, Image Vision, and More - URL: https://intl.sienovo.cn/blog/139362678 - Date: 2024-06-02 - Tags: #RK3588, #SophonBM1684X, #FPGA Powered by the RK3588 (quad-core A76 + quad-core A55), with a CPU clock speed of up to 2.4GHz, delivering 1MB L2 cache and 3MB L3 cache for enhanced CPU computing performance. Offers 6TOPS AI computing power, expandable up to 38TOPS. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362678/01_d7f252bf692a9dba45571ed6b622115c.png) #### Product Specifications System Controller CPU RK3588, quad-core Cortex-A76 + quad-core Cortex-A55, 4.4GHz Chipset SOC GPU GPU Sophgo BM1684X Video Encoding Supports 1080p video encoding, H.264, VP8 formats Video Decoding Supports 8K VP9 and 4K 10-bit H.265/H.264 video decoding at up to 60fps Supports 1080p multi-format video decoding (VC-1, MPEG-1/2/4, VP8) NPU AI 6TOPS computing power, supports INT4/INT8/INT16/FP16 operations Memory Type 8GB Storage eMMC 1 x eMMC (on-board on core board), 64GB TF 1 x TF SATA 1 M.2 SATA 1 x M.2 SATA SSD Networking RJ45 2 x Gigabit Ethernet (Gbe) RJ45 Expansion M.2 1 x M.2 --- ## Domestic Phytium/Loongson/Rockchip Chips in Xinchuang Industry Applications: Financial Sector, Education Sector, Government Agencies - URL: https://intl.sienovo.cn/blog/139363008 - Date: 2024-05-31 - Tags: #Finance Government Agencies **Solution Background:** In the context of the national strategy for IT application innovation and development, government service halls need to deeply advance "Internet + Government Services" based on national independent technological capabilities. This involves accelerating the construction of a national integrated online government service platform, further implementing the innovation-driven development strategy, enhancing government network security assurance capabilities and informatization construction levels, promoting the deep application and transformative development of government services, fostering the development of strategic emerging industries, and utilizing secure and controllable information technology to strengthen cybersecurity and informatized government construction. **Solution:** Government affairs are crucial to the national economy and people's livelihoods, and both the government and the public have very high requirements for the secur --- ## Application of AI Edge Computing Boxes in Intelligent Transportation - URL: https://intl.sienovo.cn/blog/139362976 - Date: 2024-05-31 - Tags: #AI, #EdgeComputing ![image.png](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362976/01_8697699313311ce7573fbf1f761fc829.png) **Background** With economic growth, demand for transportation has surged significantly. However, road infrastructure development has progressed slowly, leading to an increasingly prominent imbalance between supply and demand in transportation. Major roads in urban centers suffer from severe traffic congestion during peak hours, which is becoming a常态化 issue and a key factor restricting sustainable urban development. **Pain Points** The quality of the transportation environment will either promote or hinder regional economic development. As road networks continue to expand, traffic violations occur frequently, making fine-grained governance and management extremely challenging. Road enforcement remains heavily reliant on manual inspection and supervision, significantly increasing operational costs while maintaining low efficiency. ![image.png](https://pub-048dcb --- ## Application of AI Boxes in Smart Gas Stations - URL: https://intl.sienovo.cn/blog/139362953 - Date: 2024-05-31 - Tags: #AI ![image.png](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362953/01_1e3c655dfdb5c7c6b912dbf3a944e5a7.png) **Background** To standardize gas station operations and ensure public safety, Article 5 of the "Safety Regulations for Gas Station Operations" (AQ 3010-2007) specifies basic requirements for fuel unloading operations, including protection against static electricity and lightning, fire prevention, personnel supervision, and prohibiting unauthorized vehicles and non-staff from entering the unloading area. **Pain Points** Currently, numerous safety hazards exist during fueling and unloading processes. These include difficulties in manual identification, challenges in post-incident evidence collection, lack of early warnings, poor management timeliness, non-compliant operations, significant safety risks, and high labor costs. ![image.png](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362953/02_43cd3f827ff35683f343fd760fbb7ce7.png) **Solution Overvie --- ## AI Inference Acceleration Card Powered by Sophon BM1684 Chip - URL: https://intl.sienovo.cn/blog/139362911 - Date: 2024-05-31 - Tags: #AI, #BigData Powered by the Sophon BM1684 chip, this computing accelerator card is designed for AI inference. It can be integrated into servers and industrial control computers, efficiently supporting all mainstream AI algorithms on the market to enable applications such as video structuring, facial recognition, behavior analysis, and status monitoring. It delivers AI empowerment to smart city, intelligent transportation, smart energy, smart finance, smart telecom, and smart industrial fields. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362911/01_f809544b429d45c56347964d1163e5c0.png) #### Product Specifications AI Chip AI Chip Sophon BM1684 CPU CPU ARM 8-core A53 @2.3GHz TPU Architecture TPU Architecture SOPHON NPU Cores NPU Cores 64 AI Computing Power FP32 (FLOPS) 2.2T INT8 (OPS) Winograd OFF 17.6T INT8 (OPS) Winograd ON 35.2T VPU Video Decoding Capability H.264: 1080P @960fps Video Decoding Resolution H.265: 1080P @1000fps Video Encoding Capability --- ## Phytium + FPGA Multi-CPU, Multi-Serial Port Fully Domestic Industrial Control Host - URL: https://intl.sienovo.cn/blog/139362841 - Date: 2024-05-31 - Tags: #AI, #FPGADev The Phytium multi-CPU, multi-serial industrial control host is a domestically developed, autonomous, and controllable solution based on the high-performance, eight-core Phytium D2000 processor platform. Equipped with domestic firmware and supporting Chinese operating systems such as UOS and Kylin, it meets the secure computing requirements of financial systems. It enables full domestication, autonomy, and control from hardware and operating system to applications, making it a flagship solution for China's financial information security control systems. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362841/01_467447ed2912848b2649ceb2609a6932.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362841/02_c2d5246aa720e26740ad1a13ccd99e70.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362841/03_079f07944b4af99123481e1be7d06bcb.png) #### Product Specifications System Configuration Processor Phytium D2000 octa-core standard versi --- ## Phytium D2000 + FPGA Cloud Terminal: Achieving Complete Domestic, Independent, and Controllable Solutions from Hardware, Operating System to Applications - URL: https://intl.sienovo.cn/blog/139362803 - Date: 2024-05-31 - Tags: #FPGADev, #PhytiumD2000 The Phytium cloud terminal is a domestically developed, independent, and controllable solution based on the high-performance 8-core Phytium D2000 processor platform. Equipped with the domestic Kunlun firmware and supporting domestic operating systems such as UOS and Kylin OS, it meets the requirements for secure domestic information processing. It achieves full domestication, independence, and control from hardware, operating system to applications, making it a flagship solution for domestic secure desktop cloud computing. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362803/01_4d0a6368107418dde95ff28c8b8c5188.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362803/02_f79c866dd4f4bd97db08e9ee62c51f04.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362803/03_df04633cc7dfe5f8eb0ce45b9f300b3f.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362803/04_98d589c61ef74889425afdac74d19128.png) #### Product Spec --- ## Loongson 3A4000 + FPGA Cloud Terminal Solution with Kunlun Domestic Firmware, Supporting UOS, Kylin, and Other Domestic Operating Systems - URL: https://intl.sienovo.cn/blog/139362728 - Date: 2024-05-31 - Tags: #FPGADev, #Loongson The Loongson cloud terminal is a domestically developed, autonomous, and controllable solution based on the high-performance quad-core Loongson 3A4000 processor platform. Equipped with Kunlun domestic firmware, it supports domestic operating systems such as UOS and Kylin. Designed to meet the requirements of secure domestic information processing, it enables full localization and control from hardware and operating system to applications, making it a flagship desktop cloud solution for China's information security. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139362728/01_603e39f575b359e4a1d8559c6ca90d74.png) #### Product Specifications System Configuration Processor Loongson 3A4000 (4-core, 1.8GHz, up to 2.0GHz) MIPS 64-bit processor BIOS 1 × 64 Mbit flash, using U-Boot / Kunlun firmware Chipset 7A1000 Memory 2 × DDR4 SO-DIMM slots, supporting up to 32GB Storage SATA 1 × SATA3.0 vertical 7-pin interface M.2 1 × M.2 2280 NVMe SSD Ethernet Chip RTL811 --- ## Sophgo BM1684 + FPGA + AI + Camera Inference Edge Computing Box - URL: https://intl.sienovo.cn/blog/139362634 - Date: 2024-05-31 - Tags: #AI, #BigData Edge AI inference has moved decisively out of the data center and onto factory floors, traffic intersections, and energy substations. The Sophgo BM1684-based edge computing box described here represents a complete hardware platform designed to run neural network workloads continuously, in harsh environments, without a cloud dependency. This post breaks down the hardware specifications, explains what each capability means in practice, and outlines the application domains this box targets. ## The Sophgo BM1684 SoC At the heart of the unit is the Sophgo BM1684, an edge AI SoC purpose-built for inference workloads. The chip pairs an 8-core ARM Cortex-A53 cluster running at 2.3 GHz with a dedicated tensor processing unit capable of **17.6 TOPS at INT8** precision. For workloads that cannot tolerate quantization error, the chip also delivers **2.2 TFLOPS at FP32**, giving developers the option to run full-precision models where accuracy is non-negotiable. INT8 quantization is the standard --- ## 【Cognex China Case Study】Nvidia/Sophon + Smart AI Camera: AI-Driven | The Future Path to Reducing EV Costs - URL: https://intl.sienovo.cn/blog/139317062 - Date: 2024-05-31 - Tags: #AI, #SmartAICamera Driven by environmental awareness, government incentives, and the development of new energy technologies, consumer demand for electric vehicles (EVs) is continuously growing, and EVs have become a crucial component of future transportation. However, the road to large-scale replacement of internal combustion engine (ICE) vehicles by EVs is still long. The biggest obstacle is the relatively high selling price of electric vehicles. Although the operating and maintenance costs of EVs are lower than those of ICE vehicles, the high purchase price still deters many potential buyers. According to Kelley Blue Book estimates, the average transaction price (ATP) for new EVs reached $61,448 at the end of last year, approximately 34% higher than comparable ICE vehicles. The two most significant cost centers for electric vehicles are batteries and labor, with lithium-ion battery packs accounting for approximately 50% of an EV's price. Therefore, EV manufacturers and battery suppliers seeking to ga --- ## [Cognex Domestic Case Study] Intelligent AI Camera Enables Accurate and Fast Automated Parcel Labeling with Machine Vision - URL: https://intl.sienovo.cn/blog/139316017 - Date: 2024-05-31 - Tags: #AI, #SmartAICamera Cognex's 3D-A1000 is a fully functional vision inspection system specifically designed for logistics applications, compatible with various sorting machines and parcel detection scenarios. It accurately detects whether parcels are present on the sorter, if parcels exceed boundary limits, empty trolley conditions, and whether any items have been left behind. Thanks to its patented 3D structured light technology, the product offers enhanced innovation to meet evolving customer demands. This article focuses on the application of the 3D-A1000 in intelligent parcel labeling and label verification within the express logistics industry, analyzing in depth the unique features and significant value of this solution. **Customer Requirements** Unlike typical scenarios where only one label on a parcel needs to be verified, this customer wanted to apply a new label to display the parcel’s actual weight, on top of an existing label already affixed to the parcel surface. However, achieving this re --- ## [Cognex China Case Study] Intelligent AI Camera: In-Depth Analysis of DataMan 380's High-Speed, Wide-Field AI Decoding Capabilities - URL: https://intl.sienovo.cn/blog/139316722 - Date: 2024-05-30 - Tags: #AI, #SmartAICamera As barcode reader technology continues to evolve, wide-field, high-speed applications have become a key development direction in the industrial reading field. Customer demand for wide-field, high-speed readers stems from their ability to significantly reduce production costs and improve operational efficiency. However, wide-field applications often involve reading multiple barcodes simultaneously, which undoubtedly increases the processing burden on algorithms and may impact reading speed. To address this challenge, Cognex has introduced the high-performance DataMan 380 series of fixed-mount readers, redefining the standard for wide-field, high-speed barcode reading. This series not only offers an expansive field of view but also leverages AI-powered imaging and decoding technologies to greatly optimize reading accuracy, ensuring stable and reliable high-speed performance. In particular, the DataMan 3816 model, with its high resolution of up to 16 megapixels and advanced AI-based bar --- ## 【Cognex Domestic Case Study】Smart AI Camera Joins Forces with OSARO to Automate Order Fulfillment for Zenni Optical - URL: https://intl.sienovo.cn/blog/139316566 - Date: 2024-05-30 - Tags: #AI, #Automation, #DevOps In the era of e-commerce, Zenni Optical, a global leader in online eyewear retail, sells over 6 million pairs of glasses annually. However, it faced a unique and complex challenge—processing orders by scanning barcodes inside eyeglass cases. Traditional manual methods had reached a process bottleneck, demanding a more automated and scalable solution. To address this challenge, Cognex partnered with robotics integrator OSARO to successfully enhance Zenni Optical’s distribution efficiency. **Customer** **Zenni Optical** ![Image](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139316566/01_c0a6ce62444898d7fb8ffc9c37fb4f19.png) Founded in 2003 and headquartered in California, USA, Zenni Optical delivers high-quality, affordable eyewear directly to consumers. With a wide variety of styles, customizable options, and strong product quality, the company has steadily grown its market share in the eyewear industry. **Challenge** **High-Speed Barcode Reading Through Semi-Transpare --- ## 【Smart AI Camera】New AI-based Imaging and Illumination Technology - URL: https://intl.sienovo.cn/blog/139316449 - Date: 2024-05-30 - Tags: #AI, #AICamera ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139316449/01_40d0c5d4d0c41d50bceea28943befeea.jpeg) **Reduce Inspection Time** **Lower Reject Rates and Costs** **Detect More Defects Faster** The Trevista CI Dome combines Cognex's patented computational imaging algorithms with structured diffuse dome illumination to deliver unparalleled topographical image quality, providing innovative solutions for inspecting both glossy and matte surfaces. This helps to: **reduce inspection time, lower reject rates and costs, and detect more defects faster**. _**1**_ **Shape from Shading (SfS) technology** captures raw intensity images and separates shape information from grayscale information to provide high-quality topographical images. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139316449/02_197621a8cb525500ef9bc996f9d11e53.jpeg) _**2**_ Compared to other CI systems, the Trevista CI Dome can capture synthetic topographical images **2x faster**, improving --- ## [Cognex Domestic Case Study] AI Vision Camera Innovation Accelerates Digital and Intelligent Transformation in Retail Logistics - URL: https://intl.sienovo.cn/blog/139316325 - Date: 2024-05-30 - Tags: #AI, #BigData Chain supermarkets and retail stores are facing challenges brought about by changing consumer shopping habits, driving demand for digital transformation in logistics systems fueled by emerging technologies. The deep integration of the logistics industry with AI-powered machine vision addresses pain points of traditional machine vision—such as slow recognition speed, high environmental requirements, and time-consuming customized deployment—significantly improving efficiency and accuracy across the logistics supply chain. This article focuses on optimizing internal logistics handling within supermarket and retail supply chains, offering insights and inspiration for similar application scenarios. Cognex’s In-Sight 2800 Detector, equipped with edge learning technology, meets the specific needs of logistics systems in retail environments. With easy-to-use AI tools, it enables multi-functional applications such as package presence detection, item sorting, and process anomaly detection. Th --- ## 【Cognex Domestic Case Study】Machine Vision Accelerates EV Battery Pack Assembly for Ansomat, Supporting Domestic Customization - URL: https://intl.sienovo.cn/blog/139315493 - Date: 2024-05-30 - Tags: #AI, #Cognex The rapid growth and intensifying competition in the electric vehicle market necessitate automotive component production, with power batteries at its core, to move towards higher levels of customization while achieving flexible production of multiple varieties and small batches. This shift places higher demands on operators, who need to quickly adapt to handling products of different types and specifications to ensure smooth and efficient production processes. Ansomat, featured in this case study, is facing demands from EV battery customers for flexible battery module configuration and fast, accurate installation. To address this, Ansomat sought a machine vision product with a low barrier to entry, short training time, and high accuracy to implement its services. Ultimately, Cognex In-Sight 3800 met these requirements. **Customer** **Ansomat** ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139315493/01_5f8e343b29f3ab6e8eb8afbfd5ddf94c.png) Ansomat is a leading pro --- ## 【ARM+Codesys Case】T3/RK3568/Raspberry Pi + Codesys Wire Winding Machine Control Solution — Motion Controller, Customization Supported - URL: https://intl.sienovo.cn/blog/139273555 - Date: 2024-05-28 - Tags: #codesys **Wire Winding Machine Control Solution** **SC Series Motion Controller** A wire winding machine is a device that winds linear material onto specific workpieces. Most electrical products require wound coils made of enameled copper wire (commonly known as magnet wire). From coil design and parameter analysis to CNC programming, automatic compensation technology, adaptive diagnosis and control throughout the entire winding process, and detection of motion interference in the wire guiding section, every step relies heavily on automation, materials science, mechanics, stacking theory, and testing theory. Wire winding machines possess all the advantages of CNC equipment—high speed, high precision, high flexibility, and a high degree of automation. Advances in the electronics industry continue to place higher demands on the CNC and servo drive systems used in winding machines. High-speed, high-precision interpolation breaks down complex automatic winding trajectories into precise servo c --- ## 【ARM+Codesys Case Study】T3/RK3568/Raspberry Pi + Codesys Lithium Battery Test Equipment Control Solution - URL: https://intl.sienovo.cn/blog/139273422 - Date: 2024-05-28 - Tags: #codesys Lithium batteries were born in the 1960s and commercialized by Sony Corporation in Japan in the 1990s. With numerous advantages such as fast charging and discharging, long cycle life, and no memory effect, lithium-ion batteries have become the primary choice for large-scale applications in today's digital products and electric vehicles. Compared to nickel-metal hydride batteries and lead-acid batteries, lithium batteries can store more electrical energy. Many familiar products today, such as new energy vehicles, personal computers, and smartphones, are major applications of lithium batteries. Lithium batteries also have stricter requirements for quality and safety. Therefore, as a critical checkpoint for battery safety, the importance of battery testing equipment is becoming increasingly prominent, with OCV (Open Circuit Voltage) testing, located at the backend of the lithium battery production line, being a key component. OCV (Open Circuit Voltage) test equipment is located in the --- ## [ARM+Codesys Case Study] T3/RK3568/Raspberry Pi + Codesys Lithium Battery Stacking Machine Solution: Achieving Efficient Production with CODESYS - URL: https://intl.sienovo.cn/blog/139273356 - Date: 2024-05-28 - Tags: #codesys Lithium Battery Stacking Machine Solution **Riding the Waves, Promoting the Development of the New Energy Industry** Lithium batteries are rechargeable batteries that achieve charging and discharging by the movement of lithium ions between the positive and negative electrodes. They offer advantages such as high energy density, high voltage, long cycle life, and no memory effect. The lithium battery industry is a rapidly developing sector supported by national policies. It has grown rapidly in recent years and is expected to continue growing in the future, with electric vehicles representing one of the most significant high-growth areas for lithium batteries. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139273356/01_db660b7ac04de8d7af3736238f146e43.png) **Lithium Batteries Have Three Main Categories of Industry Applications** **01** ****Industrial Energy Storage and Others**** UPS for communication, new energy storage power supplies, etc. **02** ****Consumer --- ## 【ARM+Codesys Case】T3/RK3568/Raspberry Pi + Codesys Motion Controller for Pillow Packaging Machine - URL: https://intl.sienovo.cn/blog/139273231 - Date: 2024-05-28 - Tags: #codesys The pillow packaging machine is a highly capable continuous packaging machine suitable for a wide range of specifications in both food and non-food packaging. It supports not only packaging with unprinted film materials but also high-speed packaging using pre-printed roll films with logos. With advantages such as high stability, high production efficiency, suitability for continuous packaging, and adaptability to multiple packaging formats, it has gained widespread adoption in the packaging industry. The motion controller serves as the core of the control system, while the high-performance Ω6 A series servo system acts as the execution component. This combination enables the packaging equipment to operate at high speeds with precise positioning, ensuring a safer and more reliable control system that meets current production requirements. **Schematic Diagram of Pillow Packaging Machine:** ![Image](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139273231/01_dd8cb461bbff4a52 --- ## [ARM+Codesys Case Study] Express Logistics Single-Piece Separator Control System Based on Allwinner T3 + Codesys - URL: https://intl.sienovo.cn/blog/139257207 - Date: 2024-05-28 - Tags: #codesys Logistics is crucial to the national economy and people's livelihoods, an indispensable part of social development. With the reform and opening up of society, industrial development has been rapid, accompanied by the swift growth of the logistics industry. The surge in business volume in e-commerce and express delivery, coupled with rising labor costs, has led to explosive growth in the automated conveying and sorting equipment market. The logistics industry is transforming from traditional methods to digitalization and intelligence, with new logistics industries benefiting from rapid upgrades driven by industrial internet, 5G, artificial intelligence, and the Internet of Things. During shopping festivals, consumers purchase large quantities of goods, merchants receive massive orders, and a huge volume of packages are dispatched. This is where logistics sorting systems play a crucial role. Logistics conveying and sorting systems are an important part of the logistics process, widely --- ## 【ARM+Codesys Case Study】Application of RK3568 + Codesys Soft PLC Solution in Electroplating Production Lines - URL: https://intl.sienovo.cn/blog/139256222 - Date: 2024-05-28 - Tags: #codesys **1 Introduction to Electroplating Production** Electroplating is a crucial process. Products treated with electroplating not only achieve improved quality but also significantly enhanced performance, while extending their service life. An electroplating production line is a complete system coordinated by an electrical control system, combining various electroplating treatment tanks, electroplating hoist movement devices, power supply equipment, circulation filtration devices, testing instruments, heating devices, air agitation devices, drainage systems, and pollution treatment devices, all according to specific electroplating process requirements. Automatic electroplating production lines reduce material consumption, alleviate human labor intensity, minimize human contact with chemical pollutants, and simultaneously improve production efficiency and quality. They also facilitate the digital and centralized management of equipment and production processes. The operation of the hoist --- ## 【ARM+Codesys Case Study】Raspberry Pi + Codesys SoftPLC Solution Applied to Filling and Capping Machines in the Packaging Industry - URL: https://intl.sienovo.cn/blog/139255838 - Date: 2024-05-28 - Tags: #codesys ARM series supports: Allwinner T3, RK3568, Raspberry Pi **Machine Model Definition: Dual-Station Capping Machine** Capping machines are primarily suitable for capping (screwing/rolling) various materials and cap specifications. Applicable to screw caps, anti-theft caps, tamper-evident caps, press-on caps, etc. Pressure can be easily adjusted, and the cap pickup position can be set according to the cap size. The structure is compact and reasonable, allowing for easy integration with other equipment to form a production line. Machine advantages: Linear design, facilitating easy and aesthetically pleasing integration into a production line. **Control Process and Key Points** ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139255838/01_77a2773720f948015a04e46f25a230e9.png) **Key Control Points:** 1. The equipment operates as part of a production line, requiring precise synchronized motion. Electronic cams are used to achieve synchronized speed and ensure capping synch --- ## [ARM+Codesys Case Study] 3C Dispensing Edge Control Solution Based on Allwinner T3 + Codesys SoftPLC: Integrating Motion Control, Vision, Laser Ranging, and Other Technologies - URL: https://intl.sienovo.cn/blog/139253217 - Date: 2024-05-28 - Tags: #codesys Vision-based Precision Dispensing Control Solution For planar dispensing applications using Cartesian mechanisms, this is a one-stop PC-based controller solution developed on the **CODESYS** software platform, including motion controller hardware and dispensing application software. The solution integrates motion control, vision, laser ranging, and other technologies, efficiently and precisely controlling the application of adhesive to the product surface or interior. Common applications include PCB pin encapsulation, red glue dispensing, chip underfill, thermal paste application, lens modules, voice coil modules, mobile phone casings, and screen dispensing. **The core of the entire control solution is the dispensing application software developed on the CODESYS software platform, which has the following main features:** **1. Integrates common dispensing process control functions to meet most dispensing application scenarios** • Dispensing paths support vision-assisted teaching an --- ## RK3568+CODESYS Runtime: Runtime Software System for Smart Automation - URL: https://intl.sienovo.cn/blog/139253094 - Date: 2024-05-28 - Tags: #Automation, #DevOps, #Codesys, #SoftPLC **CODESYS Runtime Overview** To enable hardware devices to be programmed using the IEC 61131-3 standard-based programming environment CODESYS IDE, the CODESYS Runtime System must be ported to the corresponding hardware device. The CODESYS Runtime System is an industrial-grade real-time operating system kernel. By porting the CODESYS Runtime System to a hardware platform, any embedded device or PC-based device can be transformed into an IEC 61131-3 compliant industrial controller. The CODESYS code execution mechanism is compiled execution, meaning that IEC code written in the CODESYS IDE is compiled into machine code by an integrated compiler and then downloaded to the CODESYS Runtime via Ethernet or serial port. CODESYS Runtime can leverage hardware platform resources (such as clock resources, memory resources, etc.) to process these instructions. CODESYS technical engineers are responsible for deploying CODESYS Runtime to the hardware platforms selected by customers, and we provide --- ## Nvidia Orin/Jetson +GMSL/RLINC/VbyOne/FPDLink Coaxial AI Multi-Camera Synchronized Automotive Vision Solution - URL: https://intl.sienovo.cn/blog/139237892 - Date: 2024-05-27 - Tags: #DigitalCamera, #CoaxialCamera, #MultiCameraSync In this presentation, we introduced the application of multi-camera synchronization technology in autonomous machines. A detailed explanation was provided on how to offer efficient multi-camera synchronization solutions to customers, focusing on three typical use cases: autonomous delivery robots, upgrades to controller vision sensor solutions, and humanoid robots. Furthermore, it detailed how innovative multi-camera synchronization technology can meet the demands of autonomous machines for multi-camera combined perception and precise synchronization of data from different cameras. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139237892/01_924409e16d51339902e17f27c4382ce1.png) **Multi-Camera Application in Autonomous Delivery Robots** Autonomous delivery robots, as a typical L4 autonomous driving scenario, commonly use the NVIDIA Jetson Orin platform as their core computing processor. They need to process information from various sensors simultaneously, such as lidar --- ## Nvidia Orin/Jetson + OmniVision/SONY AI Camera Automotive Vision Solution - URL: https://intl.sienovo.cn/blog/139226317 - Date: 2024-05-27 - Tags: #AI, #Nvidia ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139226317/01_d50ee15265bf95c16e530aadd69acc57.jpeg) As a technology innovation company dedicated to providing high-quality images for intelligent driving and autonomous machines, it recently announced the launch of the industry's first automotive camera module based on the latest OmniVision 8M OX08D10 sensor. This module effectively addresses the demand for higher resolution and image quality in Advanced Driver-Assistance Systems (ADAS) and Autonomous Driving (AD), supporting the intelligent upgrade of the automotive industry. **OmniVision's Latest 8-Megapixel Image Sensor** The OX08D10 is the first 8-megapixel CMOS image sensor to feature OmniVision's new 2.1-micron TheiaCel™ technology. Utilizing next-generation Lateral Overflow Integration Capacitor (LOFIC) and OmniVision's DCG™ High Dynamic Range (HDR) technology, it can accurately capture LED light sources and eliminate flicker artifacts under various driving condi --- ## NVIDIA AGX Orin/Jetson Platform + GMSL Automotive AI Vision Solution — Sony Automotive 17-Megapixel Ultra-High Resolution Front-Facing Camera - URL: https://intl.sienovo.cn/blog/139226126 - Date: 2024-05-27 - Tags: #AI, #VehicleAIVision Introducing the "17-Megapixel Ultra-High Resolution Front-Facing Camera" and the "Intelligent Driving Super Vision 5V Solution" based on this camera. This camera utilizes Sony's 17-megapixel IMX735 automotive image sensor, featuring a 120-degree horizontal ultra-wide-angle lens and excellent ultra-high-speed transmission technology. It is a revolutionary innovative product in the industry and has attracted significant attention at auto shows. **Sony 17-Megapixel IMX735 Image Sensor** The IMX735 image sensor is a new CMOS image sensor launched by Sony for automotive cameras, and it is currently the sensor chip with the highest effective pixel count in the automotive field. This image sensor achieves a breakthrough in pixel resolution, with up to 17 million effective pixels, capable of clearly capturing features of objects at extremely long distances. Unlike traditional CMOS, this image sensor uses a column-by-column horizontal signal output method, making it easier to synchronize wit --- ## NVIDIA Orin/Jetson Platform + Digital Coaxial GMSL Automotive AI Vision Solution for Automotive, Robotics, and Other Applications - URL: https://intl.sienovo.cn/blog/139225878 - Date: 2024-05-27 - Tags: #nvidia, #Camera, #VehicleAIVision Imaging and vision technology specialist has recently officially launched a series of camera products compatible with the NVIDIA DRIVE AGX Orin platform. These self-developed digital coaxial GMSL2 camera modules meet the high-quality imaging requirements of intelligent vehicles. Currently, there are 11 camera models available for the NVIDIA DRIVE AGX Orin platform. These products utilize image sensors from ON Semiconductor, Sony, and OmniVision with resolutions ranging from 2 to 8 megapixels. They support YUV/RAW data output formats and feature high dynamic range (HDR) and LED flicker mitigation (LFM). These camera products offer long-distance transmission, high data rates, and strong anti-interference capabilities, making them suitable for applications requiring long-range, low-latency, and high-quality data transmission. They have already been deployed in various vehicles, vehicle-infrastructure coordination systems, unmanned ground vehicles (UGVs), large-scale robots, and industr --- ## What are the differences between AHD, CVBS, and HDMI interfaces for an RV1126-based AI network camera? Supports 8-channel AHD cameras and real-time AI analysis - URL: https://intl.sienovo.cn/blog/139182225 - Date: 2024-05-24 - Tags: #AI, #AHDCamera ### What are the differences between AHD, CVBS, and HDMI interfaces for network cameras? What are their application scenarios? AHD, CVBS, and HDMI are different video transmission interfaces, each suitable for different application scenarios. Below are their main application scenarios: 1. AHD (Analog High Definition): AHD is an analog high-definition video transmission technology that provides high-quality image and video output. It is primarily used in surveillance systems, such as security cameras and video surveillance equipment. AHD can transmit high-definition video signals over coaxial cable, supporting long-distance transmission and real-time image display. 2. CVBS (Composite Video Baseband Signal): CVBS is a composite video baseband signal, also known as standard-definition video. It is a traditional analog video interface, typically transmitted using RCA or BNC connectors. [CVBS](http://www.icamvision.com/product/100.html "CVBS") is widely used in older televisions, VCRs, --- ## AI Server Application Case: SAS Expander Backplane, PCIe Switch Expansion Card - URL: https://intl.sienovo.cn/blog/139172574 - Date: 2024-05-24 - Tags: #CLanguage, #ProgrammingLanguage, #pcie switch **Application Case: SAS Expander Backplane** Based on SEP 81xx series chips • First 100% domestically produced SAS12G Expander backplane • 2U12-bay NVMe hybrid expansion hard drive backplane • Supports 3.5"/2.5" NVMe/SAS/SATA hard drives • Designed and developed according to standard SFF specifications • Supports SGPIO and I2C management signals • Firmware online upgrade, BMC management, fan control, etc. • Widely applied in telecommunications, finance, government, transportation, education, and other industries ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139172574/01_0c6ed0adfccd67b1722b91beff1d12aa.png)  High-density storage dedicated SAS expander backplane  30 drive bays per board  Supports 3.5"/2.5" SAS/SATA hard drives; designed per standard SFF specifications  Supports SGPIO & I²C management signal interfaces, supports HDD LED & BMC management  Compatible with mainstream market hard drives, HDD performance ≥220M --- ## Domestic AI Server Tri-Mode RAID Card, Tri-Mode HBA Card, SAS RAID Card - URL: https://intl.sienovo.cn/blog/139172517 - Date: 2024-05-24 - Tags: #RLanguage, #Server, #Database ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139172517/01_6d497756053ced62e7459098e57995f1.png) **Technical Specifications** • Host Interface: PCIe 4.0 x8 • Data Interface: SATA/SAS/PCIe Tri-Mode • Connectors: 2x8 SFF-8654, 2x M-Key M.2 (2280) • Controller: IOC 2250 • Drive Support: Up to 16+2 SATA/SAS/PCIe drives • RAID Levels: RAID 0/1/10/1E, Pass-Through • Physical Dimensions: 167.7mm × 68.9mm • Performance: 13,700 MB/s bandwidth, 3M IOPS • Typical Power Consumption: 13W\* **Key Features & Advantages** • Onboard dual M.2 slots with hot-swap support (hot-swap mechanical kit optional) • 11.7% increased heatsink surface area per fin • Ordered drive enumeration • Out-of-band management and remote maintenance via BMC • Dual Function (x16, x2 with independent management) • Supports mixed SAS/SATA and HDD/SSD configurations • Flexible and comprehensive software management tools with CLI and GUI support • Global/local hot spare, data rebuil --- ## Domestic PCIe Switch Alternative to Broadcom for AI Server IO Interconnect Chip Solutions - URL: https://intl.sienovo.cn/blog/139172423 - Date: 2024-05-24 - Tags: #pcie switch **Servers are the infrastructure for big data, artificial intelligence, blockchain, cloud computing, and the metaverse. China ships around 4 million servers annually, with projections exceeding 5 million by 2025 (according to the China Business Industry Research Institute). High-performance enterprise-grade interconnect chips control the nervous and circulatory systems of servers.** **Market Pain Point: Currently, over 95% of domestic demand is monopolized by U.S. companies such as Broadcom.** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139172423/01_f80c1e2bad5d2d354426595c4108a03f.png) **Interconnect chips = IO interconnect + network interconnect, representing the shortest board among the "four key components" of servers.** System-level perspective from complete equipment development, IC technology expertise accumulated from DSP chip R&D, and management experience gained from large-scale engineering and team leadership **have laid a solid foundation for breakin --- ## 12Gb/s SAS Expanders — SAS Expansion Chips for AI Servers and More - URL: https://intl.sienovo.cn/blog/139172372 - Date: 2024-05-24 - Tags: #SASExpander SAS Expander is a 12Gb/s Serial Attached SCSI (SAS) expansion chip supporting 48/36/24 ports, delivering high-performance, scalable, and cost-effective storage solutions. The product comes with a feature-rich software development kit (SDK), including streamlined and easy-to-use standard API interfaces that meet diverse development requirements across various application scenarios such as storage subsystems and Storage Area Networks (SANs). This significantly shortens time-to-market, reduces deployment risks and total cost of ownership (TCO), and enhances product competitiveness. • SAS/SATA dual storage interface • 12Gb/s SAS • 6Gb/s SATA • Supports EDFB bandwidth aggregation • Supports SAS wide ports • Supports partition management • Phy-based • T10-mode • Supports SXP internal virtual ports • Supports security authentication • Supports multiple boot modes • Supports port mirroring • Supports firmware upgrade • Supports SPIN UP Applications: • Scalabl --- ## PCIe 4.0 16GT/s PCIe Switch Chip for AI Servers and More - URL: https://intl.sienovo.cn/blog/139172335 - Date: 2024-05-24 - Tags: #pcie switch The PCIe 4.0 Switch chip is available in multiple configurations such as 104, 64, and 48 ports, supporting PCIe data rates of 2.5GT/s, 5GT/s, 8GT/s, and 16GT/s. It delivers a high-performance, low-latency, scalable, and cost-effective PCIe interconnect solution. The product comes with a comprehensive software development kit (SDK), featuring simple and easy-to-use standard API interfaces that meet diverse development requirements for applications in data centers, AI servers, all-flash storage, and embedded systems. This significantly shortens time-to-market, reduces deployment risks and total cost of ownership (TCO), and enhances product competitiveness. PCIe 4.0/3.0/2.0/1.0 • Link rate auto-negotiation • Configurable UP/DP on any port • P2P transfers between any DP ports • Standard and aggressive hot-plug support • GPIO/UART/I2C interfaces • PCIe error handling with AER • Lane reversal • Polarity inversion • NTB interconnect • Base switch and NT modes • SRNS, S --- ## 10G SFP Dual-Port 10 Gigabit Ethernet Controller, High-Speed Fiber Optic Network Interface Card - URL: https://intl.sienovo.cn/blog/139172287 - Date: 2024-05-24 - Tags: #Networking The 2-Port 10G SFP+ NIC is a high-speed network interface card that utilizes a PCI Express 3.0 x8 interface, supporting dual-port 10 Gigabit Ethernet. It offers advantages such as high performance, high reliability, and low power consumption, making it an ideal choice for data centers, cloud computing, virtualization, and other fields. It supports various network protocols, such as TCP/IP, UDP/IP, VLAN, etc., capable of meeting the demands of different application scenarios. In addition, it also supports technologies like SR-IOV and DCB, which can improve the efficiency and performance of network virtualization. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139172287/01_5da56e05cb976a100ae82789930c8332.png) Dual-Port 10 Gigabit Ethernet Controller • PCIe 3.0 x8 Host Interface (2.5GT/s, 5GT/s, 8GT/s) • Compatible with 10Gb/s, 1Gb/s Ethernet (SFP+/SFP) • Supports TCP/UDP Transmit/Receive Segmentation/Aggregation Offload • Supports Receive Side Scaling • Supports NIC Vi --- ## ARM+FPGA+NVIDIA AI Camera Hardware and Software Customization - URL: https://intl.sienovo.cn/blog/139150493 - Date: 2024-05-23 - Tags: #FPGADev, #ARMDev, #AI With a seasoned ISP imaging technology team and partnerships with NVIDIA, Horizon Robotics, and others, our team possesses comprehensive ISP image quality service capabilities across most of the mainstream automotive platforms available today. We are capable of independently developing image ISP and enhancement algorithms. Our team includes multiple experienced optical design experts who possess expertise in automotive module optical design. Our senior ISP imaging technology team ensures high-quality imaging performance for each of our customers' camera models. **Platform Solution Capabilities** Development of SerDes camera adapter boards/carrier boards based on original manufacturer hardware or customer-designed hardware **▼** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139150493/01_1bf08989d223ff2e98b3a81eafced418.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139150493/02_a209535da322f96126b87a8f61f92d82.png) ![](https://pub-048dcb96257f476 --- ## Camera ISP Image Quality Tuning Customization Service Based on ARM|DSP+FPGA+NVIDIA AI Platforms - URL: https://intl.sienovo.cn/blog/139150331 - Date: 2024-05-23 - Tags: #ISP Basic Framework and Algorithm Introduction ISP (Image Signal Processor), which is image processing, primarily post-processes signals output by front-end image sensors. Its key functions include linear correction, noise reduction, bad pixel correction, interpolation, white balance, automatic exposure control, etc. Relying on ISP, it can better restore scene details under various optical conditions. ISP technology largely determines the imaging quality of a camera. It can be divided into two forms: standalone and integrated. ISP firmware consists of three parts: one is the ISP control unit and basic algorithm library, another is the AE/AWB/AF algorithm library, and the third is the sensor library. The basic idea of firmware design is to provide the 3A algorithm library separately. The ISP control unit schedules the basic algorithm library and the 3A algorithm library. Meanwhile, the sensor library registers function callbacks with both the ISP basic algorithm library and the 3A algorit --- ## ARM|DSP+FPGA+NVIDIA AI Custom Cameras - URL: https://intl.sienovo.cn/blog/139150141 - Date: 2024-05-23 - Tags: #FPGADev, #ARMDev, #AI Xinmai possesses high-performance, full-stack camera capabilities: mastering optical design for automotive modules with multiple experienced optical design experts; possessing extensive hardware design experience for automotive camera modules; mastering ISP image tuning capabilities for most automotive platforms on the market, and capable of independently developing image ISP and enhancement algorithms; in terms of manufacturing process, capable of 8-megapixel module production, assembly, calibration, and testing. We can provide customers with a series of high-quality services including camera design, manufacturing, driver development, and image ISP. We offer customized services according to customer needs. We collaborate deeply with mainstream platforms such as NVIDIA, HiSilicon, Qualcomm, Horizon Robotics, and Black Sesame Technologies to provide customers with professional image ISP services based on various SoCs. Currently, we have provided high-quality products and services to ov --- ## GMSL Image Acquisition Card, Suitable for Unmanned Vehicles, Autonomous Driving, Autonomous Machines, Data Acquisition, and Other Scenarios, Supports Customization - URL: https://intl.sienovo.cn/blog/139149499 - Date: 2024-05-23 - Tags: #GSML Based on various The Series 2nd Generation GMSL Image Acquisition Card (hereinafter referred to as **2nd Gen Image Acquisition Card**) is an independently developed FPGA-based high-speed image product. Compared to the 1st Gen card, the 2nd Gen Image Acquisition Card, due to the adoption of PCIe Gen3 technology, has seen a multiple increase in both speed and bandwidth. This image acquisition card can connect to GMSL cameras, offering advantages such as high frame rate, high speed, and low latency, widely applied in unmanned vehicles, autonomous driving, autonomous machines, data acquisition, and other scenarios. Industrial PC platform. Plug in the [Tengyun] Series GMSL Image Acquisition Card, and the acquisition card can connect to all vehicle cameras. Each card can support 8 GMSL camera inputs, supporting up to 8-megapixel 30fps. Simultaneously, it can connect to GPS or PTP for time synchronization. Timestamped data can be transmitted via the PCIe Gen3 interface with low latency a --- ## Domestic Alternative to NI: USB-6003, 8 AI (16-bit, 100 kS/s), 2 AO (5 kS/s/ch), 13 DIO USB Multifunction I/O Device - URL: https://intl.sienovo.cn/blog/139122705 - Date: 2024-05-22 - Tags: #linux, #DevOps, #Server ## Domestic Alternative to NI: USB-6003, 8 AI (16-bit, 100 kS/s), 2 AO (5 kS/s/ch), 13 DIO USB Multifunction I/O Device The USB-6003 is a low-cost multifunction DAQ (Data Acquisition) device that provides a cost-effective alternative to National Instruments (NI) products. In this article, we will explore the features and capabilities of the USB-6003, including its analog I/O, digital I/O, and 32-bit counter. ### Key Features The USB-6003 offers the following key features: - 8 analog inputs (AI) with 16-bit resolution and a sampling rate of 100 kS/s - 2 analog outputs (AO) with a sampling rate of 5 kS/s per channel - 13 digital I/O (DIO) lines - A 32-bit counter - Screw-terminal connectivity for easy connection of sensors and signals - Included NI-DAQmx driver and configuration utility for simplified configuration and measurements ### Applications The USB-6003 is suitable for a variety of applications, including: - Simple data logging - Portable measurements - Academic laboratory --- ## 【NI Alternative】USB‑6363, 32-Channel AI (16-Bit, 2 MS/s), 4-Channel AO (2.86 MS/s), 48-Channel DIO, USB Multifunction I/O Device - URL: https://intl.sienovo.cn/blog/139122608 - Date: 2024-05-22 - Tags: #NIAlternative, #DAQCard ## Overview The USB‑6363 is a high-performance USB multifunction data acquisition (DAQ) device from National Instruments, offering 32 channels of analog input at 16-bit resolution and up to 2 MS/s aggregate throughput, 4 channels of analog output at 2.86 MS/s, and 48 channels of digital I/O — all in a single bus-powered USB form factor. For engineers evaluating NI alternatives or building new DAQ systems, understanding exactly what the USB‑6363 delivers helps clarify the benchmark any replacement must meet. ## Analog Input Subsystem The 32 analog input channels are multiplexed into a single 16-bit successive-approximation ADC. The 2 MS/s figure is the aggregate sample rate across all active channels, so a single-channel acquisition runs at the full 2 MS/s while a 16-channel scan runs at roughly 125 kS/s per channel. Input ranges are software-selectable, and the analog front end supports both single-ended and differential configurations — reducing the effective channel count to 16 di --- ## 【NI Domestic Alternative】USB-6366, 8-Channel AI (16-bit, 2 MS/s), 2-Channel AO (3.33 MS/s), 24-Channel DIO, USB Multifunction I/O Device - URL: https://intl.sienovo.cn/blog/139122539 - Date: 2024-05-22 - Tags: #NIAlternative, #SyncSamplingDAQ, #DAQCard ## A Drop-In Domestic Alternative to the NI USB-6366 Multifunction DAQ Device For test engineers and system integrators who have built workflows around National Instruments' USB-6366, sourcing a domestic Chinese alternative has historically meant compromising on either performance or software compatibility. The USB-6366 occupies a well-defined niche: simultaneous-sampling, high-throughput analog acquisition with enough digital and counter resources to handle real control loops and automated test sequences in a single USB-connected module. This post walks through the key technical capabilities of the USB-6366 architecture and explains what to look for when evaluating a domestic substitute. ## What Makes the USB-6366 Distinctive Not all DAQ devices sample their analog input channels simultaneously. Many lower-cost designs use a single ADC with a multiplexer, sequencing through channels one at a time. The USB-6366 uses **simultaneous sampling**, meaning every analog input channel is di --- ## 【NI Domestic Alternative】USB‑6211, 16 AI (16-bit, 250 kS/s), 2 AO (250 kS/s), 4 DI, 4 DO USB Multifunction I/O Device - URL: https://intl.sienovo.cn/blog/139122089 - Date: 2024-05-22 - Tags: #NIAlternative, #DAQCard ## NI Domestic Alternative: USB‑6211 Multifunction I/O Device The USB‑6211 is a multifunction DAQ (data acquisition) device that offers a range of features and capabilities for various applications. In this article, we will explore the key features and benefits of the USB‑6211, as well as its suitability for different use cases. ### Key Features and Benefits The USB‑6211 provides analog I/O, digital inputs, digital outputs, and two 32-bit counters. It features an onboard amplifier specifically designed for fast settling times at high scan rates, making it suitable for applications that require high-speed data acquisition. The device also employs streaming technology to enable DMA-like high-speed bidirectional data transfer over USB. ### Applications and Use Cases The USB‑6211 is ideal for a variety of test, control, and design applications, including: * Portable data logging: The USB‑6211's compact size and high-speed data transfer capabilities make it an excellent choice for por --- ## 【NI国产替代】USB‑6212，16个AI（16位，400 kS/s），2个AO (250 kS/s)，最多32个DIO USB多功能I/O设备 - URL: https://intl.sienovo.cn/blog/139122025 - Date: 2024-05-22 - Tags: #NIAlternative, #DAQCard The USB‑6212 is one of NI's most widely deployed mid-range USB DAQ devices, offering a practical balance of channel count, resolution, and sampling speed in a bus-powered form factor. This post breaks down the hardware specifications, key architectural features, and the typical application scenarios where the USB‑6212 — or a pin-compatible domestic alternative — fits best, helping engineers evaluate whether this class of device meets their acquisition requirements. ## Device Overview and Positioning The USB‑6212 sits in NI's M Series DAQ family, targeting engineers who need genuine 16-bit resolution and multi-hundred-kilosamples-per-second throughput without committing to a PCI/PCIe chassis. Being bus-powered over USB means it can be deployed in field rigs, vehicle test benches, and lab stations with equal ease — no external power brick required. Its headline figures are: - **16 analog input (AI) channels** at **16-bit resolution** and up to **400 kS/s** aggregate scan rate - **2 a --- ## [NI Domestic Alternative] PXI-6133 Multifunction Data Acquisition Device, 8 AI Channels (14-bit, 2.5 MS/s/ch), 8 DIO Channels, PXI Multifunction I/O Module - URL: https://intl.sienovo.cn/blog/139121915 - Date: 2024-05-22 - Tags: #DAQCard, #NIAlternative ## 8 AI Channels (14-bit, 2.5 MS/s/ch), 8 DIO Channels, PXI Multifunction I/O Module The PXI-6133 is a simultaneously sampling, multifunction data acquisition device designed for high-speed, precision measurement applications. This article introduces the device's core capabilities and the growing ecosystem of domestic Chinese alternatives targeting engineers who need NI-compatible DAQ performance without the cost or supply-chain dependencies of imported instrumentation. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139121915/01_c7f4b1f7ae6e3516ccb0ffb01c09b7c7.png) ## What Is the PXI-6133? The PXI-6133 is a PXI-form-factor data acquisition module originally developed by National Instruments (now NI, a part of Emerson). It occupies a single PXI slot and connects to a PXI chassis backplane, making it part of a modular, rack-based test system architecture widely used in aerospace, defense, telecommunications, and research laboratories. The device provides: - **8 analo --- ## 【Domestic NI】PXIe-6124 Multifunction DAQ Device, 4-Channel AI (16-Bit, 4 MS/s/ch), 2-Channel AO, 24-Channel DIO, PXI Multifunction I/O Module - URL: https://intl.sienovo.cn/blog/139112214 - Date: 2024-05-22 - Tags: #DigitalIntelligence ## PXIe, 4-Channel AI (16-Bit, 4 MS/s/ch), 2-Channel AO, 24-Channel DIO, PXI Multifunction I/O Module The PXIe-6124 is a simultaneously sampled multifunction DAQ device designed for various applications in the telecommunications industry, ultrasonic and sonar testing, and high-energy physics. As a user of this device, it's essential to understand its capabilities and limitations to ensure optimal performance. In this article, we will explore the features and functionalities of the PXIe-6124 and provide guidance on how to set it up and use it effectively. ### Key Features of the PXIe-6124 The PXIe-6124 is a multifunction DAQ device that provides: * Analog I/O (AI) with 4 channels, 16-bit resolution, and a sampling rate of 4 MS/s per channel * Analog output (AO) with 2 channels * Digital I/O (DIO) with 24 channels * Two 32-bit counters for timing and triggering * Analog and digital triggering capabilities ### Applications of the PXIe-6124 The PXIe-6124 is suitable for a w --- ## [NI Domestic Alternative] PCIe-6374 Synchronous Sampling Multifunction DAQ Device, 4 AI Channels (16-bit, 3.5 MS/s/ch), 2 AO, 24 DIO, Multifunction I/O Device - URL: https://intl.sienovo.cn/blog/139111454 - Date: 2024-05-22 - Tags: #SyncSamplingDAQ ## Overview The PCIe‑6374 is a synchronous sampling multifunction data acquisition (DAQ) device designed for high-speed, precision measurement applications. With 4 analog input channels running at 3.5 MS/s per channel simultaneously, 2 analog outputs, 24 digital I/O lines, and four 32-bit counters, it represents a capable PCIe-bus instrument targeting engineers who need simultaneous multi-channel acquisition without inter-channel skew. This post covers the device's architecture, key capabilities, and the range of industries where it sees deployment — along with context for evaluating domestic alternatives in the NI ecosystem. ## Hardware Architecture The PCIe‑6374 sits in the PCIe x1 or x4 slot of a standard desktop or embedded PC, giving it direct, low-latency access to system memory through DMA transfers. The card's analog front end provides **4 simultaneously sampled AI channels at 16-bit resolution and up to 3.5 MS/s per channel** — a spec that distinguishes it from multiplexed --- ## [Domestic Alternative to NI] PXIe-7890 Hardware-in-the-Loop Simulation, 8 AO, 16 Low-Latency AO, 64 DIO, FlexRIO Multifunction I/O Module - URL: https://intl.sienovo.cn/blog/139110584 - Date: 2024-05-22 - Tags: #FPGADev, #DAQCard, #NIAlternative, #PXIe-7890 ## A Domestic Alternative for PXI-Based HIL Testing: Inside the PXIe-7890 FlexRIO Multifunction I/O Module Hardware-in-the-Loop (HIL) simulation sits at the heart of modern power electronics validation — and until recently, NI's FlexRIO family had few credible domestic competitors in the Chinese market. The PXIe-7890 changes that calculus. This article walks through the module's architecture, explains why each I/O resource matters for signal-level inverter HIL, and describes how the card is positioned for ECU verification and validation workflows. ## What the PXIe-7890 Is Built For The PXIe-7890 is a PXI Express multifunction I/O module designed specifically for **signal-level inverter Hardware-in-the-Loop (HIL)** applications. In a signal-level HIL setup, the real-time simulator must reproduce the fast, low-latency analog signals that an Electronic Control Unit (ECU) would receive from physical sensors and actuators — pulse-width modulation feedback, resolver signals, current sense --- ## Building Modern Smart Industry - Intelligent, Digital, Automated Energy Saving and Emission Reduction - URL: https://intl.sienovo.cn/blog/139107682 - Date: 2024-05-22 - Tags: #DigitalIntelligence ### Building Modern Smart Industry - Intelligent Energy Saving and Emission Reduction Following the design principle of "Integrated Energy Management", it integrates energy production and consumption information from various urban sectors (such as industry, transportation, construction, etc.), and provides an "integrated" comprehensive energy management platform for three types of entities: city governments, enterprises, and the public, thereby promoting urban energy saving, emission reduction, and energy balance. * #### [Smart Data Analysis](https://www.decomen.cn/jn/101.html "智能分析数据") * #### [Smart Data Analysis](https://www.decomen.cn/jn/100.html "智能分析数据") * #### [Implementation Plan Architecture Diagram](https://www.decomen.cn/jn/99.html "实施方案架构图") ### Revitalizing Rural Smart Agriculture - Building Smart Irrigation Systems Project Background The smart water-saving irrigation solution is applied in this Wangcheng Smart Water-Saving Irrigation Demonstrat --- ## 4U Dual-Xeon Ruggedized Server with High Integration, Enhanced Cooling, Stable Performance, and Easy Maintenance - URL: https://intl.sienovo.cn/blog/139074888 - Date: 2024-05-22 - Tags: #Server, #DevOps 1. Product Introduction 1.1 Product Overview The 4U dual-processor Xeon ruggedized server serves as an information processing server capable of loading application software and performing functions such as data processing and information exchange. It features high integration, efficient heat dissipation, stable performance, and convenient maintenance. Its environmental adaptability and electromagnetic compatibility comply with national standards. 1.2 Product Images ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139074888/01_5b92e21b3375d3f2b7b1d6278304535d.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139074888/02_37e7f8cd5ac6029b8bd62177968c8258.png) 1.3 Coating Exposed surfaces of the chassis are coated. The enclosure shall be ice gray (GY09) as specified in GB/T 3181-2008, with a textured powder coating finish. Markings and characters shall also conform to GB/T 3181-2008. 1.4 Standardization Requirements - Product development shall f --- ## Rugged Industrial PCs in ESOP Workstations, MES Workstations, Food Processing Production Line Workstations, and Equipment Information Collection - URL: https://intl.sienovo.cn/blog/138010825 - Date: 2024-05-22 - Tags: #AI, #DataAcquisition, #EdgeComputing ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138010825/05_4299c683f3cec5fde609806ff48dd6dc.jpeg) **Workstation Industry Applications** **Project Background** E-SOP is a management information platform that digitizes work instructions and provides unified management and centralized control. The ESOP terminal is a compact, full-featured, and cost-effective industrial PC. It connects to the MES system via network at the upper layer and to a display at the lower layer to show work instructions. The ESOP control terminal is characterized by its stability and durability, making it suitable for 24/7 continuous operation in factories. **Solution Requirements** ● Unfixed on-site workstations, complex locations, and demanding installation conditions. ● Factories operate 24 hours a day, so workstations must support uninterrupted operation. ● Requires both wired and wireless communication capabilities. **Solution** The provided solution includes: 1. Embedded Industrial PC + I --- ## Application of the XM-3288A Smart Terminal Motherboard in Hospital Triage and Queuing Systems - URL: https://intl.sienovo.cn/blog/139091993 - Date: 2024-05-21 - Tags: #IoT, #QueueCallMachine The triage and queuing display screens, powered by the XM-3288A smart terminal motherboard, are designed to show patient queue information and doctor work status. They offer advantages such as patient convenience, enhanced hospital image, improved management efficiency, better doctor-patient relationships, and cost savings. This system effectively addresses issues like disorganized patient visits, cumbersome consultation processes, noisy environments, and unbalanced doctor workloads, thereby significantly improving hospital service quality and efficiency. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139091993/01_0d6b1307bc0faaafb1754eefbe16dad4.jpeg) **Motherboard Solution Advantages** The core motherboard of this solution is the XM-3288A smart terminal motherboard. It is a high-performance, graphically powerful, feature-rich, and mature and stable motherboard, enabling terminal devices to stably and smoothly implement functions such as triage information display --- ## High-Extensibility Portable 1553B Bus Tester, Supports Kylin OS - URL: https://intl.sienovo.cn/blog/138853856 - Date: 2024-05-21 - Tags: #Networking, #MILSTD1553BTester The handheld portable 1553B bus tester is a modular, customizable test instrument that utilizes the PXIe expansion slots of a customized platform to embed self-developed high-performance T-series dedicated 1553B test cards, and integrates advanced protocol analysis and test software FP-1553B Pro and FP-5186. The basic configuration allows for 1553B signal waveform acquisition (with a software oscilloscope), data monitoring, fault diagnosis, cable detection, data recording, fault injection, signal diagnostic analysis and localization, and BC/RT validity testing. It can also detect ambient temperature. This instrument is suitable for design evaluation, production debugging, and routine maintenance of high-reliability, high-stability equipment in the design, test, and production departments of industries such as aviation, aerospace, weaponry, and shipbuilding. The system offers strong extensibility, with 4 PXIe and 5 MiniPCIe expansion slots capable of integrating various functional ca --- ## Dual Intel Xeon Gold High-Performance Server Motherboard with High-Reliability, Fully Ruggedized Features for Hyper-Converged Computing - URL: https://intl.sienovo.cn/blog/139075105 - Date: 2024-05-20 - Tags: #Server, #DevOps 1. Product Introduction 1.1 Product Overview This is a dual-CPU motherboard designed around the Intel Xeon Gold series processors, compliant with commercial EEB motherboard specifications, specifically engineered for high-performance, fully ruggedized servers. It integrates 64GB DDR4 memory with surface-mounted memory chips and provides abundant high-strength I/O interface connectors (6 SATA 3.0, USB 3.0, Gigabit Ethernet ports, VGA, and RS232 interfaces). Featuring high reliability, full ruggedization, high performance, and rich interfaces, this motherboard serves as the core platform for high-reliability, fully ruggedized hyper-converged computing servers. Motherboard dimensions: 304.8\*295\*2.4mm. 1.2 Product Images ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139075105/01_12dc6186a3ce3a2c6948202109e79334.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139075105/02_520733d6d911c542dd35976f3b513551.png) 2. Key Features and Performance --- ## Dual-Socket VPX Gold Xeon High-Performance Server Module for High-Reliability, Fully Ruggedized Hyper-Converged Computing Server Scenarios - URL: https://intl.sienovo.cn/blog/139075012 - Date: 2024-05-20 - Tags: #Server, #DevOps 1. Product Introduction 1. Product Overview This is a dual-Xeon VPX module designed based on Intel Xeon Gold series processors. It utilizes high-speed connectors compliant with the VPX specification and is specifically engineered for high-performance, fully ruggedized servers. It features 128GB of soldered DDR4 memory and offers a rich set of high-strength I/O interfaces (6x SATA 3.0 / USB 3.0 / Gigabit Ethernet electrical ports / VGA interface / RS232 interface). This motherboard is characterized by high reliability, full ruggedization, high performance, and abundant interfaces, making it suitable as the core motherboard for high-reliability, fully ruggedized hyper-converged computing servers. The motherboard dimensions are 233.35mm (width) * 270mm (length), with a board thickness of ≤2.4mm. 1. 1. Product Photos ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139075012/01_8e61c586c46b7eb60ccf1e7b23b18729.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9. --- ## Essential "Hardcore Equipment" for Digital Business Operations — Intelligent Payment and Checkout Solution. Supports HarmonyOS and Full Domestic Production, Customizable - URL: https://intl.sienovo.cn/blog/139057110 - Date: 2024-05-20 - Tags: #POSTerminal, #IoT In recent years, with the rapid development of emerging technologies such as IoT, artificial intelligence, and 5G, the offline retail industry has begun its digital transformation supported by technology, improving store operation capabilities and business efficiency to achieve cost reduction and enhanced productivity. To address payment challenges faced by small and micro merchants, this intelligent payment solution—centered on payment technology and featuring aggregated payment capabilities, a powerful hardware platform, and professional after-sales support—has become the essential "hardcore equipment" for rapidly achieving digitalized operations. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139057110/01_80aadcdddd8b12acee42bffee9642ef3.jpeg) Centered on facial recognition payment, this solution offers the following advantages: **1** Powerful Aggregated Payment Functionality The intelligent payment system aggregates multiple payment methods including facial re --- ## High-Cost-Performance Professional Core Motherboard for Smart POS Cash Register Terminals, Low Power Consumption + High Expandability - URL: https://intl.sienovo.cn/blog/139056765 - Date: 2024-05-20 - Tags: #POSTerminal Smart cash registers help physical stores upgrade their services, effectively improving checkout efficiency and increasing revenue. As a result, they are widely used in industries such as retail, catering, beauty, specialty stores, gas stations, automotive services, and education & training. To better serve partners, we have launched several professional Android motherboards tailored for smart cash register applications. These motherboards offer advantages such as low power consumption and rich interface options, along with comprehensive support including system, software, and peripherals, making them highly popular in the market. * * * [Single-Screen Smart POS] ![Image](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139056765/01_8f911c295ac6824cc9a992676fea6093.jpeg) [Double-Screen Smart POS] **XM-3566SF** **Motherboard Positioning:** Mini form factor, primarily designed for single-screen POS terminals. **Motherboard Dimensions:** 100\*80mm, board thickness: 1.6mm ! --- ## What Role Do IoT Gateways Play in Elevator On-Demand Maintenance Solutions? Elevator IoT Gateway - URL: https://intl.sienovo.cn/blog/139056532 - Date: 2024-05-20 - Tags: #IoT To reduce elevator failures, prevent accidents, and ensure personal and property safety, IoT-based elevator on-demand maintenance has been progressively implemented in many regions across the country. This approach enables predictive identification of elevator safety hazards, making problem-solving more scientific, targeted, and precise, thereby effectively enhancing elevator operational safety. So, as a crucial component of the elevator on-demand maintenance solution, what role do IoT gateways play in this scheme? ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/139056532/01_5f137883d745a44e1f566080c51fb373.jpeg) Elevator IoT gateways are primarily used for real-time monitoring and display of elevator operating status. By installing the IoT gateway on the elevator car door, and utilizing its built-in high-precision sensors such as door magnetic sensors, current sensors, and human presence sensors, it can real-time monitor and collect elevator operating status data. * --- ## Avionics AFDX High-Performance ARINC664 Network Interface Card. This product supports application requirements such as ARINC664 network simulation, testing, and data analysis. - URL: https://intl.sienovo.cn/blog/138862658 - Date: 2024-05-14 - Tags: #AFDX It is a standard full-height, half-length PCI specification, high-performance ARINC664 network interface card. This product supports application requirements such as ARINC664 network simulation, testing, and data analysis; it supports 2 ARINC664 ports, using RJ45 connectors, with each port having up to 64K buffer. The two ports can be used as two independent ports or as redundant ports. The product integrates an IRIG-B system clock, providing multi-node clock synchronization, which facilitates its use in multi-node simulation systems. Transmission supports configuration of up to 128 transmit Virtual Links (VLs) and 1024 transmit ports; reception supports configuration of up to 512 receive VLs and 4096 receive ports. It not only supports Queuing, Sampling, and SAP ports, but also SNMP and 615A loading protocols, among others. As a standard full-height, half-length PCI card, it can be conveniently applied in various PCs and industrial computers with PCI slots. This product supports hi --- ## Avionics AFDX Card: Standard PMC Specification, High-Performance ARINC664 Network Interface Card - URL: https://intl.sienovo.cn/blog/138862551 - Date: 2024-05-14 - Tags: #AFDX This is a standard PMC specification, high-performance ARINC664 network interface card. The product supports application requirements such as ARINC664 network simulation, testing, and data analysis; it supports 2 ARINC664 ports in RJ45 plug form, with each port having up to 64K cache. The two ports can be used as two independent ports or as redundant ports. The product integrates an IRIG-B system clock, providing multi-node clock synchronization, which facilitates its use in multi-node simulation systems. For transmission, it supports configuring up to 128 transmit VLs and 1024 transmit ports; for reception, it supports configuring up to 512 receive VLs and 4096 receive ports. It not only supports Queuing, Sampling, and SAP ports, but also SNMP and 615A loading protocols, among others. As a standard PMC specification card, it can be conveniently applied in various hosts with PMC slots, such as CPCI/VME/VPX embedded systems. The product supports high-speed forwarding ports, reducing --- ## PXI/PXIe ARINC 429/717 Avionics Bus Adapter Card - URL: https://intl.sienovo.cn/blog/138854216 - Date: 2024-05-14 - Tags: #A429AvionicsBus The A429 is a standard PXI/PXIe x1 multi-protocol bus adapter card. This product supports up to 36 ARINC 429 channels, or 32 ARINC 429 channels plus 4 ARINC 717 channels. Each ARINC 429 and ARINC 717 channel can be software-configured for reception or transmission, meeting the communication, testing, and data analysis application requirements for ARINC 429 and ARINC 717 buses. Each ARINC 429 channel of this product supports standard ARINC 429 data rates and custom rates, with custom data rates reaching up to 300kbps. It supports functions such as bus signal acquisition, error injection, IRIG-B DC encoding/decoding, IRIG-B AC hardware decoding, automatic data rate detection, data playback, and Label or SDI message filtering. Transmit channels support periodic and aperiodic messages, with period size and message interval time being software programmable. Receive channels simultaneously support three message caching modes: queue, sampling, and multi-channel buffering. Interrupt queues --- ## Next-Generation PCI Specification A429/717 Avionics Bus Adapter Card - URL: https://intl.sienovo.cn/blog/138854110 - Date: 2024-05-14 - Tags: #A429AvionicsBus A multi-protocol bus adapter card based on the third-generation PCI bus specification, supporting ARINC 429 and ARINC 717. This product supports up to 42 ARINC 429 channels, or 40 ARINC 429 channels plus 2 ARINC 717 channels. Each ARINC 429 and ARINC 717 channel can be software-configured as transmit or receive, meeting application requirements for communication, testing, and data analysis on ARINC 429 and ARINC 717 buses. The ARINC 429 channels support standard ARINC 429 data rates as well as user-defined rates up to 200 kbps. The card supports both periodic and non-periodic message transmission, with programmable period sizes and message intervals via software. It offers three message buffering modes: queue, sampling, and multi-channel caching. Additionally, it supports programmable bus signal amplitude and bus signal capture functions. The ARINC 717 channels support two encoding schemes: HBP and BPRZ. Multiple data rates are available, including 64 wps, 128 wps, 256 wps, 512 wps, --- ## PCIe 1M/4M 1553B Bus Adapter Card - URL: https://intl.sienovo.cn/blog/138854002 - Date: 2024-05-14 - Tags: #1553b The 1553B is a 1553B bus adapter card developed for test and simulation applications, supporting 1M and 4M bus speeds. The product offers 1 to 4 dual-redundant 1553B channels, supporting single-function/full-function operation. It utilizes high-speed SRAM and large-capacity DDR3 cache, which improves the response performance of bus messages, enabling better support for multi-channel full-function applications. Additionally, new features have been added, including software-configurable direct or transformer coupling, programmable bus signal amplitude, protocol error injection and detection, digital signal generator, and bus signal waveform monitoring, which can be used for testing, verification, and troubleshooting of the 1553B bus. The XM1553B adopts the latest generation 1553B protocol processor, featuring advanced BC, RT, and BM functionalities. It can not only be used as a 1553B bus communication adapter but also in conjunction with FlightPack-1553B software to achieve real-time a --- ## PXI/PXIe 1553B Bus Test Module - URL: https://intl.sienovo.cn/blog/138852703 - Date: 2024-05-14 - Tags: #1553b A 1553B bus adapter card specifically developed for GJB5186 testing, supporting 4Mbps and 1Mbps bus speeds. This product provides 2 dual-redundant 1553B channels, 1 dedicated test channel, and 2 cable test channels. In addition to features such as programmable coupling methods, programmable bus signal amplitude, common-mode voltage injection, and bus signal waveform acquisition, the new generation TM53x card also adds a high-speed DAC to enrich and improve GJB5186 electrical performance testing, as well as cable continuity and cable short-circuit test functions. The PXI/PXIe utilizes a self-developed, state-of-the-art 1553B protocol processor, featuring advanced BC, RT, and BM capabilities. When used with FlightPack 5186 (FP-5186) test software, it enables real-time analysis and simulation of 1553B bus data, as well as test applications for specific GJB5186 test subsets. The PXI/PXIe can be used in PXI and PXIe chassis to form dedicated avionics bus test instruments and build various --- ## XM1394-PCI - 1394 Avionics Single-Node/Three-Node Simulation Card - URL: https://intl.sienovo.cn/blog/138844032 - Date: 2024-05-14 - Tags: #FPGADev PCI bus Mil-1394B full-featured card, supporting 1 node (CC) with all CC, RN, and BM functionalities.       The 1394 full-featured card is used to simulate CC, RN, and BM node functionalities within a 1394 bus. It supports features such as bus topology viewing, data logging, and error injection, enabling the construction of a 1394 bus network and data transmission across it. The core functionality of the 1394 three-node simulation card is implemented based on an FPGA, which handles the parsing of the 1394B bus standard AS5643 protocol. This design offers fast FPGA logic function startup, strong protocol processing capability, small size, and light weight, meeting the product's testing requirements in laboratory environments. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138844032/01_3fcd89aea20e7a3f6589b5ea2b12610b.png) ·   Supports 1394 network communication, using the standard SAE AS5643 protocol format; ·   Employs transformer coupling to provide Beta mode 1394B --- ## XM1553B Avionics Bus Protocol Module (Built-in Bus Transceiver) - URL: https://intl.sienovo.cn/blog/138843134 - Date: 2024-05-14 - Tags: #1553b It is a high-performance 1553B module with a 4Mbps data rate, compatible with 1Mbps communication speed, supporting single function (BC, or RT, or BM) and multi-function (BC & 1 RT & BM). This module integrates 32K×16bit dual-port RAM and a 4Mbps 1553B transceiver internally. The host interface supports serial port and SPI. The serial port is a TTL-level UART interface, which can connect to external transceivers to support RS232/RS422/RS485, with 1553B bus rates up to 4Mbps (compatible with 1Mbps). The SPI interface supports a maximum synchronous clock of 22MHz. The XM1553B-M utilizes a self-developed intelligent 1553B protocol processor, which enables precise scheduling, real-time transmission/reception, and response for 4Mbps 1553B bus messages. Specifically, for applications involving sending vector words, the Condition Block of the BC function module can automatically send aperiodic messages. The RT function module can automatically clear the Service Request bit after receiving --- ## PXIe i3/i5/i7 Single Board Computer Controller - URL: https://intl.sienovo.cn/blog/138842760 - Date: 2024-05-14 - Tags: #Networking It is a main controller specifically designed for PXIe hybrid test systems, compliant with 3U 12HP PXIe specifications. This product features Intel® Core™ i3/i5/i7 4th generation high-performance processors and supports up to 16GB DDR3L memory. The system's PXI Express link configuration uses a common 4-port 4-lane mode, offering data throughput up to 8GB/s. The CX786x provides rich and flexible I/O interfaces, including two DisplayPort interfaces capable of connecting two monitors simultaneously, two USB 3.0 interfaces for high-speed external devices, two Gigabit Ethernet ports, and four USB 2.0 interfaces for other external devices or USB-interfaced instruments. The product design has undergone rigorous testing and is mature for application, capable of operating stably and reliably for extended periods. It is widely applicable in industrial automation control and military computing fields. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138842760/01_a09e9e528525ac721f --- ## Application of Rugged, Domestically Produced Industrial PCs in Laser Marking Machine Equipment Industry - URL: https://intl.sienovo.cn/blog/138024373 - Date: 2024-05-14 - Tags: #EdgeComputing, #AI ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138024373/01_5009dc283c3d2c24b559aa2d342bdc60.jpeg) ##### **Laser Marking Machine Equipment Industry Applications** **Project Background** Smart marking machine systems hold a mainstream position in the market due to their flexible recognition algorithms, high precision, and integrated processing and vision capabilities. They are primarily applied in scenarios requiring higher refinement and precision, such as processing fields like electronic components, integrated circuits, mobile communications, automotive parts, jewelry, and precision instruments. As modern precision processing equipment, laser marking machines can significantly improve production efficiency and reduce enterprise tooling and labor costs. They are suitable for various automated production line applications and intelligent upgrades, making them the optimal choice for enterprises seeking intelligent equipment upgrades. **Solution Requirements** ● Require --- ## Intelligent Centralized Remote Monitoring and Management of Substations Based on Raspberry Pi + Codesys, Supporting OEM/ODM - URL: https://intl.sienovo.cn/blog/137501317 - Date: 2024-05-14 - Tags: #AI, #RaspberryPi As the national smart grid construction continues to advance, the construction of new smart substations and the intelligent upgrading of existing substations have become an inevitable trend. To adapt to this development wave, Shenzhen Xinmai has developed an IoT integrated solution that can help achieve centralized remote monitoring and intelligent management of substations. **Achieving Intelligent Centralized Remote Monitoring and Management of Substations** Intelligent centralized remote monitoring and management of substations is achieved through means such as IoT, sensors, and computer technology. The IoT host real-time collects and monitors data from infrastructure and critical electrical equipment across the entire substation, such as temperature and humidity, heating and ventilation, fire protection, transformers, and power distribution. This data is interconnected with the substation's integrated information platform, meeting the smart substation's 24/7 demand for centralize --- ## [HarmonyOS + Domestic Rockchip] Smart Building Solution | How to Achieve Intelligent and Refined Building Management Across Multiple Scenarios? - URL: https://intl.sienovo.cn/blog/138811936 - Date: 2024-05-13 - Tags: #harmonyos, #Huawei As digitalization and intelligent technologies become increasingly integrated with work and daily life, there is growing focus on human-centric services. By leveraging digital tools and technology to meet diverse needs, the transformation of commercial buildings into smart buildings is accelerating, gradually forming a comprehensive smart building product matrix. ![Image](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138811936/01_d2f3a46dadbac3ca4cf16b9932de7639.png) **Solution Highlights** **01/Digital Signage – Brand and Information Display** Corporate culture promotion, announcements, and notices Centrally managed content via remote control Integrated visitor recognition with customized welcome messages **02/Smart Access Control – Efficient and Accurate Entry Management** Supports facial recognition and card-based access Precise access permission management for employees, whitelist users, and visitors Blacklist monitoring and real-time alerts ![Image](https:// --- ## High-Performance Motherboard Solutions for Versatile Smart Displays: Supporting HarmonyOS and Free Customization with Full Domestic Production - URL: https://intl.sienovo.cn/blog/138811817 - Date: 2024-05-13 - Tags: #IoT With the rapid development of technologies such as 5G, artificial intelligence, cloud computing, IoT, and 4K/8K ultra-high-definition video, the smart commercial display market is evolving towards intelligence, real-time interaction, and AI perception. New products and scenarios are continuously emerging, among which the Versatile Smart Display, as a new type of intelligent display, is attracting significant attention in the smart commercial display and smart home fields. It can meet various user needs such as fitness, cooking, office work, online classes, video conferencing, and binge-watching shows. Due to the adoption of advanced artificial intelligence and IoT technologies, terminal devices have higher demands for the performance of core motherboards. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138811817/01_0d6804e13322f0b5372a17a88e1c4e3b.png) To this end, VisionMEI provides its partners with higher-configuration and more cost-effective core motherboard solutio --- ## RK3568/RK3588 AI Box Solution for Smart Campus — Electronic Class Signs, Access Control, Digital Campus, Supports HarmonyOS, Free Customization Available - URL: https://intl.sienovo.cn/blog/138810480 - Date: 2024-05-13 - Tags: #Learning, #Lifestyle The smart campus solution leverages emerging technologies such as IoT and artificial intelligence to build an intelligent campus environment for teachers and students. It covers multiple scenarios including campus security, smart classrooms, attendance management, and smart canteens, delivering more humane, convenient, and efficient services across work, study, and daily life. **Solution Architecture** ![Image](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138810480/01_8a295fabe603730441ff64e47cbdcf4c.jpeg) **Key Features** Comprehensively senses the physical campus environment, seamlessly integrating the school's physical space with digital space. By leveraging computational analysis in cyberspace, it captures operational patterns of the campus and provides feedback and control over the physical environment, establishing an intelligent, open educational setting and a convenient, comfortable living environment for faculty and students. **Application Scenarios** ![Imag --- ## Application of Smart Self-Service Terminal Motherboards RK3288/RK3568 in Hotel Front Desk Self-Service Kiosk Solutions, Supporting HarmonyOS and Free Customization - URL: https://intl.sienovo.cn/blog/138809846 - Date: 2024-05-13 - Tags: #harmonyos, #Networking, #Huawei The Hotel Front Desk Self-Service Kiosk Solution is based on self-service terminals, enabling guests to complete check-in/check-out with simple operations. This significantly improves hotel operational efficiency, enhances guest experience, and reduces labor costs. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138809846/01_dc9f1e10c694bd11982593b7e431238a.jpeg) This solution addresses the following pain points of traditional front desk check-in methods: 1. High traffic and delayed reception 2. Long guest queuing times 3. Insufficient staffing during hotel peak hours 4. Guest privacy protection concerns #### ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138809846/02_b0da331dbb4fe5ba0885cdf894755405.png) **Project Business Requirements** ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138809846/03_dff096d0150fe897541cb3dde0c7eec8.png) #### #### 1. **Touchscreen Operation:** Supports touchscreen operation, allowing guests to t --- ## RK3288 Smart Terminal Motherboard Application in Smart Running Track Projects, Supporting Fully Domestic Production and Free Customization - URL: https://intl.sienovo.cn/blog/138804843 - Date: 2024-05-13 - Tags: #harmonyos, #AI Smart running tracks, launched by our partners and based on the IoT-3288A smart terminal motherboard, represent a healthy exercise method leveraging intelligent technology. Utilizing technologies such as the Internet of Things (IoT), facial recognition, and big data analysis, they monitor and collect data on people's exercise, display workout statistics including mileage and calorie consumption, and generate performance leaderboards, making public fitness more convenient, effective, and intelligent. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138804843/01_25c2b2f3b6f95b758c3ad3ee49b5b4b5.png) ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138804843/02_93f7ebadd281af51cabba56d34b97675.png) **Core Motherboard Solution Advantages** ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138804843/03_21f86ed5b3a8d8a00c74419db331ee01.png) The core motherboard of this solution is the IoT-3288A, based on the RK3288 platform, offering the followi --- ## Application of RK3568 Motherboard in Intelligent Transit LED Display Projects – Supports HarmonyOS and Full Domestic Production - URL: https://intl.sienovo.cn/blog/138804715 - Date: 2024-05-13 - Tags: #harmonyos, #Huawei #### The AIoT-3568A-based smart bus LED display enables dynamic route information presentation and voice-based station alerts, reducing instances of passengers overshooting or missing stops. It significantly improves the efficiency and quality of public transportation services, delivering a more comfortable, safer, and convenient travel experience while adding new vitality to urban development. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138804715/01_c7f96bfe4516a48618e01f01c4cd492e.jpeg) Project Requirements 1. **Information Broadcasting**: Real-time display of bus arrival times, route details, weather forecasts, news, and other relevant information. 2. **Voice Announcements**: Supports voice announcements for arriving stations, helping passengers stay informed and reducing the risk of missing stops due to smartphone usage. 3. **Emergency Alerts**: In emergency situations, the smart bus LED display can trigger built-in alarm systems to alert passengers and gui --- ## Application of High-End Smart Terminal RK3399 Motherboard in Delivery Robot Projects, Supporting Free Customization - URL: https://intl.sienovo.cn/blog/138804534 - Date: 2024-05-13 - Tags: #IoT, #Robotics A series of delivery robots based on the high-end smart terminal motherboard IoT-3399E have been developed for delivery services in various offline stores. These delivery robots enable intelligent recognition, precise delivery, automatic obstacle avoidance, autonomous scheduling systems, voice announcements, and information interaction, significantly improving service efficiency and offering consumers a more convenient and intelligent service experience. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138804534/01_8427d030a1111f931cf4fbad4636626d.jpeg) Core Motherboard Advantages The core motherboard used in the delivery robot project is the Sienovo IoT-3399E, which is based on the RK3399 hexa-core 64-bit processor. It features exceptional processing performance, high computing power, and strong expandability, offering significant advantages. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138804534/02_177e077d55dc9915a71565036624ed49.jpeg) **More Pow --- ## Application of Localized OpenHarmony OS Smart Terminal RK3568 Mainboard in Digital Class Signage Projects - URL: https://intl.sienovo.cn/blog/138804264 - Date: 2024-05-13 - Tags: #OpenSource, #harmonyos, #Huawei The digital class signage solution, featuring the localized OpenHarmony OS smart terminal mainboard AIoT-3568A and a facial recognition algorithm, supports multiple functions such as campus information publishing, facial recognition attendance, examination room management, and interactive inquiries. This helps schools achieve informatization, networking, and digitalization at the hardware level, building a smart education environment across the three dimensions of "school, teachers, and students." ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138804264/01_77af3187df2da49f06275495e3c03e69.jpeg) **Solution Advantages** **01/High-Performance Core Mainboard** This solution utilizes the high-performance core mainboard AIoT-3568A, based on the RK3568 quad-core processor. It boasts powerful core processing capabilities and excellent power consumption control technology, offering 1 TOPS of computing power. It integrates various display interfaces, Ethernet, Wi-Fi, BT, and 4 --- ## Application of All-Scenario Smart Terminal RK3288 Motherboard in Smart Waste Recycling Projects, Supporting HarmonyOS and Full Domestic Production - URL: https://intl.sienovo.cn/blog/138804067 - Date: 2024-05-13 - Tags: #harmonyos, #AI, #Huawei The smart waste recycling project launched by the all-scenario smart terminal motherboard AIoT-3588A aims to address the increasingly prominent waste disposal issues in the process of urbanization. Smart waste sorting bins feature multiple functions such as touchscreen operation, automatic weighing, categorized disposal, and electronic voice prompts. Residents can deposit waste through various methods, including sorting points cards, mobile phone QR code scanning, and facial recognition, enabling more efficient waste sorting, improving sorting accuracy, and effectively saving human resources. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138804067/01_c83b7ea58a76ab99f9f9c063d2f2645b.jpeg) #### Project Feature Requirements 1. Supports card/QR code/facial recognition for waste disposal 2. Supports waste weighing 3. Waste bin overflow alert 4. Supports voice prompts 5. Smart anti-pinch (hand protection) 6. Advertising screen displays waste sorting promotional ads, com --- ## Application of Fully Localized RK3288 Motherboard for Smart Self-service Terminals in Self-checkout Projects, Supporting HarmonyOS - URL: https://intl.sienovo.cn/blog/138803814 - Date: 2024-05-13 - Tags: #harmonyos, #Huawei The Smart Self-service Terminal Motherboard IoT-3288A has launched a self-checkout terminal, primarily targeting store checkout scenarios such as shopping malls, supermarkets, restaurants, and retail stores. After customers scan items they wish to purchase at the barcode scanning area, they can choose QR code payment, facial recognition payment, and membership/shopping card payment, significantly improving checkout efficiency, greatly reducing labor and hardware costs, and enhancing the customer shopping experience. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138803814/01_ed1eb82de1fc11cac8b8618e34d150d2.png) **Functional Requirements** 01/ Product Identification and Settlement: Customers can scan product barcodes or use RFID technology to identify products on the self-checkout machine. The system automatically reads product information and calculates prices. 02/ Aggregated Multiple Payment Methods: Supports facial recognition payment, QR code payment, bank card --- ## RK3568-based Fully Localized Identity Verification All-in-One Machine Project, Supports Customization and HarmonyOS - URL: https://intl.sienovo.cn/blog/138803440 - Date: 2024-05-13 - Tags: #RK3568, #IDVerificationTerminal The identity verification terminal solution is built around the AIoT-3568A AI motherboard as its core platform, offering comprehensive support for the system, identity recognition, and an ecosystem of other peripheral accessories. This article will delve into the project overview, application scenarios, system architecture, peripheral specifications, and testing methodologies involved in deploying a fully localized identity verification all-in-one machine. ## Project Overview ### Project Application Scenarios The identity verification terminal is designed for various application scenarios, including: 1. **Identity Verification**: Used in government agencies, enterprises, public institutions, and financial institutions to verify identities. 2. **Real-name Registration**: Facilitates real-name registration in accommodation establishments such as hotels, guesthouses, and apartments. 3. **Security Checks**: Employed at transportation hubs like train stations, airports, and ports for se --- ## RK3568-based Fully Localized Dual-screen Visitor Machine Project, Supports HarmonyOS, Supports Customization - URL: https://intl.sienovo.cn/blog/138803254 - Date: 2024-05-13 - Tags: #RK3568 The dual-screen visitor machine solution is centered around the AIoT-3568A AI motherboard, providing a robust platform for identity recognition and peripheral accessory integration. This solution is particularly relevant in various applications, including visitor registration, management, and verification across multiple sectors. In this post, we will delve into the project overview, application scenarios, and essential components of the dual-screen visitor machine, as well as the setup process and key considerations. ## Project Overview The dual-screen visitor machine is designed to enhance the visitor management process in various environments. It functions as a comprehensive system for identity verification and registration, utilizing advanced technologies to streamline operations. ### Project Application Scenarios 1. **Visitor Registration**: This system can be implemented in government agencies, enterprises, and commercial buildings to facilitate efficient visitor registratio --- ## RK3568-based HarmonyOS All-in-One Access Control Solution Project - URL: https://intl.sienovo.cn/blog/138803049 - Date: 2024-05-13 - Tags: #harmonyos, #Huawei The HarmonyOS All-in-One Access Control Solution leverages Sienovo's HarmonyOS AIoT-3568X AI motherboard, powered by the OpenHarmony operating system, to deliver a robust and secure identity verification platform. This post delves into the architecture of this solution, detailing its key components, peripheral integration guidelines, and essential steps for hardware setup and display configuration, ensuring a smooth deployment for various access control scenarios. ## Project Overview The HarmonyOS All-in-One Access Control Solution is designed for scenarios demanding high security and reliable identity verification. At its core, it emphasizes independent controllability, utilizing self-developed algorithms and domestic chips to ensure a secure and manageable system. **Project Application Scenarios:** This solution offers a comprehensive suite of features, including facial recognition, ID verification, intelligent gate control, and traceable access data, making it suitable for a wide --- ## ZYNQ Domestic Alternative - FMQL100TAI Core Board, a Fully Domestic Intelligent Heterogeneous Computing Platform Based on Fudan Microelectronics Qinglong JFMQL100TAI, Supports Customization - URL: https://intl.sienovo.cn/blog/138754383 - Date: 2024-05-12 - Tags: #FPGADev, #FMQL100TAI, #ZYNQAlternative A fully domestic intelligent heterogeneous computing platform development kit based on Fudan Microelectronics Qinglong 100TAI from Shanghai Fudan Microelectronics. This kit includes one Fudan Microelectronics Qinglong 100TAI core board and one PCIe-spec expansion baseboard. The core board of this kit integrates the minimum system for 100TAI, featuring a single JFMQL100TAI900 System-on-Chip (SoC). This single chip integrates a quad-core Processing System (PS) and FMSH Programmable Logic (PL). The chip integrates three major modules: a high-performance SoC, a large-capacity FPGA, and an AI acceleration engine. It adopts a new generation multi-core bus architecture, supporting a more powerful quad-core SoC system, extensive FPGA resources, and an AI acceleration engine with a buyi architecture. It can support up to 27.5 TOPS of computing power, with support for VPE, INT8/INT16. On the core board, the PS side features one group of 32-bit DDR3 SDRAM. Onboard are one 256Mbit QSPI Flash, o --- ## Fudan Micro FMQL45T900 ARM+FPGA+AD Fully Localized Solution, Compatible with XILINX's XC7Z045-2FFG900I (i.e., ZYNQ7045) - URL: https://intl.sienovo.cn/blog/138753851 - Date: 2024-05-12 - Tags: #FPGADev, #ARMDev, #FMSH A fully localized ARM core board based on Shanghai Fudan Microelectronics FMQL45T900. This core board integrates the minimum system of Fudan Micro's FMQL45T900 (compatible with XILINX's XC7Z045-2FFG900I) onto an 87*117mm core board. It can serve as a core module for functional expansion, enabling rapid construction of a signal platform, facilitating product development for users. The core board features DDR3 SDRAM, EMMC, SPI FLASH, Ethernet PHY chips, and more. PL-side I/O expansion is achieved through two board-to-board FMC connectors. The FMQL45T900 is a fully programmable fusion chip developed by Fudan Microelectronics. It integrates a Processing System (PS) based on a feature-rich quad-core processor and Programmable Logic (PL) on a single chip, utilizing the most advanced 28nm process technology. Coupled with corresponding development software, it enables an integrated hardware and software platform, facilitating user development, shortening development cycles, and saving produc --- ## Design Solution for Semiconductor New Energy Intelligent Equipment Controllers and Industrial Software - URL: https://intl.sienovo.cn/blog/127987768 - Date: 2024-05-11 - Tags: #HostComputer, #SemiconductorEquipment, #NewEnergyEquipment Xinmai's intelligent manufacturing solution for the engineering machinery industry deeply integrates Xinmai's proprietary information technology and enterprise digitalization technology with advanced manufacturing technology in the engineering machinery sector. It spans all stages of the entire product lifecycle, including marketing, R&D, manufacturing, and service, as well as the optimized integration of corresponding systems. This achieves digitalization, networking, and intelligence in engineering machinery manufacturing, continuously improving product quality, efficiency, and service levels, and fostering the enterprise's innovative, green, coordinated, open, and shared development. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127987768/01_dca392187e7b77aacf1b92f644218194.png) Solution Architecture The Xinmai Intelligent Equipment Business Unit is committed to providing technologies, products, and solutions for the entire smart manufacturing process, helping man --- ## ARM+FPGA-based Industrial Medical Endoscope Solution - URL: https://intl.sienovo.cn/blog/138665690 - Date: 2024-05-10 - Tags: #FPGADev ## Introduction This article describes the first installment of a multi-part series on an FPGA-based monocular endoscope positioning system for cardiac surgery simulation. The system uses a camera, SDRAM frame buffering, and real-time image processing on an FPGA to track and localize the tip of a surgical catheter inside a cardiac simulator — giving trainee surgeons coordinate feedback without requiring direct visual inspection of the heart interior. This post covers the project background, FPGA fundamentals, system design rationale, algorithm selection, and hardware module overview. --- ## 1. Background and Motivation ### 1.1 Medical Device Context Cardiovascular disease treatment is among the most commercially and clinically significant segments of the medical device industry. Cardiac assist devices — whether implantable or external, electronic or mechanical — have steadily decreased in size, making them easier to implant. At the same time, cardiac electrophysiology has emerged --- ## FPGA-Based Audio and Video Monitor and Video Interface Capture Device Applications - URL: https://intl.sienovo.cn/blog/138665596 - Date: 2024-05-10 - Tags: #FPGADev FPGA technology has become a cornerstone of professional broadcast and industrial video processing, offering the deterministic, low-latency pipeline performance that software-only solutions struggle to match. This article introduces two FPGA-based product categories — a professional audio/video monitor with real-time analysis tools, and a flexible video interface capture device — covering their key capabilities and the engineering use cases they address. ## FPGA-Based Professional Video Monitor Modern broadcast and cinematography workflows demand more than simply displaying a picture. Colorists, camera operators, and post-production engineers need objective, real-time signal analysis to make confident exposure and color grading decisions. An FPGA implementation is well-suited to this role: the parallel processing fabric can simultaneously compute waveform data, build histogram bins, and render the display pipeline without the frame-drop risk inherent in a CPU-based approach. The mon --- ## FPGA-Based Audio and Video Live Production Switcher – Application Case - URL: https://intl.sienovo.cn/blog/138665422 - Date: 2024-05-10 - Tags: #LiveStreaming Live production at the edge demands deterministic, sub-frame latency that general-purpose CPUs and even GPU-based pipelines struggle to guarantee. This application case showcases an FPGA-based audio and video live production switcher developed by Sienovo, designed for broadcast studios, live-streaming setups, and professional AV integration where real-time signal switching and compositing must be hardware-reliable. ## Why FPGA for Live Switching? FPGAs are uniquely suited to video switching because every pixel pipeline stage executes in fixed, predictable gate delays rather than competing for CPU scheduler slots. An FPGA fabric can clock video data through capture, format conversion, compositing, and output all within a single frame period—typically 16.7 ms at 60 fps—with no OS jitter. This makes FPGA the preferred architecture for broadcast-grade switchers, where a dropped frame or glitched transition is unacceptable on air. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/b --- ## FPGA-Based Audio and Video Matrix – 2K/4K Resolution Solution - URL: https://intl.sienovo.cn/blog/138615121 - Date: 2024-05-10 - Tags: #AudioVideo ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138615121/01_f4158d2c6bda5509ff89f4bb49718b5c.png) ① Single board supports 4 inputs and 4 outputs, handling any video resolution up to 4096x2160P30 ② Single board supports HDMI, VGA, DVI, fiber optic, SDI, and HDBaseT interfaces ③ Interface input resolution auto-adaptive ④ Output resolution freely configurable per interface ⑤ Broadcast-grade switching speed and latency of 20ms ⑥ Pure RGB image processing for more accurate color reproduction ⑦ Supports multi-channel arbitrary拼接 (video wall), window opening, roaming, overlay, scaling, rotation, sequence switching, and OSD on a single screen ⑧ Suitable for matrix switching, video wall, splitting, multi-display applications, etc. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138615121/02_583b85e5acfc897d4b205aa370aea1a3.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138615121/03_1c139166ea7446be043d6ea427a69fad.png) Audio and V --- ## FPGA + Actions ARM Solution for VR Video Player with 3D Glasses Display - URL: https://intl.sienovo.cn/blog/138613888 - Date: 2024-05-10 - Tags: #AR, #VR ## FPGA + Actions ARM Solution for VR Video Player with 3D Glasses Display Head-mounted VR video players present a deceptively simple display problem: one video stream must reach two eyes simultaneously, with pixel-perfect synchronization, low latency, and no tearing — all within the tight power and size budget of a wearable device. This post walks through how Sienovo's engineering team solved that challenge using a combined FPGA + Actions (炬力) ARM platform to drive a dual-LCD VR video player capable of real-time 2D/3D switching. --- ## The Core Challenge: One Source, Two Displays A conventional single-SoC design typically drives one display pipeline. Extending that to two independent LCD panels — each forming one eye of a stereoscopic pair — introduces synchronization demands that software alone cannot reliably meet. Frame timing skew between left-eye and right-eye panels of even a few milliseconds is perceptible as a "ghosting" artifact and contributes directly to motion sickness --- ## FPGA-based Video Matrix Switching Solution - URL: https://intl.sienovo.cn/blog/138614676 - Date: 2024-05-09 - Tags: #Networking ### I. System Solution for a Single Display Device: Conference Room with Only 1 Display Device A conference room may have many signal sources but only one display device. In this scenario, the best solution is to use a switcher. #### (1) Switcher (Control Methods: Remote Control, Software, Chassis Panel, Central Control) Signal sources connect to the switcher's input ports, and the switcher's output connects to the display device. Common interface types include VGA and HDMI. For example: 16 computers connect to the switcher's inputs, and the switcher outputs to a projector (as shown below). Qiyao Technology's switchers feature three control methods: infrared remote control, software (RS-232 serial port), and chassis panel. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138614676/01_812914bd7bda89ffe7be6b21e82bcdad.png) #### (2) Automatic Switcher (Control Methods: Automatically detects and prioritizes the last connected signal for output switching, Remote Control, C --- ## FPGA Capture Card, Capable of CVBS/HDMI/SDI Signal Conversion - URL: https://intl.sienovo.cn/blog/138614560 - Date: 2024-05-09 - Tags: #FPGADev ## An FPGA-Based Multi-Format Capture Card Supporting CVBS, HDMI, and SDI Conversion Professional broadcast and AV integration work rarely involves a single signal standard. A television station may need to ingest legacy composite video from an archive deck, accept HDMI output from a modern graphics workstation, and simultaneously feed a live SDI router — all from the same piece of rack equipment. This FPGA capture card addresses exactly that scenario, providing hardware-level conversion between CVBS, HDMI, and SDI in a single unit aimed at broadcast studios, live-event stages, and corporate conference rooms. ## Signal Input and Adaptive Detection The card accepts three distinct input formats: - **CVBS (Composite Video Baseband Signal)** — the analogue standard that has been the backbone of broadcast infrastructure since the NTSC/PAL era. CVBS carries luminance, colour, and sync on a single coaxial line, typically at 480i (NTSC) or 576i (PAL). - **HDMI** — the digital consumer/pros --- ## FPGA+DDR+SERDES+USB3.0 Unidirectional Transmission Solution: Data Transmits Only One Way to Prevent Reverse Attacks and Ensure System Security - URL: https://intl.sienovo.cn/blog/138614417 - Date: 2024-05-09 - Tags: #FPGADev, #SystemSecurity, #Security ## One-Way Data Transmission Using FPGA + DDR + SERDES + USB 3.0 and Fiber Optics In high-security environments — government networks, industrial control systems, financial infrastructure, and classified data centers — the threat of reverse-channel attacks is a fundamental concern. A bidirectional data link, no matter how well encrypted, always carries the risk that a compromised endpoint can inject traffic back toward the source. The solution described here eliminates that attack surface entirely by making the physical layer unidirectional: data flows one way, and only one way, from transmitter to receiver. This design uses an FPGA as the central control fabric, paired with DDR memory for buffering, SERDES (Serializer/Deserializer) transceivers for high-speed serial signaling, and a USB 3.0 host interface for connecting to the host system. The physical medium is optical fiber, which is inherently passive in one direction — a fiber carrying light from transmitter to receiver cannot c --- ## FPGA+HDMI Conversion Solution for Live Screen Switching in Online Broadcasting; Customer Applications: Live Streaming, Self-Media - URL: https://intl.sienovo.cn/blog/138614295 - Date: 2024-05-09 - Tags: #FPGADev, #Media ## FPGA+HDMI Conversion Solution for Live Screen Switching in Online Broadcasting In online broadcasting, live screen switching is a critical feature that requires a seamless and high-quality video transition between different sources. In this article, we will explore a solution that utilizes Field-Programmable Gate Arrays (FPGAs) to convert HDMI signals and enable live screen switching in online broadcasting. This solution is particularly useful for live streaming and self-media applications. ### Key Features The proposed solution supports the following key features: 1. **Multi-channel HDMI high-definition input/output**: This feature allows for the simultaneous input and output of multiple HDMI signals, enabling the system to handle multiple video sources and display them on different screens. 2. **Flexible switching of all input and output channels**: This feature enables the system to switch between different input and output channels, allowing for smooth and seamless video tra --- ## FPGA+USB+CCD High-Precision Industrial Camera for Precision Object Measurement and Machining Accuracy - URL: https://intl.sienovo.cn/blog/138614187 - Date: 2024-05-09 - Tags: #DigitalCamera ## FPGA + USB + CCD High-Precision Industrial Camera for Object Measurement and Machining Accuracy Precision manufacturing depends on accurate, real-time visual inspection. When tolerances are measured in microns, the imaging pipeline itself — sensor, signal chain, interface, and software — must be engineered as a cohesive system rather than a collection of off-the-shelf parts. This post describes a purpose-built industrial camera platform combining an FPGA, a Sony CCD image sensor, and a USB 2.0 interface, designed specifically for precision object measurement and machining accuracy verification on the factory floor. ## Why FPGA + CCD Instead of CMOS-Based Solutions? Most consumer and prosumer machine-vision cameras have shifted to CMOS sensors because they are cheaper and easier to read out. For industrial metrology, CCD sensors — particularly Sony's low-noise CCD lineup — still offer advantages: lower dark current, better pixel uniformity, and a global shutter that eliminates the --- ## FPGA+MCU+SDRAM Solution for Pattern Making and Fabric Cutting in Garment Factory Production and Design Processes - URL: https://intl.sienovo.cn/blog/138614114 - Date: 2024-05-09 - Tags: #FPGADev In garment manufacturing, two of the most precision-demanding tasks are pattern making and fabric cutting. A misaligned plotter head or an uncalibrated cutter can waste meters of expensive fabric in seconds. This article outlines an FPGA+MCU+SDRAM hardware solution purpose-built for these workflows, covering the architectural choices behind the design and why each feature matters on the factory floor. ## Why FPGA+MCU+SDRAM? Garment plotters and cutters must coordinate real-time motion control, print-head firing, host communication, and user interface simultaneously — workloads that a microcontroller alone struggles to handle deterministically. The architecture here splits responsibilities: the FPGA handles time-critical tasks like motor pulse generation and print-head timing where microsecond accuracy matters, while the MCU manages higher-level logic such as protocol parsing, LCD rendering, and host communication. SDRAM provides the large frame buffer needed to hold decompressed patt --- ## FPGA-Controlled 3 Stepper Motor Driver Chips and 1 DC Motor Driver for Industrial Printing Control - URL: https://intl.sienovo.cn/blog/138613993 - Date: 2024-05-09 - Tags: #FPGADev ## FPGA-Controlled 3 Stepper Motor Driver Chips and 1 DC Motor Driver for Industrial Printing Control In the realm of industrial printing control, precision and flexibility are key. This article explores the use of FPGA-controlled 3 stepper motor driver chips and 1 DC motor driver in DIY printing applications. We'll delve into the key features and capabilities of this setup, and discuss how it can be utilized in various industrial printing scenarios. ### Customer Application The FPGA-controlled 3 stepper motor driver chips and 1 DC motor driver are designed for use in DIY printing applications, where precision and flexibility are essential. This setup can be used to control various types of motors, including stepper motors and DC motors, which are commonly used in industrial printing applications. ### Key Features The key features of this setup include: 1. **Supports touchscreen control**: The system supports touchscreen control, allowing users to easily control the motors and ad --- ## FPGA + HiSilicon ARM Solution for Simultaneous HDMI/VGA Signal Reception and Remote Control - URL: https://intl.sienovo.cn/blog/138613790 - Date: 2024-05-09 - Tags: #FPGADev Dual-channel video capture — receiving HDMI and VGA signals simultaneously on the same board — is a recurring challenge in industrial remote-monitoring and control systems. This post walks through the architecture of an FPGA + HiSilicon ARM solution designed to do exactly that, while also compressing, wirelessly transmitting, and optionally stitching both channels into a single output stream for remote-control applications. ## Why FPGA + ARM for Multi-Channel Video Capture? HDMI and VGA are fundamentally different signal types. HDMI carries a serialised TMDS bitstream with embedded clock and audio, while VGA is an analogue RGB signal with separate sync lines that must be digitised first. Handling both in real time requires parallel front-end logic that can decode one signal while simultaneously sampling and digitising the other — a task that maps naturally onto an FPGA's concurrent fabric. Once the raw pixel data is captured and normalised by the FPGA, a general-purpose application --- ## FPGA HDMI Sensor Wireless RC Model Camera - URL: https://intl.sienovo.cn/blog/138607904 - Date: 2024-05-09 - Tags: #FPGADev ## FPGA-Based Wireless RC Model Camera Solution: Receiving Image Data from Camera Sensor and Outputting via HDMI In this article, we will explore an FPGA-based solution that enables the receipt of image data from a camera sensor and its subsequent transmission to the backend via HDMI. This technology has significant applications in wireless RC model cameras, where high-quality video feed is crucial for real-time monitoring and control. The solution in question leverages the capabilities of FPGAs to receive and process image data from various camera sensors, supporting resolutions up to 2K. The key features of this solution include: ### Key Features 1. **Supports any resolution format up to 2K**: The FPGA-based solution can handle image data from camera sensors with resolutions up to 2K, making it suitable for a wide range of applications. 2. **Supports various sensor models**: The solution is designed to be flexible and can accommodate different sensor models, ensuring compatibilit --- ## FPGA-based HDMI to MIPI Extended Display Solution - URL: https://intl.sienovo.cn/blog/138607878 - Date: 2024-05-09 - Tags: #ComputerPeripherals ## FPGA-Based HDMI to MIPI Extended Display Solution Modern embedded display systems increasingly demand flexible, low-latency video routing between source interfaces and panel types that don't natively match. A common challenge arises when a host device outputs HDMI — the universal standard for consumer and professional video — but the target display panel speaks MIPI DSI, eDP, LVDS, or parallel RGB. Bridging these two worlds typically requires either a dedicated bridge IC (which locks you into a fixed resolution and limited feature set) or a software-driven SoC path (which introduces latency and processing overhead). This post introduces an FPGA-based solution that accepts a raw HDMI input signal and drives a wide range of LCD panel interfaces with zero-latency, full-pipeline flexibility. ![FPGA HDMI to MIPI block diagram](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138607878/01_681ac209d293c06487317b249ef2dacb.png) ## Why FPGA for HDMI-to-Panel Bridging? Fixed-funct --- ## FPGA OSD Solution, Applied in XBOX Console Monetization and Other Fields - URL: https://intl.sienovo.cn/blog/138607817 - Date: 2024-05-09 - Tags: #FPGADev FPGA-based On-Screen Display (OSD) overlays are a well-established technique in video processing systems, and this solution brings that capability to the HDMI domain with zero-latency pass-through — making it practical for real-time commercial applications such as pay-per-use gaming kiosks. ## What the System Does The core architecture is straightforward: an FPGA sits in-line between a video source and a display. HDMI IN captures the raw HDMI signal from the source device (a game console, media player, set-top box, or PC), while HDMI OUT delivers the same video stream with characters or images composited on top. The FPGA handles both the signal capture and the overlay rendering in hardware, which is why the system can achieve zero added latency — the overlay pixels are written into the output stream on the fly, not after a frame buffer round-trip. This is a fundamentally different approach from software-based overlays (e.g., OBS Studio or a capture card feeding a PC), which introduc --- ## FPGA Serial Screen Solution - URL: https://intl.sienovo.cn/blog/138607730 - Date: 2024-05-09 - Tags: #FPGASerialDisplay ## FPGA Serial Screen Solution FPGA serial screen solutions have become increasingly popular in various industries such as industrial automation, smart home appliances, rail transit, data centers, EV charging stations, power and medical, national defense and security, and shared devices. In this article, we will explore the key features and applications of FPGA serial screen solutions. ## Key Features FPGA serial screen solutions typically support a wide range of features, including: 1. **Supports dozens of food processing modes**: This feature enables the FPGA serial screen solution to handle various food processing tasks, such as cooking, heating, and cooling. 2. **Supports storing custom working modes**: Users can store their custom working modes, allowing for flexibility and convenience. 3. **Supports delayed operation**: The FPGA serial screen solution can be programmed to perform tasks at a later time, making it ideal for applications that require scheduling. 4. **Supports ke --- ## FPGA-based Video Matrix, Video Splicing, Seamless Switching Solution - URL: https://intl.sienovo.cn/blog/138607619 - Date: 2024-05-09 - Tags: #Matrix, #Algorithm, #LinearAlgebra, #VideoStitching ## FPGA-Based Video Matrix: High-Density HDMI Switching and Video Wall Solutions Large-scale AV installations — command centers, broadcast control rooms, stadium video walls, and industrial monitoring facilities — demand signal routing infrastructure that can handle dozens or hundreds of video feeds simultaneously without dropped frames, tearing, or perceptible latency. FPGA-based video matrix switches have become the backbone of these deployments precisely because programmable logic can perform full cross-point switching at line rate, something general-purpose CPUs and even most ASICs struggle to deliver at high channel counts. This post breaks down the key capabilities of a production-grade FPGA video matrix platform supporting up to 144×144 HDMI channels, and explains the engineering decisions behind each specification. ## What Is a Full Cross-Point Matrix? A full cross-point (or non-blocking) matrix is one where any input can be routed to any output — simultaneously and independ --- ## Multi-core Real-time Operating System Solution for DSP Processors - URL: https://intl.sienovo.cn/blog/138597411 - Date: 2024-05-09 - Tags: #FPGADev ## Multi-core Operating System for DSP Processors Networked electricity, space, deep sea, near space, phased array radar, cluster processing, distributed computing, etc., place higher demands on system processing capability, real-time performance, precision, and dynamic range. However, single-core chips, constrained by physical limits, manufacturing costs, processing power, as well as power consumption and heat dissipation, have become a system bottleneck. To improve processing performance, the traditional approach is to increase the number of single-core chip boards, but this leads to various problems such as complex interactions, complex design, high hardware investment, and poor maintainability. Traditional hardware is evolving from FPGA+PPC+DSP towards multi-core DSP+SOC. Multi-core processors will integrate more IP blocks that are simple in structure and easy to use. Heterogeneous multi-core architectures and accelerators are the major trends in processor development. **Key is --- ## Cross-Platform Communication Solution for Parallel Computing on Multi-Core DSPs - URL: https://intl.sienovo.cn/blog/138578958 - Date: 2024-05-09 - Tags: #DSP The core of parallel computing lies in computational nodes and the communication and coordination mechanisms between them. Although OpenMP provides developers with an easy-to-use, incremental development approach, when integrated with complex architecture MCSDKs, it introduces numerous opaque, non-debuggable black boxes in both tools and code—making it unsuitable for mission-critical domains such as military aerospace, satellite-borne, missile-borne, or rocket-borne systems that demand high reliability and real-time performance. Inter-core communication is a key aspect of multi-core parallel solutions. The most efficient method is using inter-core interrupts; however, to address flexibility in communication, zero-copy techniques based on shared memory pools are inevitably required. **Use Cases for Parallel Computing** - Reduce the solution time for individual problems - Increase problem scale and improve accuracy - Enhance fault tolerance - Improve reusability - Increase sys --- ## Aerospace AFDX Interface Simulation Card - URL: https://intl.sienovo.cn/blog/138578466 - Date: 2024-05-09 - Tags: #Networking The ARINC664 dual-port terminal network card is a high-performance ARINC664 network interface card (NIC) that supports ARINC664 network simulation, testing, and data analysis functions. It features two ARINC664 ports with RJ45 connectors, which can be used as two independent ports or as a pair of redundant ports. The card integrates an IRIG-B system clock, providing multi-node clock synchronization capabilities, facilitating its use in multi-node simulation systems. The ARINC664 communication specification fully complies with the ARINC664 Avionic Network PART7 protocol requirements. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138578466/01_0e10a9bbbf20918fb13989f0891c8af8.png) **Technical Specifications:** | Item | Parameter | |---|---| | Functional Indicators | | | Number of Ports | 2 channels, 2 ports with redundancy | | Port Speed | Provides two 10/100M RJ45 ARINC664 ports | | Protocol Specification | Supports ARINC664 specification | | Port Configuration | Suppo --- ## Avionics FC Node Card, FC Switch, Primarily Using LC or MPO Fiber Optic Interface Forms - URL: https://intl.sienovo.cn/blog/138578721 - Date: 2024-05-08 - Tags: #FC The FC node card primarily uses LC or MPO fiber optic interface forms. It can be used as 4/2 independent ports or as 2 pairs/1 pair of redundant ports, supporting communication rates of 1.0625Gbps, 2.125Gbps, 4.25Gbps, and 8.5Gbps. The node card fully complies with FC fiber optic communication protocol specifications such as FC-LS, FC-FS, FC-AE-ASM, and FC-AE-1553B. **Key Features:** Ø Supports 4/2 independent or redundant FC ports for point-to-point and switched communication modes Ø Supports 1G/2G/4G/8G communication rates Ø Complies with FC-PC, FC-FS protocol standards Ø Supports 256 non-data blocks and 16 data blocks Ø Supports implicit and explicit login Ø Complies with Class 3 service Ø FC frame length supports 36～2148 bytes; Ø Supports Class 3 services, supports multicast, broadcast functions; Ø Supports at least 8 Buffer-to-Buffer credits, credit value configurable; Ø Supports up to 256 receive channels and 256 transmit channels; Ø Supports primitive-level clock sy --- ## Avionics ARINC818 Acquisition Card - URL: https://intl.sienovo.cn/blog/138578616 - Date: 2024-05-08 - Tags: #AudioVideo The ARINC818 Acquisition Card is a high-performance PCIe video fiber optic acquisition and test device designed for the Avionics Digital Video Bus (ADVB) protocol. The ARINC818 protocol is primarily used for real-time high-definition image transmission between airborne equipment. It has been successfully applied in multiple civil and military aircraft models and is one of the future development directions for airborne video transmission buses. The ARINC818 Acquisition Card uses a highly integrated FPGA chip to implement the ARINC818 protocol and achieves real-time high-definition image software acquisition functionality through a high-speed 8xPCIe interface. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138578616/01_6213d29626a8c28fed82f2030e2fecda.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138578616/02_8ccd1ed492ba2dc562f63dba1c6c6493.png) **Technical Specifications:** | Item | Parameter --- ## 1553B Bus Interface Simulation Card, 1553B IP Core, Applicable to Aerospace Airborne, Integrated Aircraft Avionics, and Other Fields - URL: https://intl.sienovo.cn/blog/138578302 - Date: 2024-05-08 - Tags: #1553B The 1553B bus interface card can be used as a communication or simulation test board, supporting computer bus platforms such as USB, PCI, PXI, CPCI, Ethernet, RS422, RS485. It offers single-function (1 BC, 0-31 RTs, and 1 BM, currently only single operating mode) and multi-function (1 BC, 0-31 RTs, and 1 BM, currently multiple operating modes available) configurations, with single-channel, dual-channel, triple-channel, and quad-channel options. Communication rates support standard 1Mbps, as well as 4Mbps. Designed for industrial-grade operating temperatures from -40℃ to +85℃, it is rich in features, easy to use, and conducive to secondary development. The 1553B interface simulation card provides Windows/Linux/VxWorks drivers and supports board diagnostics and testing. It can meet the communication, testing, and simulation requirements for 1553B bus in equipment, laboratories, and field operations. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138578302/01_0e10a9bbbf20 --- ## ARINC429 IP CORE, ARINC429 FPGA IP Core Solution for Aerospace Bus - URL: https://intl.sienovo.cn/blog/138578095 - Date: 2024-05-08 - Tags: #tcp/ip, #NetworkProtocol, #Networking The ARINC429 IP CORE implements the ARINC429 interface protocol using a single FPGA. The product complies with the ARINC429/HB6096 bus protocol specifications, and each channel can be independently configured for reception or transmission. As a standard IP Core, it supports embedded system interfaces such as PMC, PCI, CPCI/VME/VPX, PCIe, as well as user-customized Local bus interfaces. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138578095/01_0228c33b45b62e806ca993659fd74ded.png)  ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138578095/02_86022a932f9eabee5a25fd5d4c730dcc.png) **Technical Specifications:** | Item | Parameter | | :--- | :--- | | Functional Indicators | | | Port Rate | Channel rates support 12.5KHz, 50KHz, 100KHz, or any configuration from 200KHz to 500KHz | | Number of Ports | Supports 16 input channels, 16 output channels | | Protocol Support | Supports ARINC429 protocol | | Filtering and Capture | Provides data filtering and data cap --- ## Aerospace ARINC429 Bus Protocol Interface Simulation Card - URL: https://intl.sienovo.cn/blog/138577937 - Date: 2024-05-08 - Tags: #MCU, #stm32, #EmbeddedHardware The ARINC429 Interface Simulation Card is a high-performance, low-power 429 bus protocol processing board. It complies with ARINC429 specifications, supporting 16 receive and 16 transmit 429 bus interfaces, enabling customers to quickly implement ARINC429 interface terminals. In addition, the product offers an IRIG-B time-code synchronization interface, suitable for multi-board collaborative environments. The card is equipped with standard driver libraries for various VxWorks and Windows versions, and provides powerful configuration application software, facilitating quick user adoption and product secondary development. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138577937/01_2a31ad530994a43935a10ece73f78b4e.png) **Technical Specifications:** Item Parameter Functional Specifications Port Rate Channel rates support 12.5KHz, 50KHz, 100KHz, or any configuration from 200KHz to 500KHz Number of Ports Supports 16 inputs, 16 outputs Host Interface 32-bit 66MHz/33 --- ## Avionics Network (ARINC818 Bus) / CVBS / HDMI / PCIe Video Card Solutions - URL: https://intl.sienovo.cn/blog/138575517 - Date: 2024-05-08 - Tags: #AudioVideo, #FPGADev 1. ARINC818 Acquisition Card The ARINC818 acquisition card is a high-performance PCIe video fiber optic acquisition and test equipment designed for the Avionics Digital Video Bus (ADVB) protocol. The ARINC818 protocol is primarily used for real-time high-definition image transmission between airborne equipment and has been successfully applied in various civil and military aircraft models, making it one of the future development directions for airborne video transmission buses. The ARINC818 acquisition card utilizes a highly integrated FPGA chip to implement the ARINC818 protocol and achieves real-time high-definition image software acquisition through a high-speed 8xPCIe interface. Functional Block Diagram: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138575517/01_fbb6fecd7fcf45a982e0dc08a56ab247.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138575517/02_18214ea7a01b53ad4779b1925a73ffa2.png) Application Areas Avionics bus communication, marin --- ## Deep Integration of AI and CIS Technologies for Intelligent Optical Imaging - URL: https://intl.sienovo.cn/blog/138519022 - Date: 2024-05-07 - Tags: #AI ## Deep Integration of AI and CIS Technologies for Intelligent Optical Imaging Intelligent optical imaging technology has been gaining significant attention in recent years, with applications in various fields such as security monitoring, intelligent driving, industrial inspection, and scientific observation. In this article, we will explore the concept of dual-chip collaborative intelligent optical cameras and how they are revolutionizing the field of optical imaging. ### Background Dual-chip collaborative intelligent optical cameras are a new generation of optical cameras that leverage the power of artificial intelligence (AI) and complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) technology. These cameras are designed to break through the bottlenecks of scene perception and cognition under complex imaging conditions, providing high-quality images even in challenging environments. ### Xinmai's Approach Xinmai, a leader in the intelligent transformation of optical --- ## 【NI Domestic Replacement】cDAQ-9178, 8-Slot USB CompactDAQ Chassis, Import Replacement Solution for Data Acquisition Card Controllers with Domestic Alternatives - URL: https://intl.sienovo.cn/blog/138490546 - Date: 2024-05-06 - Tags: #DAQ ## Replacing the NI cDAQ-9178: A Domestic Alternative for Data Acquisition Card Controllers The cDAQ-9178 is a bus-powered CompactDAQ USB chassis designed for small, portable sensor measurement systems. This chassis allows for easy connection to sensors and electrical measurements via plug-and-play USB, making it a popular choice for various industrial applications. However, for users looking for domestic alternatives, there are several options available that can provide similar functionality. The cDAQ-9178 can be paired with various combinations of C Series I/O modules to achieve mixed measurements of analog I/O, digital I/O, and counter/timers. This flexibility makes it an ideal choice for applications that require a wide range of measurement capabilities. The chassis also features four 32-bit general-purpose counter/timers, which can be accessed via two built-in BNC connectors. When looking for a domestic replacement for the cDAQ-9178, it's essential to consider the specific requ --- ## [NI Domestic Alternative] USB-4432 102.4 kS/s, 100 dB, 0.8 Hz AC/DC Coupling, 5-Input Sound and Vibration Device - URL: https://intl.sienovo.cn/blog/138489437 - Date: 2024-05-06 - Tags: #NI, #USB-4432 ## Overview: USB-4432 Sound and Vibration DAQ Industrial noise, structural fatigue, and rotating-machinery health monitoring all depend on capturing fast, low-noise analog signals from sensors that live close to the measurement point. The NI USB-4432 is a purpose-built data acquisition device for exactly this class of problem — and understanding its architecture helps engineers evaluate whether a domestic (Chinese-market) alternative can meet the same demands. ## Key Specifications at a Glance | Parameter | USB-4432 | |---|---| | Sample rate | 102.4 kS/s | | Dynamic range | 100 dB | | Low-frequency cutoff | 0.8 Hz (AC coupling) | | AI channels | 5 (ch 0–3: IEPE; ch 4: non-IEPE) | | Coupling | AC / DC selectable | | Anti-aliasing filter | Built-in, auto-adjusts to fs | The 102.4 kS/s rate gives usable bandwidth to roughly 40 kHz after the anti-aliasing filter rolls off — sufficient for most structural-acoustic and machinery vibration work, where the dominant energy is well below 20 --- ## Internet of Everything - AI Edge Computing Enabling Tencent Autonomous Vehicles - URL: https://intl.sienovo.cn/blog/138476832 - Date: 2024-05-05 - Tags: #AI To seize the development opportunities of intelligent transportation systems and explore future smart urban transportation systems, this March, Tencent's autonomous vehicles officially launched in the Shenzhen Intelligent Connected Transportation Demonstration Zone. This project will be based on intelligent connected vehicle testing, guided by the construction of an autonomous driving ecosystem and future transportation system, focusing on the five key elements of "vehicle, road, cloud, network, and map." Integrating new-generation technologies such as 5G, autonomous driving, and artificial intelligence, it aims to establish a comprehensive ecosystem for the research, development, and testing of future intelligent connected vehicles, and build an internationally leading intelligent connected transportation system test base. This is an autonomous driving demonstration project jointly created by the Shenzhen Pingshan District Government, Shenzhen Traffic Control, and Tencent. As one of --- ## 基于飞腾全国产/intel工控机，建设“智慧高速”助力湖南平益高速高效通行,ETC门架收费系统、车道收费系统和智慧高速事件检测项目 - URL: https://intl.sienovo.cn/blog/138476761 - Date: 2024-05-05 - Tags: #Highway, #ETC **Highlights** On November 28th, Hunan Province's first "smart highway"—the Pingyi Expressway—was officially completed and opened to traffic. Unlike conventional expressways, Pingyi Expressway extensively utilizes cutting-edge technologies such as Artificial Intelligence, Big Data, IoT, and Vehicle-Road Coordination to create the nation's first comprehensive smart highway operation and management platform. As the smart brain of the expressway, it achieves real-time (second-level) incident detection, rapid response, and multi-agency joint emergency response, using the power of technology to ensure the safety of drivers and passengers. With its high-quality products and professional application solutions, it undertook all ETC gantry toll collection systems, lane toll collection systems, and smart highway incident detection projects for this project. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138476761/01_cc57adc9a736d4f18eca56b627b7acdb.jpeg) 【Image from the intern --- ## Loongson 7A1000 Dual-Socket Motherboard, 3AV6UT Loongson Trusted Motherboard - URL: https://intl.sienovo.cn/blog/138460678 - Date: 2024-05-05 - Tags: #Loongson, #VPX ## Loongson Dual-Socket Motherboard ■ Loongson 7A1000 chipset ■ 32GB ECC memory ■ 1 VGA output ■ Supports iKVM ■ 2 front USB 2.0 ports, 4 rear USB 2.0 ports ■ 4 Gigabit Ethernet ports ■ Supports Kylin OS ■ Operating temperature: -40℃～+65℃ ■ Storage temperature: －55ºC～+70ºC ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138460678/01_08a00add9520862475d8b189af78d92f.png) ## 3AV6UT Loongson Trusted Motherboard ■ VPX 6U form factor, Open VPX specification ■ Domestic Loongson 3A3000 quad-core high-performance processor, 1.2GHz clock speed ■ 7A1000 chipset ■ Dual-channel DDR3 ECC 72-bit memory; ■ Standard configuration with domestic DDR3 memory chips, total capacity 16GB; ■ Onboard mSATA MLC SSD, standard capacity 512GB (optional 128GB, 256GB, 1TB) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138460678/02_09af7391ab5501eb0446b0a2ad9e149e.png) ## 3AJKGL Loongson Motherboard ■ Loongson 3A3000 quad-core domestic processor, 1.2GHz clock speed ■ AMD RS7 --- ## 6U VPX Loongson 3A3000 with Fully Domestic Components + Domestic Graphics Card, VPX 3U Loongson 2K Motherboard, Loongson 3A3000 VPX 3U Motherboard - with SRIO - URL: https://intl.sienovo.cn/blog/138460565 - Date: 2024-05-05 - Tags: #Loongson, #VPX ## 6U VPX Loongson 3A3000 + Domestic Graphics Card ■ 7A1000 Chipset ■ 16GB RAM (International) / 8GB RAM (Domestic) ■ Lingjiu GP101 Discrete Graphics Card, 1x VGA + 2x DVI Output ■ Storage: Onboard eMMC/SSD capacity 256GB ■ 4x USB 2.0 Interfaces; ■ 4x Gigabit Ethernet Interfaces; ■ Supports Kylin OS ■ Operating Temperature: -40℃～+65℃ ■ Storage Temperature: －55ºC～+70ºC ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138460565/01_8df168edfeb5a38975598b76cabc1e61.png) ## VPX 3U Loongson 2K Motherboard ■ Loongson 2K1000 Chip, 800MHz ■ DDR3 64-bit Memory, 4GB Capacity ■ 2x 1000BASE-X, 4x 1000BASE-T Interfaces ■ 2x Independent Isolated CAN Interfaces ■ Supports Kylin OS, VxWorks System ■ Operating Temperature: -40℃～+65℃ ■ Storage Temperature: －55ºC～+70ºC ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138460565/02_14b50e8e3f105ebcde59999c60d6c287.png) ## Loongson 3A3000 VPX 3U Motherboard ■ Supports Loongson 3A3000 Processor / 1.2GHz; ■ Loongs --- ## Fully Domestic CPCI Loongson 3A-3000 Motherboard - URL: https://intl.sienovo.cn/blog/138460323 - Date: 2024-05-05 - Tags: #Loongson China's push toward domestically designed computing infrastructure has produced some compelling hardware for industrial and defense-adjacent applications. These two CPCI form-factor boards based on the Loongson 3A-3000 processor represent a mature point in that roadmap — ruggedized, thermally specified for harsh environments, and running a fully domestic software stack. This post documents the two available variants and explains the key design choices behind each. ## The Loongson 3A-3000 in an Industrial Context The Loongson 3A-3000 is a quad-core MIPS64-compatible processor (Loongson's own GS464E microarchitecture) manufactured on a 28 nm process. With a TDP that remains manageable in passively cooled or conduction-cooled enclosures, it has become a natural fit for CompactPCI (CPCI) carrier boards deployed in telecommunications, rail, energy, and defense equipment — sectors where supply-chain sovereignty matters as much as raw performance. CPCI (IEC 61076-4-101) uses the Eurocard m --- ## Intelligent Health Management Daughter Card (ChMC/IPMC) Module, supports IPMI 2.0 standard communication protocol, 0Kbps configurable, can control power on/off of other blades via IPMI commands, features fault reporting and power-on self-test - URL: https://intl.sienovo.cn/blog/138380615 - Date: 2024-05-01 - Tags: #MCU, #EmbeddedHardware It is a BMC daughter card. This daughter card provides 1 Gigabit Ethernet interface connected to a Gigabit switch chip, outputs 1 Fast Ethernet debug network interface, and outputs 2 + 8 (optional) IPMB (I2C) interfaces with isolation processing (I2C BUFFER). It supports the IPMI 2.0 standard communication protocol, with configurable communication rates of 100Kbps/400Kbps. It can control the power on/off of other blades via IPMI commands, and features fault reporting, power-on self-test (POST), and operational status self-test functions. It provides software interfaces to output information such as current, voltage, main chip temperature (including CPU, 40G switch chip), and firmware version (if available) to user software. It has the capability to collect and manage monitoring information for all blades in the entire system, and can provide independent system-wide status monitoring. It adopts a PMC (VITA 42) architecture for easy ruggedization. Interaction between the AST2400 and the --- ## Detailed Introduction to a Fully Domestically Produced BMC Daughter Card - URL: https://intl.sienovo.cn/blog/138380578 - Date: 2024-05-01 - Tags: #Phytium A fully domestically produced BMC daughter card capable of implementing ChMC/IPMC functionalities. The daughter card complies with the IPMI 1.5/2.0 protocol specification and also supports custom OEM commands. The daughter card can acquire carrier board environmental information, board attribute information, and board status information, including data such as temperature, voltage, and current; FRU, system version, and CPU model; memory utilization, CPU utilization, and network status. The daughter card can also control board power on/off and reset. Furthermore, it can dynamically configure IPMB addresses and IP addresses based on chassis number and slot number, and can provide customized web management interfaces for customers. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138380578/01_b941d07a681e1bda90064cacb2c7a554.png) 1. Operating Environment Specification Name | Specification Description ---|--- Operating Temperature | -40℃ ~ +70℃ Storage Temperature | -50℃ ~ --- ## Phytium FT2000+ 6U VPX High-Performance Data Processing Blade - URL: https://intl.sienovo.cn/blog/138380416 - Date: 2024-05-01 - Tags: #Phytium ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138380416/01_227f09ef43325db475e549ada5edfcd7.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138380416/02_b847880f3b6cb4cd44eae8dcf5bb8d4b.png) 1. This is a high-performance 6U VPX data processing blade based on Phytium's FT2000+ processor. The VPX computing blade complies with the OpenVPX 6U standard specification, and its signal definitions conform to the SLT6-PAY-4F1Q2U2T-10.2.1 requirements defined in the OpenVPX VITA65 standard. 2. System interconnect interfaces are achieved through the VPX backplane, including: 10GbE Ethernet interfaces for data plane interconnection; Gigabit SerDes and MDI interfaces for control plane interconnection; single-ended GPIOs for system interrupt and time synchronization; PCIe interfaces for expansion plane interconnection; JTAG interface for system debugging and maintenance; IPMB interface for chassis management; blade slot identification signals for identifying diffe --- ## Phytium FT1500A-16 6U VPX High-Performance Dense Computing Blade - URL: https://intl.sienovo.cn/blog/138380388 - Date: 2024-05-01 - Tags: #Phytium Phytium FT1500A-16 6U VPX High-Performance Dense Computing Blade ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138380388/01_19eec8f1910be3a790b1df1872c60ab8.png) A high-performance 6U VPX single-board display computer compliant with the OpenVPX VITA65 standard. The product adopts the mainstream GPGPU architecture, integrating an FT1500A-4 quad-core processor from Tianjin Phytium and a high-performance embedded GPU, the AMD® Radeon® E8860. The E8860 delivers industry-leading 3D graphics performance and ultra-high multi-display technology, supporting 2K/4K high-resolution displays. It is ideal for embedded applications requiring exceptional multi-display experiences and advanced visual effects. Powered by a high-performance domestic ARM processor, the design is mechanically compatible with industrial control and ruggedized systems, enabling it to replace x86-based display and control subsystems or integrated display-processing units in ground-based, airborne, and shipbo --- ## 飞腾FT2000+64核ATX主板详细介绍 - URL: https://intl.sienovo.cn/blog/138380336 - Date: 2024-05-01 - Tags: #Phytium The Phytium FT2000+ is one of China's most capable domestically developed server-class processors, and the ATX motherboard built around it represents a serious platform for organizations that need high core-count compute while staying within China's autonomous and controllable (自主可控) technology ecosystem. This post breaks down the full specification of this board and explains what each feature means for system integrators and data-center operators evaluating it. ## Processor: Phytium FT-2000+ The FT-2000+ is a 64-core ARM-architecture processor developed by Phytium Technology (天津飞腾信息技术有限公司). Its cores implement the ARMv8-A ISA, making it binary-compatible with the broad Linux ARM64 software ecosystem. With 64 physical cores on a single socket, this chip targets workloads that traditionally required dual-socket x86 configurations — think HPC simulation, parallel database query engines, dense virtualization, and cloud infrastructure. Placing the FT-2000+ on a standard ATX form factor --- ## JFM7VX690 Computing and I/O Interface Module by Fudan Microelectronics for Radar Signal Processing, Data Processing, and Other High-Speed, Compute-Intensive Applications - URL: https://intl.sienovo.cn/blog/138379707 - Date: 2024-05-01 - Tags: #FPGADev ### Computing and I/O Interface Module 1 Introduction 1.1 Product Overview The computing and I/O interface module is primarily composed of the Fudan Microelectronics JFM7VX690 FPGA, domestically produced Ethernet transceiver YT8521, domestic BMC chip GD32F450, domestic CPLD chip EF2L45BG256B, and domestic memory components, designed in a standard 6U VPX form factor. This computing and I/O interface module is mainly used in applications requiring high-speed, compute-intensive processing, such as radar signal processing and data processing. It provides a 10G Ethernet interface for service data and Gigabit Ethernet interfaces for management data. As a domestically developed, independently controllable solution, this high-performance, low-power, and highly reliable computing interface module can be widely applied in \*\*\*, \*\*\*, scientific research, communications, and other fields. 1.2 Product Appearance ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138379707/01_6 --- ## Tengrui D2000-8 MXM VPX, Domestically Produced, Widely Applicable to Edge Computing Gateways, Intrusion Detection, VPN, Network Monitoring, and Other Application Fields - URL: https://intl.sienovo.cn/blog/138379662 - Date: 2024-05-01 - Tags: #Phytium ### Tengrui D2000-8 MXM VPX 1. Overview The XMVPX-108 is a low-power logic and graphics processing VPX blade based on the Phytium D2000/8 processor, featuring onboard 32GB DDR4 memory and equipped with the Phytium X100 chipset to provide general-purpose I/O interface functions. The GPU adopts an MXM small plug-in card form factor, paired with an 8GB graphics card. It provides network interfaces such as RapidIO, 40GBASE-KR4, and 1000BASE-X to meet various network interconnection requirements for system business interconnection and control plane interconnection. The Tengrui D2000 integrates 8 high-performance FTC663 cores independently developed by Phytium, compatible with the 64-bit ARMv8 instruction set, clocked at 2.3GHz, with a TDP power consumption of 35W. It also integrates rich I/O interfaces and supports Phytium's self-defined processor security architecture standard PSPA 1.0, meeting the demands for performance and trusted security in more complex application scenarios. It c --- ## FeiTeng D2000+X100 TYPE6 All-Domestic Core Board - URL: https://intl.sienovo.cn/blog/138379627 - Date: 2024-05-01 - Tags: #SignalProcessing **FeiTeng D2000+X100 TYPE6 Core Board** **Product Overview** The FeiTeng D2000+X100 TYPE6 core board is an enhanced domestic controller core board. Its core CPU chip features a FeiTeng D2000/8-core industrial version CPU, FeiTeng X100 chipset, dual-channel DDR4L slots, PHY chip, and more. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138379627/01_87f8071a08eb0fed0fbd4e5afc7c8305.jpeg) **Product Features** l Based on FeiTeng D2000+X100 chipset l Abundant PCIe expansion resources: one PCIe x16, two PCIe x2, four PCIe x1 l Memory supports two DDR4 SODIMM slots, up to 32GB l Domestically produced\*\*\* l Compatible with domestic operating systems such as Galaxy Kylin V10, UnionTech UOS20 **Product Specifications** **Form Factor** 95mm\*125mm, standard COM-Type 6 **CPU** FeiTeng D2000/8-core standard version CPU **Chipset** FeiTeng X100 chipset **Memory** 2 DDR4 SODIMM slots, up to 32GB **Display Interface** 3x DP interfaces, including eDP **PCIe** 1x P --- ## VPX双路***至强高性能服务器模块 - URL: https://intl.sienovo.cn/blog/138379589 - Date: 2024-05-01 - Tags: #AI --- Title: Dual-Processor VPX High-Performance Xeon Server Module Content: ### Dual-Processor VPX High-Performance Xeon Server Module 1 Product Introduction 1.1 Product Overview This is a dual-Xeon VPX module based on the Intel Xeon Gold series processors, featuring high-speed connectors compliant with the VPX specification. Designed for high-performance, fully ruggedized servers, it integrates 128GB of DDR4 memory using surface-mounted memory chips and provides a rich set of robust I/O interfaces (six channels of SATA 3.0/USB 3.0/Gigabit Ethernet/VGA/RS232). The motherboard features high reliability, full ruggedization, high performance, and abundant interfaces, making it ideal as the core motherboard for reliable, ruggedized hyper-converged computing servers. The motherboard measures 233.35mm (width) × 270mm (length), with a board thickness ≤2.4mm. 1.2 Product Photograph ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138379589/01_ccbf58837b9ffd216b21eb4af983cdfc --- ## 9U_VPX Signal Processor, Heterogeneous Computing Platform for Sensor Big Data - URL: https://intl.sienovo.cn/blog/138379543 - Date: 2024-05-01 - Tags: #SignalProcessing ### 9U_VPX Signal Processor 1 Introduction 1.1 Product Overview The 9U_VPX Signal Processor is a high-speed data recording, storage, and processing system designed for front-end RF systems. Developed to address the multiple challenges faced by military electronic information systems—such as diverse target types, increasingly complex battlefield environments, and diversified mission requirements—this system serves as a high-performance data recording and storage solution. The signal processor handles the recording, storage, playback, and management of sensor big data. The signal processor consists of multi-port fiber modules, high-speed real-time information processing modules, integrated management and configuration modules, and large-capacity data storage modules. It provides users with the following capabilities: - Real-time forwarding and processing of high-speed data; - High-speed data recording and playback services (user data formats are customizable); - Centralized data ma --- ## Hi3519AV100 Processor High-Speed Global Shutter Camera - URL: https://intl.sienovo.cn/blog/138350652 - Date: 2024-04-30 - Tags: #DigitalCamera High-speed imaging has long been a demanding frontier in machine vision: capturing a license plate on a vehicle traveling at highway speed, or freezing the trajectory of a tennis ball at the moment of impact, requires a camera that can deliver sharp frames without motion blur, distortion, or rolling-shutter artifacts. This post introduces a camera module built around the Hi3519AV100 SoC that addresses exactly these requirements — combining a 1-inch global shutter sensor, on-chip AI inference, and high-frame-rate H.264/H.265 encoding in a single compact design. ## Why Global Shutter Matters for High-Speed Scenes Consumer and standard industrial cameras typically use a **rolling shutter** mechanism: each row of the image sensor is exposed and read out sequentially, top to bottom. When the subject moves faster than the readout time, objects appear skewed or "jello-like" — a well-known artifact in sports footage and traffic enforcement imaging. A **global shutter** sensor exposes every --- ## Miniaturized Low-Power AI Camera Based on RK1126, Supporting Human Attribute Recognition, Facial Feature Detection, Hard Hat Detection, and More - URL: https://intl.sienovo.cn/blog/138350371 - Date: 2024-04-30 - Tags: #AI, #DigitalCamera We offer a customizable AI camera hardware and software development platform. The hardware is built around the Rockchip RV1126 processor solution, compatible with Sony IMX series image sensors, supporting PoE (Power over Ethernet) for both power supply and data transmission. Designed with a standard 38-board structure, it enables rapid, customizable enclosure design, supporting the full process from development and verification to mass production. Horus provides a complete SDK with a foundational camera platform, including system software, drivers, image processing, and AI application interfaces. It supports multiple programming languages such as Python, C, and C++, significantly accelerating the development cycle from AI algorithm prototyping to hardware deployment. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138350371/01_d0dab06573657d9e4da13ce8c4df6df7.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138350371/02_ba2acb1026f734189eb15ce30f3469e7 --- ## SMU Source Measurement Unit Platform - URL: https://intl.sienovo.cn/blog/138350248 - Date: 2024-04-30 - Tags: #SourceMeasurePlatform A precision Source Measurement Unit (SMU) is one of the most versatile instruments in electronic test and measurement, combining sourcing and measurement capabilities in a single compact package. This post introduces Sienovo's SMU platform — what it does, how it is architected, and where it fits on a modern manufacturing line. ## What Is a Source Measurement Unit? An SMU is an instrument that can simultaneously force (source) an electrical stimulus and measure the resulting response. Unlike a standalone power supply or a standalone multimeter, an SMU operates in all four quadrants of the voltage–current plane: - **Quadrant I** — source positive voltage, sink positive current (normal load) - **Quadrant II** — source positive voltage, source positive current (active load charging) - **Quadrant III** — source negative voltage, sink negative current - **Quadrant IV** — source negative voltage, source positive current This four-quadrant capability means a single instrument can emulate a --- ## ARM+FPGA Modular Instrument Based on ZYNQ7020 - URL: https://intl.sienovo.cn/blog/138350092 - Date: 2024-04-30 - Tags: #FPGADev, #ARMDev ## Modular Instrument Platform Based on ARM+FPGA The modular instrument platform is a cutting-edge solution that combines the power of ARM processors with the flexibility of Field-Programmable Gate Arrays (FPGAs). This platform is designed to provide a comprehensive test and measurement solution for various applications, from verification to prototyping and mass production. In this article, we will explore the features and benefits of this modular instrument platform, which has gained recognition from leading international customers. ### Overview of the Modular Instrument Platform The modular instrument platform is built around an FPGA controller, paired with a rich and flexible selection of instrument modules such as multimeters, oscilloscopes, signal generators, data loggers, and audio analyzers. This selection of instrument modules allows users to customize their test and measurement setup to suit their specific needs. ### Embedded Form Factor One of the key features of the mod --- ## [Domestic NI Alternative] NI-9235 10 kS/s/ch, 120 Ω Quarter-Bridge Strain Gauge, 8-Channel C Series Strain/Bridge Input Module - URL: https://intl.sienovo.cn/blog/138345536 - Date: 2024-04-30 - Tags: #DomesticReplacement The NI-9235 is a high-performance C Series strain/bridge input module designed for dynamic strain measurement applications where precise, synchronized data acquisition across multiple channels is essential. This post examines the module's key specifications, its technical strengths, and the growing landscape of domestic alternatives that replicate its capabilities for industrial and test-and-measurement applications. ## What the NI-9235 Does At its core, the NI-9235 is an 8-channel C Series module optimized for quarter-bridge strain gauge measurements. It samples at up to **10 kS/s per channel**, and because all eight channels sample simultaneously — not in a round-robin multiplexed fashion — every data point is time-coherent across the full channel array. That simultaneous sampling architecture is the defining characteristic that separates the NI-9235 from lower-cost alternatives and makes it appropriate for transient and shock-event capture. The module is built around **120 Ω quar --- ## [Domestic NI Alternative] NI-9219 100 S/s/ch, 4-Channel C Series Universal Analog Input Module - URL: https://intl.sienovo.cn/blog/138345188 - Date: 2024-04-30 - Tags: #NI, #DomesticReplacement ## Overview The NI-9219 is one of National Instruments' most versatile C Series modules, purpose-built for engineers who need a single hardware slot to cover a wide variety of sensor types. Rather than committing an entire chassis to one measurement domain, the NI-9219 lets each of its four channels operate independently — measuring a thermocouple on channel 0 while simultaneously reading an RTD on channel 1 and a full-bridge strain gauge on channel 2. This article introduces the module's capabilities and discusses why domestic (Chinese-manufactured) alternatives to this class of instrument are gaining traction in industrial and research applications. ## What the NI-9219 Measures The NI-9219 is rated at **100 samples per second per channel (S/s/ch)** — a deliberate design choice. Universal analog input modules like this one prioritise accuracy and flexibility over raw throughput. At 100 S/s/ch the module can resolve slow-moving physical phenomena (temperature, mechanical strain, wei --- ## 6UVPX龙芯3A3000+国产显卡，VPX 3U 龙芯2K主板，龙芯3A3000 VPX 3U主板 - URL: https://intl.sienovo.cn/blog/138317593 - Date: 2024-04-29 - Tags: #Loongson, #VPX China's defense, aerospace, and industrial automation sectors have long depended on imported x86 and PowerPC processors for ruggedized embedded computing. That dependency is shrinking. The three boards covered here — a 6U VPX single-board computer built around the Loongson 3A3000, a compact 3U VPX board based on the Loongson 2K1000, and a second 3U VPX design also using the 3A3000 — represent a maturing domestic ecosystem that pairs MIPS-compatible Chinese processors with the VPX (VITA 46) backplane standard used throughout high-reliability embedded systems worldwide. ## Background: Loongson Processors and the VPX Standard The Loongson (龙芯) processor family is developed by the Institute of Computing Technology, Chinese Academy of Sciences, and manufactured under the Loongson Technology brand. The 3A3000 is a quad-core, MIPS64-compatible processor running at up to 1.2 GHz, designed for general-purpose computing in embedded and desktop applications. The 2K1000 is a dual-core, lower-pow --- ## Fully Indigenous LRM Airborne Recording Module Featuring Domestic VX690T FPGA Processor and Domestic Phytium CPU FT2000/4 - URL: https://intl.sienovo.cn/blog/138316886 - Date: 2024-04-29 - Tags: #Phytium, #DomesticReplacement, #LRM ### LRM Airborne Recording Module 1 Introduction 1.1 Product Overview The LRM Airborne Recording Module is an LRM data storage module built around a domestic VX690T FPGA processor, a domestic Phytium CPU FT2000/4, and a storage module. This module utilizes high-reliability LRM connectors and is centered on a processor group comprising a CPU and an FPGA. It offers various communication interfaces including Aurora, RapidIO, Gigabit Ethernet, fiber optic ports, RS422, CAN, and PCIe. Its capabilities include partitioned and classified storage of data files (Class A, B, and C), real-time recording, automatic indexing, playback, data loading/unloading, data encryption, data destruction, as well as Gigabit network routing and switching, configuration, time synchronization, visual media access, and self-testing. The total storage capacity can reach 2TB, with a real-time data recording and transfer bandwidth of no less than 1.6GB/s. The operating temperature range is -55℃ to +70℃. The reco --- ## All-domestic VPX 3U CAN Communication Board, VPX 3U KIO Card, PCIe x1 Expansion Digital I/O Interface - URL: https://intl.sienovo.cn/blog/138313159 - Date: 2024-04-29 - Tags: #Phytium, #VPX ## Overview Industrial computing platforms increasingly demand compact, ruggedized expansion cards that can bridge modern PCIe-based compute boards with legacy fieldbus and discrete I/O ecosystems. This post covers two all-domestic (国产) VPX 3U expansion cards built around a PCIe x1 interface: a CAN communication board offering eight isolated CAN channels, and a KIO card providing 16-channel digital input plus 16-channel digital output with built-in monitoring. Both cards are designed to fit the VPX 3U form factor, making them suitable for embedded military, railway, and industrial control applications where ruggedness, slot density, and domestic-supply-chain compliance are mandatory. ## VPX 3U CAN Communication Board ### What It Does The CAN communication board plugs into a PCIe x1 slot on a VPX backplane and exposes eight fully independent CAN 2.0 channels. Each channel is galvanically isolated, meaning a fault or ground-potential difference on the field side cannot propagate back --- ## All-Domestic Multi-Port Rugged Computer / Rugged Laptop / VPX Chassis Based on Phytium VPX - URL: https://intl.sienovo.cn/blog/138312556 - Date: 2024-04-29 - Tags: #Phytium ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138312556/01_8bbdd0920d9bab187dbea44e4a6d7744.png) ■ ATR Rugged System ■ Dual VPX Phytium motherboards, offering strong information processing capabilities; ■ Single motherboard supports triple-screen high-definition display ■ Supports AC and DC 24V power supply; ■ Slots: 2 motherboard slots, 1 power supply slot, 5 expansion slots ■ Interfaces: Ethernet port, USB 2.0 port, Serial port, VGA port, DVI port, PS/2 port, Video port, Audio port, etc. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138312556/02_130f67c277db0860c83d15c019642768.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138312556/03_864f77021fc21659d19bd9695647db22.png) This type of computer features rich signal interfaces, high configuration, excellent performance, high stability, and strong expansion capabilities, which can effectively meet user requirements; The computer is equipped with an internal lithium battery, a --- ## 飞腾S2500全国产主板为VPX 6U尺寸标准板卡在船舶、交通等的应用 - URL: https://intl.sienovo.cn/blog/138307780 - Date: 2024-04-29 - Tags: #Phytium ## S2500 Tengyun Processor Motherboard for VPX 6U Applications in Marine and Transportation China's push toward domestically sourced computing hardware has produced a growing ecosystem of processors, chipsets, and system boards designed to reduce reliance on foreign silicon. The Phytium (飞腾) S2500 processor — branded under the Tengyun (腾云) line — sits near the top of that stack, targeting high-reliability embedded and server applications. This post covers a VPX 6U form-factor motherboard built around the S2500, examining its specifications and the industrial use cases it is designed to serve, particularly in marine and transportation environments. ## What Is the Phytium S2500? The Phytium S2500 is a server-class processor developed by Tianjin Phytium Information Technology, a Chinese CPU vendor focused on ARM-architecture designs for domestic government, defense-adjacent, and industrial markets. The S2500 is an octa-channel DDR4 capable, multi-core ARMv8 processor, positioned as an --- ## Phytium FT2000/4 + Galaxy Kylin Fully Domestic VPX Architecture 6U Standard Board Card, Suitable for Marine, Transportation, and Other Fields - URL: https://intl.sienovo.cn/blog/138307611 - Date: 2024-04-29 - Tags: #Phytium, #SmartTransportation The XM-FT2000-VPX is a fully domestically-sourced single-board computer built around the VPX open standard, designed for mission-critical embedded deployments in marine systems, railway signaling, transportation infrastructure, and other harsh-environment applications. This post walks through the board's hardware architecture, interface complement, and key design decisions that make it suitable for defense-adjacent and industrial programs demanding Chinese supply-chain independence. ## The Case for a Fully Domestic VPX Platform VPX (VITA 46) is the ruggedized successor to VME, offering high-speed switched-fabric backplane interconnects in standard 3U or 6U form factors. It is the dominant architecture for military, avionics, and industrial signal-processing applications worldwide. Until recently, virtually every commercially available VPX SBC relied on x86 or PowerPC silicon from US or European vendors—an untenable dependency for Chinese defense and critical-infrastructure procuremen --- ## Phytium FT2000/4 CPCI 6U Standard Board, offering interfaces such as DVI, VGA, USB, Network, Serial Port, and SATA. - URL: https://intl.sienovo.cn/blog/138307453 - Date: 2024-04-29 - Tags: #Networking, #CPCI, #Phytium, #DomesticReplacement ## XM-FT2000 Phytium Motherboard: A CPCI 6U Board Built for Industrial Computing The XM-FT2000 is a CPCI 6U form-factor single-board computer (SBC) built around Phytium's FT2000/4 quad-core processor — one of China's domestically developed Arm-compatible CPUs targeting defense, industrial, and government infrastructure markets where supply-chain sovereignty matters. This post breaks down the board's hardware architecture, interface complement, and environmental ratings to help engineers evaluate it for rugged embedded deployments. ## Processor and Chipset: All-Domestic Silicon At the heart of the XM-FT2000 sits the **Phytium FT2000/4**, a quad-core processor running at a clock speed of ≥2.2 GHz. The FT2000/4 implements Armv8-A architecture and is fabricated using a 16 nm process node. It is designed as a direct domestic replacement for x86-class embedded processors in applications that previously relied on Intel Atom or similar low-power platforms. The processor supports 64-bit oper --- ## Phytium + FPGA Smart Transportation Joint Solution - URL: https://intl.sienovo.cn/blog/138307177 - Date: 2024-04-29 - Tags: #SmartTransportation, #Phytium, #AI, #FMSH In recent years, with the rapid development of national highway construction and the fast growth in highway mileage, while facilitating public travel and promoting economic and social development, highway traffic volume has also increased rapidly. Numerous problems such as vehicle speeding, overloading, illegal lane occupation by large vehicles, non-emergency stops, and traffic congestion on highways have gradually become prominent. The number of road traffic accidents and casualties on highways has shown a gradual upward trend, causing significant losses to the lives and property of the nation and its people. Comprehensive control of road conditions, standardized vehicle behavior, full coverage monitoring without blind spots, emergency rescue, vehicle and personnel supervision, and timely sharing of traffic information have become urgent requirements for the informatization development of various business systems within traffic management departments. ![](https://pub-048dcb96257f476 --- ## Phytium FT2000/4 + FPGA All-Domestic Smart Prevention and Control Solution for Metro and Public Transport - URL: https://intl.sienovo.cn/blog/138306903 - Date: 2024-04-29 - Tags: #SmartTransportation, #Phytium With the continuous increase in urban population density, establishing a sound, multi-dimensional public security prevention and control system, preventing and combating illegal and criminal activities in accordance with the law, and protecting citizens' personal rights, property rights, and personality rights, are crucial strategies for current comprehensive public security management, and important vehicles for demonstrating the modernization level of national governance. Urban public transport is an important component of modern transportation systems. Urban public transport generally maintains orderly development, playing a significant role in improving the quality and efficiency of urban public transport supply, alleviating urban traffic congestion, guiding the optimization of urban spatial structure, and improving the urban environment. The urban public transport system is highly coupled with urban construction and development. Its operational safety maintenance and public secur --- ## Fully Localized FMQL45AIT: Fudan Micro FPGA+AI Application in Subway X-ray Machines - URL: https://intl.sienovo.cn/blog/138305318 - Date: 2024-04-29 - Tags: #FPGADev, #AI In the "Core-Driven" section of the offline exhibition area, there were also two smallest exhibits: the "Qinglong No. 1 chips" – FMQL45T (referred to as Qinglong Qianmo) and FMQL45AIT (referred to as Qinglong Jindouyun) – publicly displayed for the first time by Shanghai Fudan Microelectronics Group. A sneak peek at the AI conference, in addition to the Qinglong chips, there were also drones that just set new records. Shanghai Fudan Microelectronics Group for the first time publicly exhibited the "Qinglong No. 1 chip" – FMQL45AIT (referred to as Qinglong Jindouyun). ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138305318/01_26d9cff94e257304fb8b93de181a0b06.png) Zeng Zhaobin, Deputy General Manager of Fudan Microelectronics Group, told reporters that "Qinglong Qianmo" is China's first domestically developed, proprietary, billion-gate level fully programmable fusion chip. It integrates a processing system based on a feature-rich quad-core processor and programmable logi --- ## Empowering V2X Collaboration: An i.MX8MPlus+FPGA-based Roadside Unit Main Control Solution for Smart Transportation/Rail Transit - URL: https://intl.sienovo.cn/blog/138304802 - Date: 2024-04-29 - Tags: #NXP+FPGA In recent years, China has been dedicated to the rapid development of smart transportation infrastructure. V2X (Vehicle-to-Everything) technology, as a core area deeply integrating autonomous driving with new infrastructure, has become a key focus for new infrastructure investment. In V2X systems, Roadside Units (RSUs), deployed as critical equipment along roadsides, play a pivotal role. These RSUs not only provide real-time road information to autonomous vehicles but also facilitate intelligent interaction between vehicles (V2V) and between vehicles and infrastructure (V2I), laying a solid foundation for the future development of smart transportation. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138304802/01_ed2553461db7ee460284af7b008738f8.png)  **1**  **Main Functions of RSU** Simply put, the main functions of an RSU are to improve traffic efficiency, assist autonomous vehicles, and aid vehicles in high-precision positioning and navigation. **Improve Traffic E --- ## Phytium + Fudan Micro FPGA: A Fully Domestic High-Definition Video Communication System - URL: https://intl.sienovo.cn/blog/138302666 - Date: 2024-04-29 - Tags: #AI, #Phytium, #FMSH, #DomesticReplacement In recent years, with the rapid development of electronic information technology, office methods trending towards globalization, networking, and intelligence have become increasingly popular across various industries. Against this backdrop, domestic software video conferencing systems have emerged. Software video conferencing systems enable people in different locations to hold meetings anytime, instantly meet, talk, exchange documents, share information resources, and collaborate on decision-making. They offer unparalleled communication advantages and can fully leverage existing networks and equipment to flexibly deploy a "remote conferencing communication platform," establishing applications for daily communication, work deployment, training and recruitment, and work exchanges within the system. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138302666/01_44856d21b19cf4297335f3584998b38e.png) The high-definition video communication system based on the Phytium chip arc --- ## Integrated Highway Toll Station Solution Based on Fully Domesticated Phytium D2000: Station Data Server, Station AI Server, Toll Collection System, Monitoring System - URL: https://intl.sienovo.cn/blog/138302276 - Date: 2024-04-29 - Tags: #SmartTransportation, #HighSpeedETC Integrated Highway Toll Station Solution Industry Transportation engineering and roadside facilities, as an important component of highways, are of great significance for urban connectivity and urban development. Therefore, the design and construction of dedicated toll stations around highways will effectively promote the connection between hub distribution systems and highways, significantly enhance the city's high-speed distribution capacity, and are of great importance for traffic travel efficiency and digital management and control. As an important component of highways, the highway toll station system's overall design goal is to achieve safe, environmentally friendly, and sustainable development in highway construction and operation management, improve management and service levels, and realize the design concept of "safety, environmental protection, comfort, and harmony." As localization requirements continue to increase, Phytium core processors, with their excellent performa --- ## 【NI Domestic Virtual Instrument】Domestic Alternative to NI-9056, 1.33 GHz Dual-Core CPU, 1 GB DRAM, 4 GB Storage, -20 °C to 55 °C, Artix-7 75T FPGA, 8-Slot CompactRIO Controller - URL: https://intl.sienovo.cn/blog/138252564 - Date: 2024-04-27 - Tags: #FPGADev As industrial automation and test-and-measurement engineering teams in China navigate supply-chain diversification, NI's cRIO-9056 CompactRIO controller has become a reference benchmark that domestic vendors must match. This post breaks down exactly what the cRIO-9056 delivers — processor, FPGA fabric, I/O connectivity, real-time OS, and environmental rating — and explains what engineers should look for when evaluating a domestic alternative targeting the same application space. ## What Is CompactRIO and Why Does It Matter? CompactRIO is NI's rugged embedded platform that combines a real-time processor with a reconfigurable FPGA in a single chassis. The key architectural insight is the tight coupling between the CPU and the FPGA: the processor handles high-level logic, communication, and data management, while the FPGA provides deterministic, hardware-timed I/O at nanosecond-level precision. C-Series modules — analog input, analog output, digital I/O, CAN, serial, and dozens of other --- ## [Domestic Virtual Instrument] Domestic Alternative to NI-9205 Module, ±10 V, 250 kS/s, 16-Bit, 32-Channel C Series Voltage Input Module - URL: https://intl.sienovo.cn/blog/138252503 - Date: 2024-04-27 - Tags: #FPGADev ## Domestic Virtual Instrument: A Cost-Effective Alternative to NI-9205 Module When it comes to high-channel-count and high-speed data acquisition systems, the National Instruments (NI) C Series modules are often the go-to choice. However, these modules can be quite expensive, making them less accessible to researchers and developers with limited budgets. In this article, we'll explore a domestic virtual instrument that offers a cost-effective alternative to the NI-9205 module, a ±10 V, 250 kS/s, 16-bit, 32-channel C Series voltage input module. ### Key Features of the NI-9205 Module The NI-9205 module is a popular choice among data acquisition enthusiasts due to its high channel count and high speed. It supports single-ended or differential analog input, with four programmable input ranges per channel. This allows users to adapt the module to various measurement applications. Additionally, the NI-9205 provides up to 60 V of overvoltage protection between the input channels and comm --- ## Implementing Garbage Classification and Video Object Classification Applications with AscendCL on Ascend AI - URL: https://intl.sienovo.cn/blog/138196105 - Date: 2024-04-25 - Tags: #AI, #Classification, #AudioVideo Nowadays, artificial intelligence is developing rapidly, and the pace at which AI empowers industrial development is accelerating, leading to a surge in "AI+" demands. However, significant challenges persist in the rapid deployment of AI applications: compatible hardware is required at the lower layer, and comprehensive technical support is needed at the upper layer; both are indispensable. To address this, Ascend has launched a series of industry SDKs and reference designs. By consolidating and horizontally replicating development experience and industry knowledge from various segmented scenarios across diverse industries, these offerings significantly lower the barrier, simplify development, and improve efficiency. Xinmai Technology, an important APN partner and gold distributor of Ascend, possesses strong independent hardware design capabilities. The two parties work closely together to create a software-hardware integrated computing foundation that better meets industry needs, em --- ## Application of RK3588S and ARM Array Servers in Virtualized Cloud Platforms - URL: https://intl.sienovo.cn/blog/138169772 - Date: 2024-04-24 - Tags: #ARMDev, #Server, #DevOps The RK3588 is Rockchip's first high-end 8nm flagship chip, launched at the end of 2021. The RK3588S is a cost-optimized variant tailored for consumer markets, based on the RK3588, with some peripheral interfaces reduced while retaining key components such as the CPU, GPU, and NPU. Its primary applications include high-end ARM tablets, ARM laptops, conference panels, ARM servers, intelligent robots, AI video encoding/decoding, IP cameras, NVR/XVR systems, industrial control systems, smart cockpits, and more. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138169772/01_cefab087085ba47466ea30f39b486725.png) The technical specifications of the RK3588S are as follows: | Parameter | Specification | Description | |----------|---------------|-------------| | CPU | 8-core, 4×A76 + 4×A55 | Up to 3.0GHz | | GPU | Mali-G610 MP4, supporting OpenGL ES 1.1, 2.0, and 3.2, OpenCL up to 2.2, and Vulkan 1.2 | | | VPU | Encode: Supports real-time 8Kp30 encoding for H.265/H.264
Decode: --- ## Application of RK3588-based, Fully Domestically Produced HarmonyOS Edge Computing Industrial PC in Intelligent Transportation ETC Toll Collection Systems - URL: https://intl.sienovo.cn/blog/138169507 - Date: 2024-04-24 - Tags: #HarmonyOS, #SmartTransportation, #HighSpeedETC, #DomesticReplacement ****1.1**** ****Product Introduction**** Driven by the rapid intelligent development needs of industries such as intelligent transportation and industrial internet, the XM-RK3588 edge processor was developed with OpenHarmony as its framework, embedding HarmonyOS, to create a highly intelligent, highly reliable, highly secure, and independently controllable edge processor. 图 1-1 边缘处理器 Figure 1-1 Edge Processor ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138169507/01_a0e3746b2076a0aee3841b4dad102b2b.png) HarmonyOS enhances IoT interconnection and interaction capabilities, giving the edge processor the following advantages: l Powerful support for connecting edge devices in complex scenarios, rapid deployment capability, and convenient replication capability. l Localized data processing and storage, reducing network bandwidth pressure and customer operating costs. l End-to-end data security management, with domestic OS + domestic chip, ensuring user data security. --- ## 8-Channel Standard 3U PXIe Multifunction Asynchronous Serial Communication Isolated Card, Supports RS232/422/485 Modes, Max 10Mbps, Supports Virtual COM Port - URL: https://intl.sienovo.cn/blog/138134276 - Date: 2024-04-23 - Tags: #EdgeComputing 8-Channel Standard 3U PXIe Multifunction Asynchronous Serial Communication Isolated Card, Supports ****RS232/422/485**** Modes, Max 10Mbps, Supports Virtual COM Port. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138134276/01_c35eaa42a50c376b7dc2d74bd1c8cd33.png) ****Product Features**** QC PXIe-7108 Number of Channels 8 Channels Communication Modes Supports RS232, RS422, RS485, DIP switch selectable Signal Isolation Method Input/Output Isolation Baud Rate RS232 MAX 1 Mbps RS422/485 MAX 10 Mbps FIFO 256 MBytes Transmit and Receive FIFO Data Format Parity Bit: None, Even, Odd, Space, Mark Data Bits: 5, 6, 7, 8 Stop Bits: 1, 1.5, 2 I/O Address/IRQ: BIOS Assigned Connector Port0-7: VHDCI68-1 PXIe_CLK100 Supported Interface PCI Express Gen1 X1 Serial Port Protection Onboard 15 KV ESD Protection and Surge Protection System Support Windows2000/XP/2003/Vista/Win7/Win10, Linux 2.4/2.6 Software Support LabVIEW, C, QT, etc. Programming Method Virt --- ## RK3588 + FPGA + Multi-channel HD CMOS Camera + AI Recognition and Analysis Integrated Solution - URL: https://intl.sienovo.cn/blog/138133778 - Date: 2024-04-23 - Tags: #FPGADev, #DigitalCamera, #AI 1. 1. Product Overview The INT-AIBOX-RK4 Smart Edge Analysis All-in-One Machine is a high-performance, low-power edge computing product. It is equipped with the domestically produced RK3588 TPU chip, featuring 6Tops of NPU computing power, and supports up to 8K video encoding and decoding. This product highly integrates high-precision AI intelligent algorithms based on computer vision and deep learning networks, as well as a comprehensive video intelligent management platform. The AI intelligent algorithms cover various algorithms for scenarios such as industrial parks, communities, construction sites, and campuses, which can be combined on demand and configured according to the scenario. The comprehensive video intelligent management platform supports front-end device management, real-time video preview, alarm push, forensic capture, online algorithm loading and optimization, data situational analysis large screen display, etc. The device is easy to operate and plug-and-play, whi --- ## Applications of Rugged Onboard Computers in Smart Rail Safety Solutions - URL: https://intl.sienovo.cn/blog/138132750 - Date: 2024-04-23 - Tags: #Security #### Smart Rail Safety Solutions Xinmai offers a range of onboard train solutions with sensing, diagnostic, AI, and wireless capabilities. They provide comprehensive scalability and future-proof functionalities for vehicle, wayside, signaling, power, obstacle detection, and data collection. **Applications:** * Railway Power Supply Monitoring * Onboard Train Safety Protection * Railway Track Monitoring * Driving Behavior Analysis ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138132750/01_683340c1773305959dab424b4eb4210c.png) #### Smart Onboard Solutions Smart onboard train solutions encompass a full range of products for locomotives and carriages, featuring high reliability, high scalability, and fully redundant systems. They comply with global standards and certifications and are field-proven. Smart onboard solutions can be rapidly deployed and integrated with existing systems. **Applications:** * Train Control and Management System (TCMS) * Vehicle --- ## [Domestic Solution] Avionics Communication Bus Products Offer Native Support for Protocols like MIL-STD-1553 and ARINC 429 - URL: https://intl.sienovo.cn/blog/138131895 - Date: 2024-04-23 - Tags: #Networking Avionics Communication Bus Avionics communication bus products offer native support for protocols such as MIL-STD-1553 and ARINC 429. These products are used for the development, production, and system testing required in avionics applications. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138131895/01_41865a06429f4816001e8dce8ab0ebbb.png) ### PXIe, 2-Channel PXI ARINC-664 Interface Module The AIM ARINC-664 features an onboard processor that automatically handles all protocol-related activities, including transmit scheduling and receive buffering, with minimal interaction from the host in real-time applications. This module combines FPGA technology with a RISC processor to support ARINC-429 bus protocol processing and precisely schedule simulated information. The AIM ARINC-664 provides up to two channels in a 3U form factor, with all channels software-programmable for various receive (Rx) or transmit (Tx) modes. You can use this module for applications such as testin --- ## Rugged Industrial PCs in Weighing Systems + Forklift Computers, Integrated Weighing, Dimensioning, and Scanning Machines, and Logistics Sorting Line Workstation Industry Applications - URL: https://intl.sienovo.cn/blog/138026261 - Date: 2024-04-21 - Tags: #Computer, #EdgeComputing, #AI ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138026261/01_2fee5f585b794ae4f80d4fae30ad217f.jpeg) **Weighing Systems + Forklift Computers Industry Applications** **Background Introduction** By installing weighing sensors on forklifts and automatically detecting lifting pressure, the pressure signal is converted into a current or voltage signal. After A/D conversion, the analog signal becomes a digital signal. This data is then processed by a microprocessor and transmitted to the onboard computer via Bluetooth, serial port, or USB interface. This enables forklifts to load and unload goods according to plan, saving time and effort, preventing overloading and over-transportation, reducing equipment wear, lowering transportation costs, and improving work efficiency. At the same time, in case of forklift overload, the onboard computer can provide alarm information such as audible, visual, and text alerts, enhancing the safety of forklift operations. This solution is widely --- ## Rugged Industrial PCs in Smart Warehousing Industry: RFID + Forklift PC and Barcode Scanner + Forklift PC Applications - URL: https://intl.sienovo.cn/blog/138025913 - Date: 2024-04-21 - Tags: #Computer, #EdgeComputing, #AI ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138025913/01_fe26d2ff3c8638e14944ad1ad6210ae6.jpeg) ##### **Smart Warehousing Industry Applications** The mission of technology is to provide customers in the smart logistics industry with the best industrial PC solutions. To improve efficiency in warehouses or logistics distribution centers, we have designed a series of industrial PCs to meet the diverse application needs of warehousing. These include professional forklift-mounted computers and related accessories, AGV controllers, and industrial LCD PCs specifically designed for smart weighing integrated machines, among others. **Industry Applications** ● Barcode Scanner + Forklift PC Solution ● RFID + Forklift PC Solution ● Cold Storage Forklift PC Solution ● Weighing System + Forklift PC Solution ● Weighing, Measuring, and Scanning Integrated Machine Solution ● Logistics Sorting Line Workstation Solution ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/13 --- ## Rugged Industrial PCs in Smart Terminal Gate, OCR (Container Number Recognition), and Container Truck Onboard Computer Industry Applications - URL: https://intl.sienovo.cn/blog/138025307 - Date: 2024-04-21 - Tags: #EdgeComputing, #Computer, #AI ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138025307/01_92c4a08315ece848fd7dd17db7e8bf9c.jpeg) ##### Container Truck Onboard Computer Applications **Background Introduction** For the dispatch and operation of container trucks at terminals, various platforms of onboard computers (VT series) and onboard LED displays (VLD series) have been designed in conjunction with the terminal's TOS system. We also provide various mounting brackets to secure the onboard computers in confined cabins; additionally, a range of antenna options (stick, ceiling-mount, or fiberglass), wide-voltage waterproof power supplies, and waterproof external keyboards are offered, effectively enhancing customer stability and convenience. **Solution Requirements** ● Small to medium-sized touch display all-in-one onboard computer ● Onboard LED display ● Mounting brackets ● Wide-voltage waterproof power supply, etc. **Solution** The onboard computers (VT series) offer 7-inch to 10.4-inch touch displ --- ## Rugged Industrial Computers in Smart Port Solutions: Industry Applications for Gantry Crane / Straddle Carrier Onboard Computers - URL: https://intl.sienovo.cn/blog/138024897 - Date: 2024-04-21 - Tags: #Computer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138024897/01_8f53dd75f1379b96adac189fadce7797.jpeg) ##### Smart Port Industry Applications For port operations, optimizing the various processes of containers from ship to yard to exit gate, and achieving the goals of improving efficiency and reducing costs, are the most critical issues for port operational profitability. To enable container terminal customers to confidently use the TOS (Terminal Operating System) to dispatch and command various cranes, forklifts, trucks, and personnel at the terminal, a series of industrial computers have been designed to suit the diverse operating environments of container terminals. These are coupled with stable wireless communication networks and related technologies, allowing the control center to easily command the computer terminals installed in any corner of the port, thereby enhancing the port's operational efficiency. **Industry Applications** ● Container Truck Onboard Computers --- ## Application of Rugged Industrial PCs in the Tire Building Machine Equipment Industry - URL: https://intl.sienovo.cn/blog/138024651 - Date: 2024-04-21 - Tags: #Computer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138024651/01_52822276b04dc865402687ca9e92c931.jpeg) ##### **Application in the Tire Building Machine Equipment Industry** **Project Background** China is a major country in tire production and export. In the tire manufacturing process, the building (forming) process is a critical step. It involves assembling semi-finished components into a tire carcass (green tire) on a tire building machine according to technical specifications. The process is relatively complex, requiring high precision in equipment processing and positioning. Major tire building machine manufacturers are all striving to research and develop efficient, precise, and simple tire building equipment. China's tire equipment manufacturers are also continuously innovating in terms of process, technology, and efficiency to develop machines that meet production requirements. DPC series industrial panel PCs offer reliable and stable performance, adapt to harsh ind --- ## Application of Ruggedized Domestic Industrial PCs in Tire Curing Machine Solutions - URL: https://intl.sienovo.cn/blog/138024528 - Date: 2024-04-21 - Tags: #Computer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138024528/01_b809cb2a357091c6ee70b619853e5bbd.jpeg) ##### **Tire Curing Machine Solution** **Project Background** The curing process is the final step in tire production. To enhance the tire's wear resistance and rolling resistance, tires undergo a curing process to increase their strength. The effective control of the three key elements of curing directly impacts the quality of the final product. Traditional control systems, which involve numerous buttons, switches, and indicator lights, require manual operation. Modern intelligent control systems can automatically adjust curing process parameters to achieve optimal curing quality, improve production efficiency, and enable fully automated management of the curing operation. **Solution Requirements** ● The control host needs to be high-performance, capable of quickly and accurately processing various data. ● The on-site environment is harsh, requiring high-level protectio --- ## Rugged Domestic Industrial Computers: Applications in Electronic Kanban Systems and Machine Vision in Automotive Production Lines - URL: https://intl.sienovo.cn/blog/138011217 - Date: 2024-04-20 - Tags: #Computer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/138011217/01_ba0d99c9c23287a2d2703038944a8098.png) ##### **Applications in Electronic Kanban Systems** The core of intelligent electronic kanban systems lies in achieving full visualization and automated management in factories, ultimately improving efficiency, reducing costs, and enhancing product quality. The hardware of an electronic kanban system mainly consists of two components: a miniature industrial computer and a display terminal (flat-screen TV or LCD). **Requirements** ● Support for high-definition large-screen display ● Support for wired and wireless networking ● Compact size for easy installation **Solution** ● EBC-1122 miniature industrial computer + flat-screen TV, supporting large-screen display ● Supports both wired network and Wi-Fi communication **Advantages** ● Fanless, low-power industrial design ensures long-term stable operation ● Supports VESA and wall-mount installation ● Palm-si --- ## AI Smart Edge Analysis All-in-One Machine, Up to 10.6 TOPS, Capable of Simultaneously Processing 8 Channels of HD Video, Built-in 30+ AI Algorithms - URL: https://intl.sienovo.cn/blog/137964598 - Date: 2024-04-19 - Tags: #AI, #AudioVideo 1. 1. Product Overview The XM-AIBOX-8 AI Smart Edge Analysis All-in-One Machine is a high-performance, low-power edge computing product. Equipped with the domestic TPU chip BM1684, it boasts an INT8 computing power of up to 10.6 TOPS, can simultaneously process 8 channels of HD video, and supports hardware decoding for 8 channels of 1080P HD video and encoding for 1 channel. This product highly integrates high-precision AI intelligent algorithms based on computer vision and deep learning networks, as well as a comprehensive video intelligent management platform. The AI intelligent algorithms cover various scenarios such as industrial parks, communities, construction sites, and campuses, and can be combined and configured on demand according to the specific scenario. The comprehensive video intelligent management platform supports front-end device management, real-time video preview, alarm push, forensic capture, online algorithm loading and optimization, data situational analysis --- ## AI Smart Edge Analysis Appliance, 32 TOPS Computing Power, Simultaneously Processes 32 Channels of 1080p HD Video - URL: https://intl.sienovo.cn/blog/137964036 - Date: 2024-04-19 - Tags: #AI, #AudioVideo 1. 1. Product Overview The XM-AIBOX-32 AI Smart Edge Analysis Appliance is a high-performance, low-power edge computing product. Equipped with the BM1684X main chip, it boasts an INT8 computing power of up to 32 TOPS, FP16/BF16 computing power of up to 16 TFLOPS, and FP32 computing power of up to 2 TFLOPS. It can simultaneously process 32 channels of HD video, supporting hardware decoding for 32 channels of 1080P HD video and encoding for 12 channels. This product highly integrates high-precision AI intelligent algorithms based on computer vision and deep learning networks, as well as a comprehensive video intelligent management platform. The AI intelligent algorithms cover various scenarios such as industrial parks, communities, construction sites, and campuses, and can be combined on demand and configured according to the specific scenario. The comprehensive video intelligent management platform supports front-end device management, real-time video preview, alarm push, forensic --- ## 24-bit AD Resolution, 256 Ksps * 16 Channels Domestic Data Acquisition Card, uV-level Acquisition, Supports IEPE - URL: https://intl.sienovo.cn/blog/137920121 - Date: 2024-04-18 - Tags: #uv, #AI, #DataAcquisition, #VirtualInstrument 24-bit AD resolution, 256 Ksps * 16 channels, uV-level acquisition, USB data transfer, supports multiple programming languages such as C, LABVIEW, MATLAB, Python, provides examples, and supports secondary development. ## **XM7016 - Ethernet Data Acquisition Card** The XM7016 is an Ethernet-based high-speed data acquisition card, featuring 16 true differential input channels, 24-bit resolution, a maximum sampling rate of 256 ksps per channel, a total synchronous sampling rate of 4.096 Msps across 16 channels, precision pre-gain amplification, and integrated IEPE/ICP hardware support. This product utilizes multiple high-precision 24-bit ADC units and a pre-differential amplification module developed by our company over many years. This design provides advantages such as high speed, high resolution, high precision, ultra-low noise, high common-mode rejection ratio, wide measurement range, and low temperature drift, making it suitable for various applications requiring precise high-spee --- ## Ethernet 24-bit Strain/Bridge Data Acquisition Card, Replacement for NI 9237 - URL: https://intl.sienovo.cn/blog/137913270 - Date: 2024-04-18 - Tags: #DataAcquisition 1. 1.******Features Overview****** *    The XM-BRG is an Ethernet-based high-speed strain gauge/pressure bridge signal acquisition card. It features 8-channel (4-channel for the -4 model) true differential inputs, 24-bit resolution, a maximum sampling rate of 102.4 ksps per channel, totaling 819.2 ksps for 8 synchronous channels (409.6 ksps for the -4 model), precision pre-gain amplification, and integrated hardware support for excitation sources required by bridge sensors. This product utilizes multiple high-precision 24-bit ADC units and a pre-differential amplifier module developed by our company over many years. This gives the product advantages such as high speed, high resolution, high accuracy, ultra-low noise, high rejection ratio, wide measurement range, and low temperature drift, making it suitable for various applications requiring precise and high-speed data acquisition. *  LAN communication uses TCP/IP and a proprietary switched communication protocol with a built-in --- ## Industrial PC Applications in ESOP Workstations - URL: https://intl.sienovo.cn/blog/137880546 - Date: 2024-04-17 - Tags: #Computer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137880546/01_a1969ff9b5e2221614d038fb23990e3a.jpeg) **ESOP Workstation Industry Applications** **Project Background** E-SOP is a management information platform that enables the digitalization of work instructions and provides unified management and centralized control. Xinmai Technology's ESOP terminal is a compact, full-featured, cost-effective industrial PC. The upper layer connects to the MES system via the network, while the lower layer connects to a display to show work instructions. The ESOP control terminal features stability and durability, making it suitable for 24/7 continuous operation in factories. **Solution Requirements** ● On-site workstations are not fixed, locations are complex, and installation conditions are demanding. ● Factories operate 24 hours a day, so workstations must be capable of uninterrupted operation. ● Requires both wired and wireless communication capabilities. **Solution** The provided --- ## Fanless Embedded Industrial PC Application in MES Workstation Industry - URL: https://intl.sienovo.cn/blog/137866857 - Date: 2024-04-17 - Tags: #AI, #EmbeddedHardware, #Computer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137866857/01_1799ee902919d8caaea2aca494831280.jpeg) ##### **MES Workstation Industrial Applications** **Project Overview** The MES workstation is located in the middle layer of the entire system, responsible for integrating all factory systems and forming a data platform. The upper layer is ERP, while the lower layer connects to PLCs, data acquisition, and display equipment, etc. MES automatically receives ERP business orders, schedules production, and issues production instructions to operators or lower-level equipment. Xinmai Technology specializes in MES application scenarios and has designed and produced a series of industrial panel PCs for MES workstations. **Solution Requirements** ● Unfixed on-site workstations, complex locations, and harsh installation conditions. ● A wide variety of information collection equipment, requiring the workstation to have multiple I/O interfaces. ● The factory operates 24 hours a day, --- ## Fully Localized Fanless Embedded In-Vehicle Computer for Fleet Management Industry Applications - URL: https://intl.sienovo.cn/blog/137866408 - Date: 2024-04-17 - Tags: #MCU, #EmbeddedHardware ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137866408/01_755b4d22fcae74a09d0093d5be9df2b6.png) ##### **Fleet Management Embedded In-Vehicle Industry Applications** Fleet management solutions can effectively address the challenges of managing a large number of vehicles, and when combined with a dispatch system, they ensure more precise and effective execution of commands. They provide real-time monitoring of vehicle status, routes, and locations, guiding drivers for safe and orderly operation, and effectively reducing insurance costs, accident rates, and wear and tear on tires and components. Solution Requirements ● Industrial-grade fanless compact rugged design ● Powerful network management capabilities ● Rich I/O interfaces for effective vehicle status detection ● Robust vibration resistance ● Wide voltage input **Solution** Introducing a basic, general-purpose modular in-vehicle computer, featuring a compact fanless structural design. It is equipped with an Inte --- ## Industrial Application of Fully Localized Fanless Embedded In-Vehicle Computers in Ambulance Remote Diagnostics - URL: https://intl.sienovo.cn/blog/137866322 - Date: 2024-04-17 - Tags: #Computer, #VehicleComputer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137866322/01_9d029ef689b9e166ba530e633eaf704b.jpeg) **Industrial Application of Ambulance Remote Diagnostics** **Background** Providing rapid diagnosis and treatment for emergency patients as quickly as possible is crucial for improving patient rescue success rates. Therefore, advanced ambulance systems are exploring how, immediately after a patient enters an ambulance, information from various examination instruments can be quickly transmitted back to the hospital for preliminary diagnosis by doctors, who then guide the medical personnel in the ambulance on treatment actions. To implement this solution, it is indispensable for ambulances to be equipped with mobile in-vehicle computers that can operate stably in a vehicle environment, possess powerful computing capabilities, and transmit information from various instruments and imaging data from the ambulance back to the hospital via a fast wireless network. **Solution Req --- ## Fully Localized Fanless Embedded Vehicle PCs for Agricultural Vehicles and Steel Plant Overhead Crane Applications - URL: https://intl.sienovo.cn/blog/137866148 - Date: 2024-04-17 - Tags: #Computer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137866148/01_a4e8c8d1e7f447a9f7cefed5bbac4b54.jpeg) ##### **Agricultural Vehicle Industry Applications** **Background Introduction** The primary function of current in-vehicle computers for agricultural vehicles is to achieve precise positioning and navigation. More advanced systems aim to enable autonomous driving for agricultural vehicles and communicate with relevant sensors (e.g., soil depth sensors, fuel level sensors, etc.) to realize more automated and intelligent functions. **Solution Requirements** ● Industrial-grade fanless embedded vehicle PC ● Equipped with wireless communication capabilities and precise GPS positioning ● Accommodates unstable on-board battery voltage of various agricultural vehicles ● Requires connection to various sensor devices via I/O interfaces **Solution** To meet the demands of agricultural vehicles, Xinmai has designed a series of rugged in-vehicle computers. These units feature a rob --- ## Fanless Embedded In-Vehicle Computers in the Mining Vehicle Industry - URL: https://intl.sienovo.cn/blog/137865939 - Date: 2024-04-17 - Tags: #Computer ##### **Applications in the Mining Vehicle Industry** **Background Introduction** The modern mining industry faces many challenges, with safety being paramount. Whether working underground in mines or on the surface, employee safety must be guaranteed. Therefore, advanced mining vehicles must integrate dedicated in-vehicle computers that can operate stably in extremely harsh mining environments to ensure task completion. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137865939/01_92fb312954c97ee5beca6ef808474588.png) **Solution Requirements** **●** Industrial-grade fanless embedded in-vehicle computers **●** Equipped with wireless communication and precise GPS positioning capabilities **●** Accommodate unstable in-vehicle battery voltages of various mining vehicles **●** Requires connection to various sensor devices via I/O interfaces **Solution** In-vehicle computers, designed specifically for the mining industry environment, feature an all-weather rugged design and --- ## Fleet Management Solutions with Telematics for Construction, Logistics, and Firefighting Vehicles - URL: https://intl.sienovo.cn/blog/137857061 - Date: 2024-04-17 - Tags: #AI Transportation is crucial to the global economy, with long-haul trucks, in particular, playing a vital role in today's supply chains. Currently, freight logistics faces many challenges, including rising fuel prices and emission pollution. Due to the large size and carrying capacity of heavy-duty trucks, they generate a larger carbon footprint. Domestically, medium and heavy-duty trucks account for only 5% of the total vehicles on the road but contribute to 20% of carbon emissions. Therefore, vehicle telematics technology is applied to fleet management to help fleets make better decisions, improve operational and logistics planning efficiency, and achieve fleet management sustainability.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137857061/01_af1f6d06d1ecc96405ccd88f67c0455a.png) **Vehicle Telematics-Based Fleet Management Solutions** How does vehicle telematics play a role in fleet management, leveraging modern technologies such as wireless networks (Wi-Fi, 4G/5G), --- ## Intelligent Port Applications on x86/Domestic Platforms - URL: https://intl.sienovo.cn/blog/137818378 - Date: 2024-04-16 - Tags: #AI, #harmonyos ## Intelligent Port Applications on x86/Domestic Platforms Optimizing the flow of containers from ships to the yard and out of the facility is a critical factor in the profitability of port operations. To achieve this, Terminal Operating Systems (TOS) are used to schedule and control various cranes, forklifts, trucks, and personnel. However, ensuring seamless communication and control across the terminal is essential for efficient operations. In this article, we will explore the intelligent port applications developed by Davicom, a series of industrial computers tailored to different container terminal environments. ### Industry Applications Davicom has designed a range of industrial computers for various applications in container terminals. These include: * **In-vehicle computers for container trucks**: These computers are designed to be installed in container trucks, providing real-time data and control capabilities to optimize truck operations. * **In-vehicle computers for gantr --- ## Application of Hongmeng OS and Fully Domestic Industrial Tablet PCs in MES System Data Collection Terminals - URL: https://intl.sienovo.cn/blog/137674256 - Date: 2024-04-12 - Tags: #harmonyos, #Computer, #Huawei Driven by the wave of Industry 4.0, traditional manufacturing industries face numerous challenges such as rising raw material and labor costs, disorganized shop floor management, complex order structures, difficulty in improving production efficiency, and inability to monitor production anomalies in real time. These issues make it impossible to meet the basic requirements of digital factories, let alone align with Industry 4.0 standards. MES (Manufacturing Execution System) is an information management system designed for the shop-floor execution layer of manufacturing enterprises. MES provides enterprises with a comprehensive set of management modules, including manufacturing data management, production planning and scheduling, production dispatching, inventory management, quality management, human resource management, work center/equipment management, tooling management, procurement management, cost management, project dashboard management, production process control, bottom-level --- ## ARM/X86+FPGA Solutions for the Rail Transit and Engineering Vehicle Industries - URL: https://intl.sienovo.cn/blog/137674061 - Date: 2024-04-12 - Tags: #FPGADev Shenzhen launched its first driverless metro line—Shenzhen Metro Line 20, which can be considered a groundbreaking breakthrough for Shenzhen Metro. Behind the continuous advancements in intelligent transportation lies the need for highly stringent hardware, software, and other control systems. Driverless metro operation means that projects such as signal systems, communication systems, integrated monitoring systems, and platform screen door engineering must undergo strict acceptance procedures. The continuous improvement of industrial intelligent control systems further provides a robust and reliable foundation for intelligent transportation. ![控汇在轨道交通行业的解决方案](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137674061/01_79c4f709bac49c3d812c16c9d0816328.jpeg) Concept of Intelligent Transportation: Intelligent Transportation System (ITS) is the future direction of transportation systems. It effectively integrates advanced information technology, data communication transmissi --- ## Rockchip RK3568/RK3588 + HarmonyOS: MineHarmony Industrial Control Panels, Boards, and Gateways Driving Digital and Intelligent Transformation in Mining - URL: https://intl.sienovo.cn/blog/137648345 - Date: 2024-04-11 - Tags: #BigData From April 10 to 12, the 2nd China International Mining Equipment and Technology Exhibition was held in Xi’an under the theme “Green Intelligence Innovation, Joining Hands for a Win-Win Future.” Xinmai Technology showcased its MineHarmony solutions and products, accelerating digital intelligence upgrades and domestication transformation in the mining industry. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137648345/01_31693a8a1f5d264f10a7523a1c5b39c0.jpeg) As an enabling partner of Huawei's MineBrigade MineHarmony ecosystem, Xinmai Technology has built a comprehensive innovation product system covering production, operations, and data acquisition by deeply integrating cutting-edge digital technologies with mining application scenarios based on HongZOS and MineHarmony. This has advanced intelligent mine construction and accelerated MineHarmony compatibility adaptation and certification. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137648345/02_fdca --- ## Easily Harnessing AI with FPGAs - URL: https://intl.sienovo.cn/blog/137629895 - Date: 2024-04-11 - Tags: #FPGADev, #AI Launching artificial intelligence applications has never been easier! Thanks to FPGAs like the Xilinx Zynq UltraScale+ MPSoC, AI can now also be used offline or deployed and utilized at the edge. They can be used to develop and deploy machine learning applications for real-time inference, making AI integration into applications a breeze. Image detection or classification, pattern or speech recognition are driving upgrades in industries such as manufacturing, healthcare, automotive, and financial services. --- **Rapidly Enabling AI-based FPGA Applications** Artificial intelligence is occupying an increasing number of application and life scenarios, such as image detection and classification, translation, and recommendation systems. The number of applications based on machine learning technology is vast and continues to grow. By using core board modules from Realsun that combine FPGAs and ARM processors, using AI offline and at the edge has become easier than ever before. Artificial --- ## FPGA-based OMEGA Tokyo Olympics Timer - URL: https://intl.sienovo.cn/blog/137629776 - Date: 2024-04-11 - Tags: #FPGADev ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137629776/01_efb6160a0b0959c65a11e4a846e91ce0.jpeg) As of 2019, 31 Olympic Games have been held. Of these, OMEGA (Ω) has provided the timing equipment for 27 editions. This year's Tokyo Olympics will be the 28th. Swiss Timing has developed the ultra-high precision handheld device PowerTime 3, based on the Mars ZX2 core board. This device is designed for timing large-scale sporting events like the Olympics and will be used for timing at the Tokyo Olympics. While Swiss Timing might not be a familiar name to everyone, its parent company, Swatch Group, is widely known. Swatch Group owns 18 watch brands, including Swatch, Tissot, Longines, and OMEGA, all of which are very common brands domestically. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137629776/02_e7b3553b113b289873fd401d87d55605.png) The PowerTime 3 baseboard integrates a large number of specialized components, including a precision clock & GPS, tri --- ## Application of FPGA Core Board in Sonar Systems - URL: https://intl.sienovo.cn/blog/137629582 - Date: 2024-04-11 - Tags: #FPGADev ### Introduction Sonar systems use sound pulses to detect, identify, and track underwater objects. A complete sonar system consists of a control and display unit, a transmitter circuit, a receiver circuit, and a transducer that functions as both an emitter (speaker) and a detector (high-sensitivity microphone). ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137629582/01_334439c68f83279fc2317c27f5dc8d55.png) Sonar System Diagram ### Technical Challenges The sonar transmitter discussed in this article is a phased array transmitter capable of emitting frequencies from 10 kHz to 100 kHz. The system employs an array of transmitter modules, with each module capable of driving eight sonar transducers. The FPGA design incorporates several unique modules: an ARM processing unit (Intel HPS), a waveform generator, channel interfaces, clock and chip timing, system monitoring and control, and status registers. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/1376295 --- ## FPGA Applications in Healthcare, Illustrated by 4K Medical Endoscopy - URL: https://intl.sienovo.cn/blog/137629162 - Date: 2024-04-11 - Tags: #FPGADev **Introduction** With technological advancements, medical imaging—one of the major achievements of modern science—has found diverse applications in non-invasive diagnosis and treatment. One such application is endoscopy, which became more widespread in the 1990s when charge-coupled devices made it possible to transmit images to displays. To assist doctors in better identifying and locating lesions, manufacturers have continuously improved endoscope resolution, progressing from 1080P to today’s 4K for human medical endoscopes. In addition, innovative technologies such as fluorescence and 3D imaging have been integrated to further aid physicians in accurate diagnosis and surgical procedures. Recently, China's Ministry of Industry and Information Technology released the *Medical Equipment Industry Development Plan (2021–2025)*, which outlines detailed strategic directions for key areas of medical equipment development, including the **strategic goal of breaking through in key technologi --- ## Xilinx Zynq UltraScale+ MPSoC Drone Controller - URL: https://intl.sienovo.cn/blog/137629025 - Date: 2024-04-11 - Tags: #UAV, #FPGADev ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137629025/01_bb33ec0c2318d50339c727aab4178c2d.jpeg) The official term is Unmanned Aerial Vehicle (UAV), which is a bit clunky, so we prefer to say drone. Over the past few decades, drone technology has made tremendous progress. We developed a flight and video controller for a drone for a client. **Client Challenge** The client required a hybrid FPGA/CPU hardware whose performance met the requirements, while being lightweight, compact, and energy-efficient. A passive cooling solution would be effective for this. Additionally, the hardware needed to operate reliably under harsh conditions (vibration and extreme temperatures). **Solution** The previous generation of successful drone controllers was built on Xilinx Zynq-7000. For this upgrade, our engineering team adopted the Xilinx Zynq UltraScale+ MPSoC, whose CPU handles position control and flight path tracking. Sensors and actuators are connected via FPGA logic; the nu --- ## RK3588 CPU+GPU+NPU Integrated AI Edge Controller for Engineering Vehicles/Rail Transit + Fatigue Driving Detection and Alert - URL: https://intl.sienovo.cn/blog/137480270 - Date: 2024-04-08 - Tags: #AI, #ARMDev, #DeepLearning The XMS-201 features a Rockchip RK3588 octa-core 64-bit processor, integrating an ARM Mali-G610 MP4 quad-core GPU and a built-in AI accelerator NPU, delivering 6 TOPS of AI computing power and supporting mainstream deep learning frameworks. The powerful RK3588 brings enhanced performance to various AI application scenarios, making it ideal for fields such as machine vision, edge computing, intelligent NVRs, and smart large screens. As an industry-leading chip, the RK3588 processor boasts powerful computing capabilities and efficient power consumption control. This processor adopts advanced process technology, ensuring its outstanding performance in complex computations and data processing. Whether it's image recognition, natural language processing, or big data analytics, the RK3588 can handle them with ease, providing strong impetus for AI applications. Our AI edge controller XMS-201 is precisely based on the powerful performance of the RK3588 processor, having undergone deep optim --- ## AI Smart Analysis Box for Construction Sites: Enhancing Management Efficiency and Safety - URL: https://intl.sienovo.cn/blog/137482081 - Date: 2024-04-07 - Tags: #AI The AI smart analysis box for construction sites is an AI-powered device based on artificial intelligence visual analysis technology, designed to enhance management efficiency in construction work areas and ensure the safety of personnel. Leveraging cutting-edge AI visual algorithms and big data, it can monitor real-time video streams from construction sites, standardizing the management of construction personnel's work attire and daily operational behavior. This minimizes issues caused by non-compliant personnel behavior and achieves digitized management of on-site safety production. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137482081/01_fa9bacfb57e88aa05783c7a110cad516.png) The AI analysis box for construction site video surveillance is primarily applied to areas covered by surveillance cameras, and it boasts multiple intelligent recognition functions. Firstly, the system can accurately identify whether construction personnel are wearing hard hats, ensuring head --- ## Intelligent Video Analytics Edge AI Box and Application Scenarios: Numerous Fields such as Communities, Campuses, Hotels, Shopping Malls, Restaurants, Hospitals, Ports, etc. - URL: https://intl.sienovo.cn/blog/137479717 - Date: 2024-04-07 - Tags: #AI, #AudioVideo, #BigData **Application Scenarios: Communities, Campuses, Hotels, Shopping Malls, Restaurants, Hospitals, Ports, and Many Other Fields** **I. Edge AI Box Product Introduction** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137479717/01_31b06eb50e1bd55fd4346fedd57cbcf6.png) 1. Based on a rich algorithm repository, algorithms can be flexibly configured for different scenarios and remotely updated and iterated in real-time. 2. Supports custom video channel algorithm execution plans. 3. Supports searching for alert event videos based on event name, time, and other criteria. 4. Supports unified storage and management of event-driven video data, saving space. 5. Supports intelligent video storage, intelligent processing, platform management, intelligent retrieval, alert management, and other functions. 6. Supports connecting to third-party cameras via ONVIF and RTSP protocols, and supports HDMI video output, etc. **II. Features** ![](https://pub-048dcb96257f476697b113fcb5939c --- ## How Industrial Test and Measurement Instruments Can Be Integrated with Artificial Intelligence (AI) - URL: https://intl.sienovo.cn/blog/137153427 - Date: 2024-03-29 - Tags: #AI The integration of industrial test and measurement instruments with artificial intelligence (AI) can be achieved through various approaches. Some of the primary methods include: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137153427/01_bcdbc8d77875d4e1fff7466867330c83.png) 1\. Data Analysis and Prediction Intelligent Data Analysis: AI algorithms can analyze data collected from sensors and test instruments to identify patterns, trends, and anomalies, thereby improving the accuracy and reliability of test results. Predictive Maintenance: By monitoring equipment performance and health status, AI can predict potential failures and enable proactive maintenance, reducing downtime and repair costs. 2\. Automation and Optimization Automatic Calibration and Adjustment: AI can automatically calibrate and adjust test instruments to ensure measurement accuracy and perform corrections when necessary. Parameter Optimization: AI-based optimization techniques can help fine-tune --- ## Ethernet/USB Data Acquisition Card 24-bit 16-channel LabVIEW 256K Synchronous Sampling - URL: https://intl.sienovo.cn/blog/137153076 - Date: 2024-03-29 - Tags: #labview XM7016 Ethernet/USB Data Acquisition Card XM7016 is an Ethernet/USB high-speed data acquisition card, featuring 16 true differential input channels, 24-bit resolution, and a maximum single-channel sampling rate of 256 ksps. It offers a total synchronous sampling rate of 4.096 Msps across 16 channels, precision pre-gain amplification, and integrated IEPE/ICP hardware support. This product utilizes multiple high-precision 24-bit ADC units combined with a pre-differential amplification module developed by our company over many years, giving it advantages such as high speed, high resolution, high accuracy, ultra-low noise, high common-mode rejection ratio, wide measurement range, and low temperature drift. It is suitable for various applications requiring precise high-speed data acquisition. The data acquisition card is available in a series of versions, including the USB model XM7016H. Highly customized services are supported. All components of the XM7016N data acquisition card are ind --- ## 全国产数据采集卡定制，24位八通道以太网数据采集卡 labview 100K采样 - URL: https://intl.sienovo.cn/blog/137152978 - Date: 2024-03-29 - Tags: #DAQCard --- Title: Fully Domestic 24-Bit 8-Channel Ethernet Data Acquisition Card with Customization Support, LabVIEW-Compatible 100K Sampling Content: The XM702 is a high-speed Ethernet-based data acquisition (DAQ) card featuring 8 true differential input channels, 24-bit resolution, a maximum single-channel sampling rate of 100 kSPS, and a total synchronous sampling rate of 800 kSPS across all eight channels. It integrates precision pre-amplification with built-in hardware support for IEPE/ICP sensors. This product employs multiple high-precision 24-bit ADC units combined with our company's proprietary front-end differential amplification module developed over years of experience, delivering high speed, high resolution, high accuracy, ultra-low noise, excellent common-mode rejection, wide measurement range, and low temperature drift. These characteristics make it ideal for precision, high-speed data acquisition in various demanding applications. The LAN communication uses the TCP/IP p --- ## Data Acquisition Cards: Reliable Products Require Robust EMC Countermeasures - URL: https://intl.sienovo.cn/blog/137147447 - Date: 2024-03-29 - Tags: #EMC **Brief Introduction to EMC** EMC (Electromagnetic Compatibility) is defined as "the ability of equipment and systems to function satisfactorily in their electromagnetic environment without introducing intolerable electromagnetic disturbances to anything in that environment." ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/137147447/01_6c857dc3339b6c64c6d55135bf882fbe.png) EMC encompasses two aspects: first, the device's ability to resist interference and operate normally (i.e., EMS); second, the requirement that electromagnetic emissions from the device do not affect the normal operation of other equipment (i.e., EMI). A good design must ensure: not being disturbed by others, and not disturbing others. **EMC Design** **1. Scope of EMC Design:** EMC design includes: **signal design, circuit design, shielding, grounding, filtering, and proper layout**. Among these, the aspects most closely related to mechanical structure are: **shielding, grounding, and proper layou --- ## 10 Reasons to Choose Custom Software Development with LabVIEW - URL: https://intl.sienovo.cn/blog/137147308 - Date: 2024-03-29 - Tags: #labview 1. Enhance Processing Power and Flexibility Through Software One of the greatest advantages of using computer-based data acquisition systems is the ability to use software to customize your test system’s functionality and visualization features to meet your specific application needs. Manual testing is expensive, slow, and error-prone, whereas software-defined systems can execute tasks faster and with consistent accuracy. LabVIEW provides a unified programming interface for data acquisition devices, enabling seamless integration between hardware and software. You can automate measurements across multiple devices, analyze acquired data in parallel, and create custom reports within minutes using LabVIEW. 2. Accelerate Your Productivity LabVIEW increases productivity by allowing you to focus on data and data processing, eliminating many of the administrative complexities of traditional programming such as memory allocation and language syntax. Built-in, specialized engineering softw --- ## Full-Featured Multi-CAN and Multi-Serial Port Robot Board Based on RK3588 - URL: https://intl.sienovo.cn/blog/137084532 - Date: 2024-03-27 - Tags: #RK3588, #AI, #AIBox The RK3588 robot controller offers five major technical advantages: 1. Integrated with a variety of powerful embedded hardware engines, supporting 8K@60fps H.265 and VP9 decoders, 8K@30fps H.264 decoder, and 4K@60fps AV1 decoder; supporting 8K30fps H.264 and H.265 encoders, high-quality JPEG encoder/decoder, and dedicated image pre-processors and post-processors. 2. Built-in 3D GPU compatible with OpenGL ES1.1/2.0/3.2, OpenCL 2.2, and Vulkan 1.2. A dedicated 2D hardware engine with MMU maximizes display performance and delivers a smooth user experience. 3. Integrated Rockchip self-developed 48MP ISP (Image Signal Processor), supporting a wide range of algorithm accelerators such as HDR, 3A, LSC, 3DNR, 2DNR, sharpening, defogging, fisheye correction, gamma correction, and more. 4. High-performance NPU supporting INT4/INT8/INT16/FP16 mixed computing. Its strong compatibility enables seamless conversion of network models based on frameworks such as TensorFlow, MXNet, PyTorch, and Caf --- ## Phytium + FPGA + AI Smart Data Acquisition and Analysis Network Appliance Solution for the Power Industry - URL: https://intl.sienovo.cn/blog/136901335 - Date: 2024-03-21 - Tags: #PhytiumCPU ### Industry Pain Points: The specific role of a secure IoT network appliance (data diode) in a monitoring platform: 35kV substations are the power core of coal mines, supplying electricity to critical equipment such as personnel hoisting systems, coal conveyance, and mine ventilation. It is crucial for the monitoring center to have real-time visibility into the substation's operational status to ensure safe mining operations. If external entities could remotely control the substation via the monitoring network, it would lead to severe consequences. The network appliance resolves this dilemma by enabling the central control room to monitor substation operations in real time while physically blocking any external control signals—ensuring one-way data flow and thus guaranteeing security. In the Baoyushan Mine Integrated Automation Monitoring Platform project, operational data from the 35kV substation needed to be collected and displayed centrally in the control room. Howeve --- ## Fully Domestic FeiTeng + FPGA Architecture with B-Code Support, 12 Ethernet Ports, and Multi-Serial Power Communication Management Solution - URL: https://intl.sienovo.cn/blog/136896954 - Date: 2024-03-21 - Tags: #FPGADev, #Architecture, #PowerCommunicationGateway, #FullyDomestic ### Industry Pain Points:        China's power grid has become the most extensive and structurally complex man-made technological system in the world today. With the introduction of a series of laws and regulations by national ministries and commissions—such as the *Cybersecurity Law of the People's Republic of China*, the *Guidelines for Information Security Protection of Industrial Control Systems* issued by the Ministry of Industry and Information Technology, Order No. 14 from the National Development and Reform Commission titled *Regulations on Security Protection for Power Monitoring Systems*, and the *Notice on Issuing Overall Security Protection Schemes and Evaluation Standards for Power Monitoring Systems* issued by the National Energy Administration—the importance of cybersecurity protection in the power industry has been significantly emphasized. Driven by the urgent need for domestic substitution of IT infrastructure in the power sector, as well as the proposal and impleme --- ## Phytium D2000 + Fudan Micro ARM+FPGA + Pre-installed Kylin Fully Domestic COMe Module - URL: https://intl.sienovo.cn/blog/136870755 - Date: 2024-03-20 - Tags: #Phytium, #Kylin, #FMSH Product Overview The COMe-D2000 core module complies with the PICMG COM Express® Type-6 Rev2.1 standard and adheres to the COMe Basic form factor. It features a ruggedized design with onboard-mounted memory and SSD storage, enhancing reliability while maintaining a compact footprint. The COMe-D2000 integrates the domestically produced Phytium D2000 octa-core processor, which includes eight 64-bit high-performance cores clocked up to 2.3GHz. It comes with 16GB of onboard domestic DDR4 memory, 64GB of domestic SSD storage, an integrated high-performance GPU, and provides rich peripheral interfaces.  ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136870755/01_90fa1736c3c6971ed3d5dc183ae7a704.png) The COMe-D2000 is a fully domestic, high-performance, high-density, low-power, and highly reliable COMe computer module. It supports multiple mainstream operating systems and is widely applicable in defense, government, scientific research, telecommunications, and other fields. --- ## Intelligent Data Acquisition and Analysis Solution Based on RK3588 + FPGA + AD + AI - URL: https://intl.sienovo.cn/blog/136834215 - Date: 2024-03-19 - Tags: #FPGADev, #AI RK3588 is Rockchip's latest flagship high-end processor, featuring high computing power, low power consumption, powerful multimedia capabilities, and rich data interfaces. It integrates an octa-core CPU (quad-core A76 + quad-core A55), an ARM G610MP4 GPU, and an NPU with built-in 6.0 TOPs computing capacity. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136834215/01_4c47a8cdd4b782b1a6268160ff76428c.png) [RK3588 + Fudan Micro FPGA Solution](https://www.bilibili.com/video/BV1Q6421u7mj/ "RK3588 + Fudan Micro FPGA Solution") ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136834215/02_55c3eb38813b970bd021af4d0e00f722.png) Five Key Technical Advantages: 1. Integrated with multiple powerful embedded hardware engines, supporting 8K@60fps H.265 and VP9 decoders, 8K@30fps H.264 decoder, and 4K@60fps AV1 decoder; also supports 8K30fps H.264 and H.265 encoders, high-quality JPEG encoder/decoder, dedicated image pre-processors and post-processors. 2. Built-in 3D G --- ## 基于RK3588的高性价比智能边缘分析一体机 - URL: https://intl.sienovo.cn/blog/136831776 - Date: 2024-03-19 - Tags: #AI, #AIBox, #RK3588 --- Title: Cost-Effective Intelligent Edge Analytics All-in-One Device Based on RK3588 Content: 1. 1. Product Overview The INT-AIBOX-RK4 intelligent edge analytics all-in-one device is a high-performance, low-power edge computing solution. Powered by the domestic TPU chip RK3588, it features an integrated 6 TOPS NPU for AI computing and supports up to 8K video encoding and decoding. This product integrates high-precision AI intelligent algorithms based on computer vision and deep learning networks, along with a comprehensive video intelligence management platform. The AI algorithms support various application scenarios such as industrial parks, residential communities, construction sites, and campuses, and can be flexibly combined and configured according to specific needs. The video intelligence management platform enables front-end device management, real-time video preview, alarm notifications, evidence capture, online algorithm loading and optimization, and data visualization --- ## Raspberry Pi CODESYS PLC Controller Solution with License and Real-Time System - URL: https://intl.sienovo.cn/blog/136631299 - Date: 2024-03-11 - Tags: #codesys, #RaspberryPi We offer genuine CODESYS licenses and real-time system integration services. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136631299/01_0771dbdec5b8bb405a7c0a19b02b9516.png) Building a CODESYS PLC Controller Using Raspberry Pi Implementing a Controller on Raspberry Pi 1. Install the CODESYS Programming Environment 1.1 Download CODESYS 1.2 Install the CODESYS Development Environment 1.3 Run the CODESYS Development Environment 2. Run the CODESYS Development Environment 2.1 Create a Project 2.2 Edit the Program 2.3 Compile the Program 2.4 Download the Program 3. Execution Results 3.1 Interfaces 3.2 Visualization 3.3 Supported Fieldbuses 4. Next Steps Implementing a Controller on Raspberry Pi Most people are familiar with the Raspberry Pi, a compact computer that can be accessed via SSH for remote editing. If connected to an HDMI display with a USB mouse and keyboard, it functions just like a regular computer. It even supports LibreOffic --- ## Soft PLC Solution on an ARM+LINUX Real-Time Hardware Platform Based on RK3588 + Codesys + Xenomai - URL: https://intl.sienovo.cn/blog/136631170 - Date: 2024-03-11 - Tags: #AI, #codesys, #SoftPLC 1. ******Product Overview****** The company launches an AI edge computing motherboard based on the Rockchip RK3588 architecture. The RK3588 is a new generation of high-end domestic 64-bit octa-core processor manufactured using 8nm process technology, featuring high computing power, low power consumption, superior multimedia capabilities, and rich data interfaces. It integrates an octa-core CPU consisting of quad-core A76 and quad-core A55 clusters, along with an ARM G610MP4 GPU. The chip includes an embedded neural processing unit (NPU) delivering up to 6 TOPs of computing power, and supports integration of the Hailo AI accelerator chip, which provides 26 TOPs per chip, enabling total system computing power to be expanded up to 32 TOPs. It supports 8K@60fps video decoding and 8K@30fps encoding, with abundant peripheral interfaces and exceptional expandability. The RK3588's built-in NPU supports up to 6.0 TOPs and interfaces such as PCI-e/USB3.0/RGMII, enabling structured recognition --- ## Customized IRIG-B Time Synchronization Solution Based on AM62X + FPGA/MCU - URL: https://intl.sienovo.cn/blog/136523605 - Date: 2024-03-07 - Tags: #FPGADev, #IRIGB ### What is IRIG-B Time Synchronization? IRIG-B (Inter-Range Instrumentation Group-B) code is a time synchronization standard commonly used for precise time measurement and data synchronization, widely applied in power systems, telecommunications, aerospace, and other fields. The IRIG-B code transmits one frame per second, with each frame consisting of 100 code elements at a frequency of 1 kHz—meaning each code element occupies 10 ms. The basic code elements in IRIG-B are "0", "1", and "P". The pulse widths for "0" and "1" are 2 ms and 5 ms respectively, while the "P" element is a position marker with a pulse width of 8 ms. The diagram below illustrates the basic code elements of IRIG-B. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136523605/01_b47ccf0bab897bee6535bff7025f737.png) **Figure 1** The following figure shows the pulse sequence structure of one IRIG-B frame. Two consecutive "P" code elements indicate the start of a new second, with the leading edge --- ## Intel x86-based Rail Transit / Indian Metro Automatic Fare Collection (AFC) System - URL: https://intl.sienovo.cn/blog/136463908 - Date: 2024-03-04 - Tags: #Networking **India - Mumbai Metro Line 3** Currently, India's Mumbai Metro Line 3 is under full construction. This 33.5-kilometer-long line will be Mumbai's first underground metro line, featuring 27 underground stations and 1 ground-level station. Its successful completion will connect other metro lines, monorail, suburban railways, intercity railways, and Mumbai Airport, among others, significantly reducing traffic congestion on Mumbai's urban roads and alleviating the overload on other lines. Traditional manual ticketing cannot meet today's massive and efficient travel demands, therefore, the need for Automatic Fare Collection (AFC) systems is particularly urgent and important. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136463908/01_4f462408658e29270a2eafa9b3314579.jpeg) **Automatic Fare Collection (AFC) System** The Automatic Fare Collection (AFC) system primarily consists of two major parts: the application management system (clearing center system, central computer --- ## Intel-Based & Domesticated Dedicated Controller for Unmanned Forklifts & Machine Vision - URL: https://intl.sienovo.cn/blog/136463814 - Date: 2024-03-04 - Tags: #Robotics Unmanned forklifts and machine vision are two distinct technological domains, yet they can be integrated to achieve more efficient logistics automation. Unmanned forklifts are automated transport vehicles capable of moving and transporting goods without human intervention. Machine vision, an artificial intelligence technology, enables computers to recognize and interpret content within images or videos. In logistics automation, machine vision assists unmanned forklifts in identifying cargo, obstacles, and surroundings, thereby enabling better path planning and collision avoidance. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136463814/01_b613c701ba821f1fcdf68b83916a8dc4.png) A dedicated controller for unmanned forklifts and machine vision acts as the central nervous system, playing a decisive role in this process. A high-performance, stable controller skillfully coordinates the movement of unmanned forklifts while ensuring accurate and error-free execution of comma --- ## Intel/ARM/Domestic EMS Energy Storage Controller Solutions - URL: https://intl.sienovo.cn/blog/136463703 - Date: 2024-03-04 - Tags: #EnergyStorageController New energy storage is a critical equipment foundation and key supporting technology for building a new power system and advancing the green, low-carbon transformation of energy. It plays a vital role in achieving carbon peak and carbon neutrality goals. When it comes to energy storage, the public often first thinks of batteries, whose performance directly affects energy conversion efficiency, system lifespan, and safety. However, for energy storage to function effectively as a complete system, the EMS (Energy Management System)—the "brain" of the system—is equally important. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136463703/01_36264b1d8a055874b02aaf8799180f48.jpeg) In 2024, there will be a strong push to launch new products in industries such as new energy and smart healthcare, focusing on user-centric design and real-world application scenarios to drive product innovation through use cases. Yesterday morning, the first major product launch of 2024 was success --- ## Rail Transit and Power Solutions with Fully Domestic Phytium E2000Q and Fudan Micro FPGA - URL: https://intl.sienovo.cn/blog/136345570 - Date: 2024-02-28 - Tags: #FPGADev, #Phytium, #DomesticReplacement 1. ****Product Overview**** ITX-XMF201 is a high-performance edge computing gateway motherboard featuring the domestically produced quad-core Phytium E2000Q processor, achieving a localization rate of 95%. The board integrates 2 Ethernet ports, 2 CAN interfaces, 6 RS232 serial ports, 1 RS485 serial port, and 16 GPIO channels, meeting IoT gateway requirements for industries such as banking, rail transit, and power systems. 1. ****Product Images**** 1. ****Product Features**** 1. Onboard domestic quad-core Phytium E2000Q processor; 2. One SO-DIMM slot supporting 16GB, 8GB, or 4GB, up to 16GB maximum memory; 3. Onboard 2 Ethernet ports, 2 CAN interfaces, 16 GPIO channels, 6 RS232 ports, and 1 RS485 port; 4. Supports operating systems including Kylin V10, UOS, and LINUX. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136345570/01_3ad34e4df60c26adfd7e73724e830cf2.png) 1. ****Specifications**** ****Form Factor**** MINI-ITX, 170mm × 170mm ****CPU**** Phytium E20 --- ## VPX Computing Blade Based on Domestic Phytium FT-2000+/64-Core and Fudan Microelectronics FPGA - URL: https://intl.sienovo.cn/blog/136345368 - Date: 2024-02-28 - Tags: #FPGADev, #DAQCard, #VPX, #FullyDomestic 6U VPX Computing Board ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136345368/01_93ac7d9968c79f3caad375cbfd6e5198.png) **Product Overview** **Product Features** ¾ Phytium computing platform with 100% domestic localization The VPX-MPU6902 is a computing blade based on the Phytium FT-2000+/64-core processor, operating at a main frequency of 2.2 GHz, responsible for managing and scheduling service data flows. Paired with the Phytium X100 chip featuring an integrated independent graphics unit, it is suitable for various terminal and server application scenarios, meeting high-performance computing requirements in industries such as banking, telecommunications, rail transit, and power. 1. Onboard Phytium FT-2000+/64-core high-performance processor; 2. Onboard Phytium X100 chip with integrated independent graphics; 3. Single-blade double-precision floating-point processing capability ≥192 GFlops or single-precision floating-point processing capability ≥384 GFlops; 4. 32 --- ## 6U VPX Domestically Produced Phytium D2000/8-Core + Fudan Micro FPGA Information Processing Motherboard - URL: https://intl.sienovo.cn/blog/136345147 - Date: 2024-02-28 - Tags: #FPGADev, #DAQCard ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136345147/01_c92f751ae53a9cb278f08444c673c7cc.png) ****Product Features**** ****Product Functions**** ¾ Phytium computing platform with 100% domestic localization The VPX-MPU6503 is a high-performance information processing motherboard based on the Phytium D2000 octa-core processor. It integrates a high-performance computing module consisting of the Phytium D2000 processor and Phytium X100 bridge chip, featuring onboard dual-channel 32GB DDR4 memory and a 128GB solid-state SSD. An expansion interface for additional SSD storage is reserved to support increased disk capacity. This motherboard is primarily designed for applications requiring high-speed, intensive data processing and display control. ****Category**** ****Feature Description**** ****Form Factor**** 233.35mm × 160mm × 1.6mm ****Processor**** Phytium D2000, 8-core, 2.3GHz clock speed, TDP = 40W ****Chipset**** Phytium X100 ****Memory**** Onboard dual- --- ## Design of a ZYNQ-Based PCIe High-Speed Data Acquisition Card (5): Host Software Design - URL: https://intl.sienovo.cn/blog/136284648 - Date: 2024-02-25 - Tags: #DAQCard, #HostComputer **4.4 Host Software Design** The host software is primarily responsible for receiving data and saving it to files. Since the acquisition card is a PCIe device, its development must be based on a PCIe device driver. In this design, the WinDriver development tool is selected to generate the PCIe device driver and function library. Based on this driver, the overall functionality of the host software is developed within the Visual Studio (VS) environment. This section first introduces WinDriver, then explains the driver generation process, followed by the development of various functions in the VS environment using the generated driver. Finally, the host software interface is presented and described. **4.4.1 WinDriver Introduction and Driver Generation** WinDriver uses low-level drivers for device development. The core driver that communicates with hardware is *windrvr.sys*. Developers only need to call functions from the WinDriver-provided library within their application to implement --- ## Design of a ZYNQ-based PCIe High-Speed Data Acquisition Card (Part 4) Software Design, Aurora Protocol Logic Design - URL: https://intl.sienovo.cn/blog/136284561 - Date: 2024-02-25 - Tags: #FPGADev System Software Design **4.1 Introduction** This chapter performs system software design based on the analysis conclusions from Chapter 2. Software design includes logic design, embedded software design, and host computer software design. In logic design, the ADC module, Aurora module, DDR3 SDRAM module, and PCIe module are analyzed and designed. The logic code for each module is written based on the IP cores provided by Vivado software, and data connection issues between modules are resolved. Embedded design involves porting the system and kernel, and realizing system startup on Zynq's PS core. In host computer design, driver development tools are first introduced, followed by an overview of the host computer's overall design. **4.2 Logic Software Design** Since the FMC interface data of the carrier card is related to the type of daughter card connected, either the ADC module or the Aurora module is selected based on the type of daughter card connected. When an AD daughter card i --- ## Design of a High-Speed PCIe Data Acquisition Card Based on ZYNQ (3) Hardware Design - URL: https://intl.sienovo.cn/blog/136284469 - Date: 2024-02-25 - Tags: #FPGADev Acquisition Card Hardware Design **3.1 Introduction** Hardware design of the acquisition card is the foundation for realizing data acquisition functions. A well-designed hardware platform facilitates easier implementation of acquisition functionality and simplifies software development. This chapter provides a detailed description of the hardware design of the acquisition card based on the hardware architecture outlined in Chapter 2, including component selection, configuration, and specific circuit designs for both the carrier card and daughter cards. The overall hardware block diagram of the carrier and daughter cards is shown in Figure 3.1. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/136284469/01_040ba6a0f1d1b7b4a79af1a31b1f999d.png) **3.2 Carrier Card Hardware Design** **3.2.1 Main Control Chip Selection and Configuration Circuit** **(1) Main Control Chip Selection and Analysis** Based on the hardware design analysis presented in Chapter 2, the control chip --- ## Design of a ZYNQ-Based PCIe High-Speed Data Acquisition Card (2): System Architecture and Host Software - URL: https://intl.sienovo.cn/blog/136284355 - Date: 2024-02-25 - Tags: #FPGADev Overall Design of the Acquisition Card and Related Technologies **2.1 Introduction** This project originates from a radar emitter identification system, requiring the acquisition, transmission, and storage of intermediate frequency (IF) signals from radar emitters. Based on project requirements, this chapter presents the overall design scheme of the data acquisition card. The design encompasses both hardware and software components. First, the performance specifications of the acquisition card are analyzed. Then, the overall hardware architecture is proposed, followed by the software architecture built upon the hardware design. Finally, relevant protocols and key technologies used in the system are explained. **2.2 Overall Design Overview** **2.2.1 Analysis of System Specifications** In this project, the IF signal bandwidth of the radar emitter ranges from 760 MHz to 1060 MHz. This radar signal is a bandpass signal. Applying the bandpass sampling theorem allows for a reduced samp --- ## Design of a High-Speed PCIe Data Acquisition Card Based on ZYNQ (Part 1) - URL: https://intl.sienovo.cn/blog/136284314 - Date: 2024-02-25 - Tags: #FPGADev As the first step in information processing, data acquisition is becoming increasingly important. Currently, data acquisition has been widely applied in aerospace, civilian, military, and medical fields. With continuous advancements in related technologies, signal frequencies are rising and bandwidths are expanding, driving data acquisition technology toward high-speed, large-volume data processing. In electronic warfare applications, the emergence of various complex wideband radar systems has made electromagnetic signals in space more complicated. To identify specific signals within such complex electromagnetic environments, high-speed ADCs are first required to sample the electromagnetic signals, followed by high-speed data transmission to a processor for further processing and analysis, thereby extracting information embedded in the signals. Typically, high-speed data acquisition cards perform the tasks of signal acquisition and transmission, while data processing can either be com --- ## Joint Solution for Domestic Computing Module Based on Phytium ARM + FPGA - URL: https://intl.sienovo.cn/blog/136141844 - Date: 2024-02-17 - Tags: #Networking **Overview of the Joint Solution** With the increasing demand for independent innovation in electronic information systems for specialized fields, continuous development and upgrading of domestically produced computing systems and modules capable of withstanding harsh environments are required. Independent innovation in electronic information systems for specialized fields refers to achieving full control over the research, design, production, upgrade, and maintenance of information systems—from hardware to software—using proprietary technologies and security mechanisms. Among these efforts, the independent development of computing modules for harsh environments is a critical component. The self-reliant development of such modules requires not only indigenous processor subsystems but also comprehensive domestication of peripheral interfaces and functional units. For specialized application scenarios, highly integrated designs are necessary, supporting multiple service forms. **Solut --- ## Domestic Phytium ARM+FPGA Power Industry DCS Joint Solution - URL: https://intl.sienovo.cn/blog/136002394 - Date: 2024-02-02 - Tags: #FPGADev **Overview of the Joint Solution** In the development of thermal power generation, as societal demand for electrical resources continues to rise, the previous coarse power generation methods are no longer viable. More refined generation is required to maximize resource utilization. Such control must be achieved through automation technology, as manual operations alone cannot meet these requirements. As a critical component of national infrastructure, the power system can enhance generation efficiency and safety by adopting domestically produced control systems. Developing an innovative, domestically sourced distributed control system (DCS) based on Phytium CPUs reduces reliance on foreign CPUs, enhances the level of indigenous innovation in core control equipment, mitigates technological risks arising from international fluctuations, and promotes the healthy development of the ecosystem surrounding domestic CPU technologies and products. The DCS based on Phytium CPUs applied in this --- ## Intel Atom + Kintex-7 70T FPGA, 8-Slot CompactRIO Controller - URL: https://intl.sienovo.cn/blog/135767292 - Date: 2024-01-23 - Tags: #FPGADev, #NIAlternative, #DAQCard The NI cRIO-9047 is a rugged embedded controller built around an Intel Atom quad-core processor and a Xilinx Kintex-7 70T FPGA, targeting industrial test, measurement, and control applications that demand real-time determinism, extended temperature operation, and tight hardware-software integration. This post walks through the hardware architecture, connectivity options, and key use cases for the cRIO-9047, with notes on where the FPGA and TSN capabilities provide the most leverage. ## Hardware Architecture Overview At its core, the cRIO-9047 pairs two distinct processing layers that operate concurrently: **Real-Time Processor — Intel Atom Quad-Core at 1.60 GHz** The host processor runs NI Linux Real-Time OS and handles high-level application logic, communication stacks, and data management. With 4 GB of DRAM and 4 GB of onboard storage, it can sustain logging-intensive workloads without relying on an external PC. The Intel Atom family is well-suited here: it delivers x86 compatibil --- ## Alternative to Imported Controllers: Intel Atom + Kintex-7 70T FPGA, 4-Slot CompactRIO Controller - URL: https://intl.sienovo.cn/blog/135767088 - Date: 2024-01-23 - Tags: #FPGADev, #NIAlternative When high-stakes industrial applications demand real-time determinism, synchronized multi-node communication, and FPGA-level flexibility in a ruggedized package, NI's cRIO-9040 stands out as a compelling alternative to imported proprietary controllers. This post walks through the key hardware architecture and connectivity features of the cRIO-9040, explaining why its combination of Intel Atom processing, Kintex-7 FPGA fabric, and Time-Sensitive Networking makes it a practical choice for distributed measurement, embedded control, and coprocessing applications. ## Hardware Architecture Overview The cRIO-9040 is a 4-slot CompactRIO chassis-and-controller combo built around a **1.30 GHz dual-core Intel Atom** processor paired with **2 GB of DRAM** and **4 GB of onboard storage**. The Intel Atom platform brings x86-64 compatibility with a low thermal envelope — important in sealed industrial enclosures where active cooling may be limited or undesirable. On the programmable logic side, th --- ## Imported Controller Alternative: NI 8-slot CompactRIO Controller Based on Zynq-7020 FPGA - URL: https://intl.sienovo.cn/blog/135766429 - Date: 2024-01-23 - Tags: #FPGADev, #NIAlternative, #DAQCard The cRIO-9068 is a serious piece of industrial hardware, and for engineering teams looking to move away from fully proprietary Western automation platforms without sacrificing real-time determinism or FPGA flexibility, it deserves a careful look. This post breaks down the controller's architecture, connectivity, and the design philosophy behind combining a hardened real-time processor with reconfigurable FPGA logic on a single module. ## What Is CompactRIO and Why Does It Matter National Instruments' CompactRIO (cRIO) platform is a modular, rugged measurement and control architecture widely used in industrial automation, aerospace testing, and machine condition monitoring. The chassis accepts I/O modules — analog input, digital output, CAN, serial, and more — that communicate directly with an on-board FPGA. This lets engineers implement deterministic, microsecond-level signal processing in hardware while offloading higher-level logic to the embedded real-time processor. The result is --- ## Domestic Replacement for Imported Controllers: Intel Atom + Artix-7 75T FPGA, CompactRIO Single-Board Controller - URL: https://intl.sienovo.cn/blog/135765860 - Date: 2024-01-23 - Tags: #FPGADev The NI sbRIO-9603 is a compact, high-integration single-board controller from National Instruments' CompactRIO family, designed to bring real-time processing and reconfigurable FPGA logic onto a single PCB for demanding OEM applications. This post examines the hardware architecture, key I/O capabilities, and why this platform—and its domestic-market equivalents—has become a reference point for engineers evaluating embedded industrial controllers that balance processing power with deterministic hardware control. ## What Is the sbRIO-9603? The sbRIO-9603 belongs to NI's Single-Board RIO (sbRIO) product line, which is aimed at volume OEM deployments where integrating a full CompactRIO chassis is impractical. Unlike a standard cRIO system that separates the controller and chassis, an sbRIO consolidates the real-time processor, FPGA fabric, and digital I/O onto one board—reducing BOM complexity, board-to-board latency, and physical footprint. The processor at the heart of the sbRIO-9603 --- ## Intel Atom + Artix-7 100T FPGA, CompactRIO Single-Board Controller - URL: https://intl.sienovo.cn/blog/135763955 - Date: 2024-01-23 - Tags: #FPGADev, #NIAlternative, #DAQCard ## Intel Atom + Artix-7 100T FPGA: Inside the NI sbRIO-9628 CompactRIO Single-Board Controller For engineers who need deterministic real-time control combined with the flexibility of user-programmable logic in a single compact form factor, National Instruments' CompactRIO single-board RIO (sbRIO) platform has long been a go-to solution. The **sbRIO-9628** sits at the capable end of that lineup, pairing an Intel Atom dual-core processor with a Xilinx Artix-7 100T FPGA — a combination that makes it well-suited for demanding industrial automation, embedded DAQ, and hardware-in-the-loop (HIL) test applications where both processing throughput and I/O timing precision matter. ## Architecture: Real-Time Processor Meets User-Programmable FPGA The sbRIO-9628 runs **NI Linux Real-Time**, NI's hardened Linux-based RTOS that provides deterministic execution for time-critical control loops while still giving developers access to familiar Linux tooling and networking stacks. Atop this sits the d --- ## ZYNQ-7020 Integrates Real-Time Processor Running NI Linux Real-Time, Supports FPGA Secondary Development - URL: https://intl.sienovo.cn/blog/135763468 - Date: 2024-01-23 - Tags: #FPGADev The NI sbRIO-9637 is a CompactRIO Single-Board Controller that brings together a real-time processor, a user-reconfigurable Xilinx Zynq-7020 FPGA, and a full complement of analog and digital I/O onto a single printed circuit board. Designed for engineers who need deterministic control, signal acquisition, and custom FPGA logic in a compact, embeddable package, the sbRIO-9637 is particularly well suited for high-volume OEM deployments where board-level integration is a hard requirement. ## Processor and Memory Architecture At the heart of the sbRIO-9637 is the Xilinx Zynq-7020 SoC — a tightly coupled heterogeneous device that pairs a dual-core ARM Cortex-A9 processing system (PS) running at 667 MHz with a Artix-7-class programmable logic (PL) fabric. This architecture is what allows NI to run a full real-time operating system on the PS side while simultaneously offloading time-critical or parallel tasks to the FPGA fabric on the PL side, all within a single chip and without the latenc --- ## Germany SYS TEC Core Module PLCcore-iMX35 CODESYS - URL: https://intl.sienovo.cn/blog/135697047 - Date: 2024-01-19 - Tags: #codesys, #SoM, #AM335X ### Germany SYS TEC Core Module PLCcore-iMX35 CODESYS The PLCcore-iMX35 CODESYS is a powerful Soft-PLC that can be used as a baseboard for your own HMI devices. The PLCRuntime System is CODESYS V3, it minimizes the required peripheral connectivity, which simplifies the design of application-specific baseboards. Due to various local inputs and outputs and onboard supported communication interfaces, the PLCcore-iMX35 can connect to its peripheral environment in a common way via multiple network interfaces. Additional application areas include the ability to execute independent Linux applications in parallel with the PLC runtime system. Enabling the PLC to be used as a plug-and-play core module with a small form factor can \*\*\*significantly reduce the time and cost of user-specific control development. The PLCcore-iMX35 CODESYS is also particularly suitable for use as a base component for customized HMI devices and as an intelligent network node for decentralized processing of proces --- ## [NI Domestic Alternative] NI-9231, 8-Channel, 51.2 kS/s/ch, -5 to 5 V, C Series Sound and Vibration Input Module - URL: https://intl.sienovo.cn/blog/135625771 - Date: 2024-01-16 - Tags: #NIAlternative, #DAQCard, #NI-9231 ## Overview The NI-9231 is an 8-channel C Series sound and vibration input module designed for high-fidelity dynamic signal acquisition. It targets engineers working on noise, vibration, and harshness (NVH) testing, rotating machinery analysis, and structural health monitoring — applications where both measurement accuracy and sensor flexibility are critical. This post unpacks the module's key specifications and explains why each feature matters in a real industrial measurement context, and frames what to look for in a domestic Chinese-market equivalent. ## Key Specifications at a Glance | Parameter | Value | |---|---| | Channels | 8 simultaneous | | Sample rate | 51.2 kS/s per channel | | Input range | −5 V to +5 V | | IEPE excitation | 2 mA (switchable) | | TEDS support | Yes (IEEE 1451.4) | | Form factor | NI C Series | The 51.2 kS/s per-channel rate is not arbitrary. At that rate, the usable bandwidth reaches roughly 20 kHz — exactly the upper limit of human hearing and a commo --- ## [NI Domestic Alternative] NI‑9232, 3-Channel, 102.4 kS/s/ch, ±30 V, C Series Sound and Vibration Input Module - URL: https://intl.sienovo.cn/blog/135620982 - Date: 2024-01-16 - Tags: #NIAlternative, #DAQCard, #NI‑9232 The NI-9232 is a C Series sound and vibration input module designed for high-fidelity dynamic signal acquisition in industrial condition monitoring and structural analysis applications. This post covers the module's core capabilities, explains how its hardware features translate to real-world measurement tasks, and discusses what to look for when evaluating domestic NI alternatives for this class of measurement hardware. ## What the NI-9232 Does The NI-9232 provides three channels of simultaneous analog input, each capable of sampling at up to 102.4 kS/s. The ±30 V input range is unusually wide for a vibration front-end — most IEPE-oriented modules target ±5 V or ±10 V — which gives this module headroom to accommodate both low-level piezoelectric accelerometer outputs and higher-voltage signals from proximity probes or tachometers without external attenuation. All three channels acquire synchronously, meaning their samples are time-aligned at the hardware level. This is a critical r --- ## 【NI Domestic Alternative】NI‑9234, 4-Channel, 51.2 kS/s/ch, ±5 V, C Series Sound and Vibration Input Module - URL: https://intl.sienovo.cn/blog/135620905 - Date: 2024-01-16 - Tags: #DAQCard, #NIAlternative, #NI‑9234 ## Overview: The NI‑9234 and Its Role in Industrial Vibration Measurement The NI‑9234 is a 4-channel, C Series sound and vibration input module rated for 51.2 kS/s per channel with a ±5 V input range. It is purpose-built for acquiring data from piezoelectric sensors commonly used in rotating machinery diagnostics, structural health monitoring, and acoustic testing. As demand for domestic (Chinese-manufactured) alternatives to National Instruments hardware grows in industrial automation and research settings, understanding the full capability set of the NI‑9234 is essential for identifying a functionally equivalent replacement. ## Supported Sensor Types The NI‑9234 is designed to interface with two broad categories of sensors: **IEPE (Integrated Electronic Piezoelectric) sensors** — These are the most common type of vibration sensor in industrial use. An IEPE accelerometer embeds a charge amplifier directly inside the sensor housing, requiring the DAQ module to supply a constant-cur --- ## [NI Alternative] NI‑9218, 51.2 kS/s/ch, 2-Channel C Series Universal Analog Input Module - URL: https://intl.sienovo.cn/blog/135620512 - Date: 2024-01-16 - Tags: #DAQCard, #NIAlternative, #NI‑9218 The NI-9218 is a two-channel, 51.2 kS/s/ch C Series universal analog input module designed for engineers who need one hardware platform to cover a wide range of sensor types without swapping modules between test campaigns. This post breaks down what makes the NI-9218 distinctive, how its adapter-based architecture works, and why it shows up so frequently in automotive, off-highway, and portable data-logging applications — along with what to look for if you are evaluating drop-in alternatives. ## What Is the C Series Platform? C Series modules slot into National Instruments CompactDAQ (cDAQ) chassis and CompactRIO (cRIO) controllers. The chassis handles timing, synchronization, and USB/Ethernet/Wi-Fi connectivity to a host PC, while each C Series module provides a specific analog or digital I/O function. Because every module shares the same mechanical form factor and backplane interface, a single chassis can mix signal-conditioning types — strain gauges in slot 1, thermocouples in slo --- ## [NI Domestic Alternative] sbRIO‑9234, Non-enclosed, 4-Channel, 51.2 kS/s/ch, ±5 V, C Series Sound and Vibration Input Module - URL: https://intl.sienovo.cn/blog/135620413 - Date: 2024-01-16 - Tags: #DAQCard, #NIAlternative The sbRIO-9234 is a C Series sound and vibration input module from National Instruments (NI) aimed at engineers who need high-fidelity dynamic signal acquisition in embedded or OEM environments. This post covers the module's core capabilities, its signal conditioning architecture, and what makes it suitable as a reference point when evaluating domestic (non-NI) alternatives for industrial vibration and acoustic measurement applications. ## What the sbRIO-9234 Does At its core, the sbRIO-9234 is a 4-channel simultaneous-sampling module rated at 51.2 kS/s per channel with an input range of ±5 V. The 51.2 kS/s rate is not arbitrary — it is a standard in audio and vibration metrology because it provides a Nyquist ceiling of 25.6 kHz, neatly covering the full 20 Hz–20 kHz audible band and capturing most structural resonance modes of interest in rotating machinery diagnostics. The module accepts signals from two broad sensor families: - **IEPE (Integrated Electronic Piezoelectric) sensor --- ## 【NI Domestic Alternative】PXIe‑4499, 204.8 kS/s, 114 dB, Four Gain Ranges, AC/DC Coupling, 16-Input PXI Sound and Vibration Module - URL: https://intl.sienovo.cn/blog/135620311 - Date: 2024-01-16 - Tags: #NIAlternative, #DAQCard The PXIe-4499 is a high-channel-count PXI sound and vibration acquisition module from National Instruments, long regarded as a reference-class instrument for demanding acoustic and structural dynamics work. As Chinese industrial and defense sectors accelerate their push toward domestic alternatives to NI hardware, understanding exactly what the PXIe-4499 offers — and what any credible replacement must match — is an essential first step for engineering teams evaluating substitutes. ## What the PXIe-4499 Is and Who Uses It The PXIe-4499 slots into a PXI Express chassis and provides 16 simultaneously sampled analog input channels, each with 24-bit resolution and a maximum sample rate of 204.8 kS/s per channel. The 114 dB dynamic range figure is a key headline: it reflects the signal-to-noise and distortion performance achievable with the on-board delta-sigma ADC architecture, which makes the module competitive with laboratory-grade measurement amplifiers when configured correctly. The --- ## [NI Domestic Alternative] PXI-4498, 204.8 kS/s, 114 dB, 4 Gain Options, 0.5 Hz AC Coupling, 16-Input PXI Sound and Vibration Module - URL: https://intl.sienovo.cn/blog/135619230 - Date: 2024-01-16 - Tags: #NIAlternative, #DAQCard The PXI-4498 is a 16-input PXI sound and vibration module from National Instruments, purpose-built for high-channel-count acoustic and structural dynamics measurements. This post covers the module's key specifications, signal conditioning architecture, and the industrial test scenarios where it delivers value — along with guidance for engineers evaluating domestic Chinese alternatives for NI PXI hardware. ## Why High-Channel-Count Sound and Vibration Acquisition Is Hard Capturing sound and vibration data across many channels simultaneously imposes requirements that general-purpose data acquisition hardware struggles to meet. Sensors like ICP/IEPE accelerometers and condenser microphones produce low-level signals that demand high dynamic range, very low noise floors, and phase-coherent sampling across every channel. A single-sample skew between channels corrupts coherence functions and cross-spectral density estimates — the foundation of noise source identification and modal analysis. --- ## [NI Domestic Alternative] PXIe-4480, 1.25 MS/s, 3.4 Hz AC/DC Coupled, 6-Input PXI Sound and Vibration Module - URL: https://intl.sienovo.cn/blog/135616054 - Date: 2024-01-16 - Tags: #DAQCard, #NIAlternative ## Overview The PXIe-4480 is a high-performance sound and vibration measurement module for the PXI Express platform, targeting engineers who need precise dynamic signal acquisition across audio, acoustic, and structural vibration domains. This article covers the module's key specifications, signal-conditioning capabilities, and typical deployment scenarios — and examines why it has become a reference point for domestic (Chinese-made) DAQ card alternatives in the PXI ecosystem. ## Key Specifications at a Glance | Parameter | Value | |---|---| | Channels | 6 simultaneous analog inputs | | Standard sample rate | 1.25 MS/s per channel | | Burst / time-domain sample rate | Up to 20 MS/s per channel | | Low-frequency AC cutoff | 3.4 Hz | | Coupling modes | AC and DC (software-selectable) | | Input range | 4 gain settings (software-configurable) | | Sensor excitation | IEPE current, voltage excitation, charge measurement | | Sensor ID | TEDS (IEEE 1451.4) | The 3.4 Hz lower cutoff in AC-c --- ## [NI Domestic Alternative] PXIe‑4492, 204.8 kS/s, 113 dB, Two Gain Ranges, 0.5 Hz AC/DC Coupling, 8-Input PXI Sound and Vibration Module - URL: https://intl.sienovo.cn/blog/135615995 - Date: 2024-01-16 - Tags: #DAQCard, #NIAlternative ## A Domestic PXI Alternative for High-Fidelity Sound and Vibration Measurement For test engineers running noise, vibration, and harshness (NVH) programs or large-scale acoustic measurement campaigns, the NI PXIe-4492 has long been a go-to reference for high-dynamic-range data acquisition inside a PXI chassis. This post introduces a domestically produced alternative module that matches the PXIe-4492's headline specifications — 204.8 kS/s sample rate, 113 dB dynamic range, 24-bit resolution, and 8 simultaneous IEPE-conditioned inputs — and explains what those figures mean in practice and where this class of hardware fits in a real measurement chain. ## What the PXIe Platform Offers for Acoustics and Vibration PXI (PCI eXtensions for Instrumentation) is a rugged, modular instrument platform built on the PCI/PCIe bus standard. A PXIe chassis provides a shared 10 MHz reference clock and trigger backplane that lets multiple modules synchronize acquisitions to sub-nanosecond precision wit --- ## [NI Domestic Alternative] PXIe‑4497, 204.8 kS/s, 114 dB, Two Gain Ranges, AC/DC Coupling, 16-Input PXI Sound and Vibration Module - URL: https://intl.sienovo.cn/blog/135615840 - Date: 2024-01-16 - Tags: #DAQCard, #NIAlternative ## Overview The PXIe-4497 is a high-performance PXI Express sound and vibration acquisition module designed for demanding multichannel acoustic and structural dynamics measurements. With 16 simultaneous-sampling analog input channels, a 204.8 kS/s per-channel sample rate, and 114 dB dynamic range backed by 24-bit resolution, it targets test engineers who need to capture wide-bandwidth, low-noise signals across many channels without introducing inter-channel timing skew. This post covers the module's key specifications, signal-conditioning architecture, and the application domains where its capabilities are most relevant—useful background whether you are evaluating the original NI hardware or a domestic PXI-compatible alternative with the same interface and feature set. ## Key Specifications at a Glance | Parameter | Value | |---|---| | Analog input channels | 16 (simultaneous) | | Maximum sample rate | 204.8 kS/s per channel | | Resolution | 24-bit | | Dynamic range | 114 dB | | Sig --- ## [NI Domestic Alternative] PXI-6254, 32 AI (16-bit, 1 MS/s), 48 DIO, PXI Multifunction I/O Module - URL: https://intl.sienovo.cn/blog/135615690 - Date: 2024-01-16 - Tags: #NIAlternative, #DAQCard The PXI-6254 is a workhorse PXI multifunction data acquisition module from National Instruments, widely deployed in automated test systems across industries ranging from semiconductor validation to aerospace manufacturing. As domestic Chinese alternatives to NI hardware continue to mature, the PXI-6254's feature set serves as an important benchmark — understanding what the original card does, and why those specifications matter, helps engineers evaluate equivalent domestic solutions with confidence. ## What the PXI-6254 Delivers At its core, the PXI-6254 is a multifunction I/O module built around four measurement pillars: - **32 analog inputs (AI)** at 16-bit resolution and up to 1 MS/s aggregate sample rate - **48 digital I/O (DIO)** lines, correlated with the analog subsystem for synchronized acquisition - **Two 32-bit counter/timer channels** for frequency measurement, pulse generation, encoder decoding, and event counting - **Analog and digital triggering**, enabling precise sta --- ## [Domestic Alternative to NI] USB‑7846 Kintex-7 160T FPGA, 500 kS/s Multifunction Reconfigurable I/O Device - URL: https://intl.sienovo.cn/blog/135589250 - Date: 2024-01-14 - Tags: #FPGADev, #NIAlternative, #DataAcquisition The Chinese source and current English body both contain real (if brief) technical product content — dedicated-ADC-per-channel architecture, FPGA programmability, LabVIEW FPGA Module integration, and specific application domains. Expanding. --- Finding a domestic, cost-effective alternative to National Instruments hardware has become a priority for many Chinese engineering teams working in test, measurement, and industrial automation. The USB-7846 — built around a Xilinx Kintex-7 160T FPGA and capable of 500 kS/s multifunction reconfigurable I/O — represents exactly that kind of alternative: a device that matches the architectural philosophy of NI's R-Series instruments while remaining accessible to local supply chains and procurement pipelines. ## What Makes the Kintex-7 160T a Strong Foundation The Xilinx Kintex-7 160T is a mid-range FPGA from the 7-series family, offering roughly 162,240 logic cells, 600+ DSP slices, and high-speed SelectIO resources. In a data acquisition conte --- ## [NI Domestic Alternative] PXIe‑6375, 208-Channel AI (16-bit, 3.8 MS/s), 2-Channel AO, 24-Channel DIO, PXI Multifunction I/O Module - URL: https://intl.sienovo.cn/blog/135589172 - Date: 2024-01-14 - Tags: #DAQCard, #NIAlternative ## Overview: A Domestic-Market Alternative to the NI PXIe‑6375 Multifunction I/O Module For test and measurement engineers building PXI-based systems, National Instruments' PXIe‑6375 has long been a benchmark multifunction I/O card. This post examines its full technical profile — 208-channel analog input, analog output, digital I/O, and four 32-bit counter/timers — and explains why domestic-market PXIe alternatives targeting this specification are gaining traction in industrial and research labs. --- ## What Is the PXIe‑6375? The PXIe‑6375 is a high-density multifunction I/O module in the PXI Express form factor. Its headline figures are: | Parameter | Value | |---|---| | Analog Input Channels | 208 (single-ended) / 104 (differential) | | ADC Resolution | 16-bit | | Max Aggregate Sample Rate | 3.8 MS/s | | Analog Output Channels | 2 | | Digital I/O Lines | 24 | | Counter/Timers | 4 × 32-bit | | Bus Interface | PCI Express (PXIe) | The 208-channel count is achieved by combining a --- ## [NI Domestic Alternative] PXIe‑6378, 16-Channel AI (16-bit, 3.5 MS/s/ch), 4-Channel AO, 48-Channel DIO, PXI Multifunction I/O Module - URL: https://intl.sienovo.cn/blog/135588481 - Date: 2024-01-14 - Tags: #DAQCard, #NIAlternative The domestic Chinese market has seen strong growth in high-performance data acquisition alternatives to National Instruments hardware, driven by supply-chain resilience requirements and cost pressures in industries ranging from telecommunications to defense. One notable entry in this space is a PXIe multifunction I/O module that mirrors the specification of the NI PXIe-6378 — offering engineers a drop-in compatible path without sacrificing measurement fidelity. ## Module Overview and Core Specifications The module is a synchronously sampled multifunction DAQ device built around the PXIe (PCI Express-based PXI Express) form factor, which is the high-bandwidth evolution of the original Compact PCI-based PXI standard. PXIe slots provide dedicated point-to-point PCIe lanes to each instrument slot, eliminating the shared-bus bandwidth contention that limits parallel high-speed acquisition in legacy PXI chassis. Key electrical specifications at a glance: | Parameter | Value | |---|---| | --- ## PXIe‑6378 Domestic Alternative, 16-Channel AI (16-bit, 3.5 MS/s/ch), 4-Channel AO, 48-Channel DIO, PXI Multifunction I/O Module - URL: https://intl.sienovo.cn/blog/135588240 - Date: 2024-01-14 - Tags: #DAQCard, #NIAlternative, #PXIe‑6378 ## Overview The PXIe-6378 is National Instruments' high-channel-density, simultaneous-sampling multifunction DAQ module in the PXI Express form factor. It targets applications that demand both high per-channel sample rates and tight synchronization across all input channels — requirements that rule out multiplexed architectures. This post breaks down the module's key capabilities, explains the underlying timing architecture, and outlines the application domains where it is commonly deployed, along with guidance for engineers evaluating domestic Chinese alternatives to NI PXI hardware. ## Key Specifications at a Glance | Parameter | Value | |---|---| | Analog inputs | 16 channels, simultaneous sampling | | ADC resolution | 16 bits | | Sample rate | 3.5 MS/s per channel | | Analog outputs | 4 channels | | Digital I/O | 48 channels | | Counters/timers | Four 32-bit counters | | Triggering | Analog and digital | | Timing engine | NI-STC3 (onboard ASIC) | | Driver | NI-DAQmx | | Form fac --- ## PXIe-6396 Domestic Alternative, 8-channel AI (18-bit, 14 MS/s/ch), 2-channel AO, 24-channel DIO, PXI Multifunction I/O Module - URL: https://intl.sienovo.cn/blog/135587993 - Date: 2024-01-14 - Tags: #NIAlternative, #DataAcquisition, #PXIe-6396 The PXIe-6396 is a high-performance, simultaneously sampling multifunction data acquisition (DAQ) module from National Instruments, widely deployed in demanding test and measurement environments. This article introduces its core capabilities and explores the domestic alternative offered by Sienovo for engineers seeking a drop-in replacement without sacrificing measurement fidelity. ## What Is the PXIe-6396? The PXIe-6396 is a PXI Express multifunction I/O module built around simultaneous sampling — meaning all analog input channels are sampled at the same instant rather than multiplexed in sequence. This is a critical distinction for applications where phase relationships between channels must be preserved, such as vibration analysis, multichannel impedance characterization, or coherent signal detection in radar and sonar systems. Its key electrical specifications are: - **8 analog input (AI) channels** at **18-bit resolution** and **14 MS/s per channel** (simultaneous) - **2 analo --- ## NI PXIe-6386 Domestic Alternative, 8-Channel AI (16-bit, 14 MS/s/ch), 2-Channel AO, 24-Channel DIO, PXI Multifunction I/O Module - URL: https://intl.sienovo.cn/blog/135583754 - Date: 2024-01-14 - Tags: #DAQCard, #NIAlternative, #PXIe-6386 ## PXIe-6386 Overview The NI PXIe-6386 is a high-performance, simultaneous-sampling multifunction DAQ module designed for PXI Express systems that demand fast, synchronized analog acquisition across multiple channels. This post covers the module's key specifications, onboard technology, and the range of demanding test and measurement applications it is built to address — along with guidance on domestic alternatives that deliver equivalent capability. ## Key Specifications at a Glance | Parameter | Specification | |---|---| | Analog Inputs | 8 channels, simultaneous sampling | | ADC Resolution | 16-bit | | Sample Rate | 14 MS/s per channel | | Analog Outputs | 2 channels | | Digital I/O | 24 channels | | Counters/Timers | 4 × 32-bit | | Triggering | Analog and digital | | Form Factor | PXI Express (PXIe) | | Driver | NI-DAQmx | The combination of 16-bit resolution and 14 MS/s per-channel simultaneous sampling places this module squarely in intermediate-frequency (IF) signal acquisit --- ## Data Acquisition Card: 24-bit, 32-channel, 256K Synchronous Analog Input Card, Supports External Trigger, External Clock, and Multi-Card Synchronization - URL: https://intl.sienovo.cn/blog/135540040 - Date: 2024-01-11 - Tags: #DataAcquisition, #TemperatureMeasurement The USB-XM2432 is a 32-channel, 24-bit synchronous analog input data acquisition card that connects directly to a host PC over USB 2.0. Designed for engineers who need high-resolution, multi-channel signal capture without the cost or complexity of a PCI/PCIe card, it targets laboratory instrumentation, quality inspection lines, medical monitoring equipment, and industrial process control. This post breaks down the card's architecture, key performance characteristics, and the scenarios where its feature set is most valuable. ## ADC Architecture: Why Σ-Δ at 24-bit Matters The USB-XM2432 uses the Analog Devices AD7768 as its converter. The AD7768 is a simultaneous-sampling, 24-bit Σ-Δ (sigma-delta) ADC with eight differential input channels per device — four of these devices are used in parallel to cover the card's full 32-channel complement. The Σ-Δ architecture trades raw speed for exceptional resolution and noise performance. Unlike successive-approximation (SAR) ADCs, a Σ-Δ converte --- ## 32-Channel Single-Ended / 16-Channel Differential 16-Bit 1000kSPS Programmable Gain AD, 8-Channel DI/DO, 4-Channel DA, 2-Channel Frequency Measurement/Counter Multifunction Data Acquisition Card - URL: https://intl.sienovo.cn/blog/135539728 - Date: 2024-01-11 - Tags: #FPGADev, #DAQCard Overview The USB-XM1636 is a high-performance data acquisition card suitable for measurement applications requiring medium to low speed and high precision. The USB-XM1636 features 32 analog inputs (configurable as single-ended or differential), 4 channels of 16-bit DA output, 8 digital input (DI) channels, 8 digital output (DO) channels, and two 24-bit frequency measurement/counters. It includes onboard programmable gain amplifiers (×1, ×2, ×4, ×8), allowing software configuration of different gain settings per channel. The device supports external clocking and external triggering, meeting a wide range of measurement requirements. Logic control is implemented using a Field-Programmable Gate Array (FPGA) to enhance reliability. Additionally, digital ground (GND) and analog ground (AGND) are separated with single-point grounding to eliminate loop interference. The USB-XM1636 uses the CYPRESS CY68013A as its USB controller chip. This board is a high-speed, high-precision USB 2.0 bus da --- ## Data Acquisition Card: 16-Channel, 16-Bit, 250KHz ADC, Supports Single-Point Acquisition and Programmable Gain - URL: https://intl.sienovo.cn/blog/135539421 - Date: 2024-01-11 - Tags: #FPGADev Overview The USB-XM1603 is a highly cost-effective, multi-functional, general-purpose A/D board. Meticulously designed, it utilizes a USB 2.0 bus, supporting hot-swapping and plug-and-play functionality without the need for address jumpers. It is suitable for measurement applications such as transmitter output and DC voltage measurements. The USB-XM1603 features 16-channel single-ended 16-bit programmable gain analog inputs, 4-channel 16-bit analog outputs, 16 digital I/O channels (8 TTL inputs and 8 TTL outputs), 2 frequency measurement channels, 2 PWM pulse output functions, and 1 (1-255) frequency divider. The logic control of the USB-XM1603 is implemented using Field-Programmable Gate Arrays (FPGAs) to enhance reliability. Additionally, digital ground (GND) and analog ground (AGND) are separated with single-point grounding to eliminate ground loop interference. This board offers very stable performance, with AD sampling stable at the mV level. Key Features and Performance A/D C --- ## Data Acquisition Card: USB 2.0 Bus, 5-Channel, 24-bit Serial 1KHz ADC, Programmable Gain 1-128x Amplification, 16-Channel DIO - URL: https://intl.sienovo.cn/blog/135531967 - Date: 2024-01-11 - Tags: #FPGADev Overview The USB-XM2401 board is a high-precision card specifically designed for weak signal measurement. It utilizes Analog Devices' AD7714 chip, based on a Σ-Δ architecture, offering 24-bit no missing codes and a self-calibration function, eliminating the need for potentiometer calibration. This ADC device also features low noise and low power consumption. The card allows software configuration of the filter cutoff frequency and programmable gain (1-128x amplification) to enhance measurement accuracy. External analog signals are input via the 20-pin IDC connector (J1) on the board. The USB-XM2401 provides 16 channels of digital input/output (DIO) with TTL levels. The 16 digital I/O signals are input/output via the 40-pin IDC connector (J2) on the board. Digital outputs feature an automatic power-on clear function, and CPU output data provides forward drive. Inputs can be configured via jumpers to be pulled high or low (factory default is pull-low) according to field requirements, --- ## Data Acquisition Card: USB 2.0 Bus, 4-Channel Synchronous, 24-bit 156KHz AD, 16-Channel DIO - URL: https://intl.sienovo.cn/blog/135531720 - Date: 2024-01-11 - Tags: #FPGADev Overview The USB-XM2404 board is a high-speed, high-precision 4-channel synchronous data acquisition card with a USB 2.0 bus, offering up to 24-bit resolution and a 156 KSPs sampling rate. This card supports external triggering and software-timed triggering. Four analog signals and one external trigger signal (falling edge trigger) are input via the IDC-20 connector P1 on the board. 16 digital inputs (DI) and 16 digital outputs (DO) are input/output via the IDC-40 connector P2. The analog input signals of the USB-XM2404 use differential input for ADC conversion. The AD conversion results are stored in large-capacity SDRAM (4M words). The AD chip itself includes a differential amplifier and a digital filter. The USB host controller chip of the USB-XM2404 card uses CYPRESS's CY68013A. This board is a high-speed, high-precision data acquisition board with a USB 2.0 bus, supporting hot-swapping and plug-and-play functionality. It utilizes Field-Programmable Gate Array (FPGA) design to --- ## USB-XM2403 USB Interface Temperature Data Acquisition Card - URL: https://intl.sienovo.cn/blog/135530209 - Date: 2024-01-11 - Tags: #FPGADev, #DataAcquisition, #TemperatureMeasurement A 24-bit temperature measurement card with a USB 2.0 bus, supporting 1-channel RTD mode and 6-channel thermocouple mode, with no external conditioning required. It also supports multi-range voltage measurement, 16-channel bidirectional I/O, 2-channel counter/frequency measurement, and 3-channel PWM output. Features Overview The USB-XM2403 is a USB interface temperature data acquisition card. The USB-XM2403 features 7 analog inputs (configurable for temperature measurement or small signal measurement), 16 DIO channels, two counter/frequency measurement channels (DIO pins multiplexed), and 3 PWM outputs. The ADC chip supports programmable gain (×1, ×2, ×4, ×8, ×16, ×32, ×64, ×128), and each channel's amplification factor can be set individually via software. The logic control of the USB-XM2403 is implemented using a Field-Programmable Gate Array (FPGA) to enhance reliability. Additionally, digital ground (GND) and analog ground (AGND) are separated with single-point grounding to elimi --- ## RV1126 Edge AI Box, Supports 4-6 Channels of 1080p Video, 2 TOPS Computing Power - URL: https://intl.sienovo.cn/blog/135509262 - Date: 2024-01-10 - Tags: #RV1126, #AI BOX ****1**** Product Overview Xinmai has launched an AI edge computing motherboard based on the Rockchip RV1126 architecture. The RV1126 chip features a quad-core ARM Cortex-A7 at 1.5GHz, an RSIC-V CPU at 200MHz, and an NPU with 2.0 TOPS. The AI edge computing motherboard offers rich peripheral interfaces and strong expandability, making it widely applicable in AI intelligent fields such as smart security, industrial internet, smart cities, smart transportation, and smart healthcare. Chip Block Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/135509262/01_36790b80a98ba21fb28159fcb3c01ed4.png) ****2**** Platform Features * The Rockchip RV1126 adopts a 14nm process, featuring a quad-core ARM Cortex-A7 at 1.5GHz, an RSIC-V CPU at 200MHz, and an NPU with 2.0 TOPS; Its built-in NPU supports INT8/INT16 mixed-precision operations, perfectly balancing performance, power consumption, and computational accuracy, and supports network model conversion for frameworks like T --- ## NI PC-based Measurement and Control Systems - URL: https://intl.sienovo.cn/blog/135447184 - Date: 2024-01-08 - Tags: #AI, #FPGADev PC-based measurement and control systems provide engineers with electrical and physical measurement capabilities, enabling them to perform benchtop measurements in a customizable, accurate, and cost-effective manner. What are PC-based Measurement and Control Systems? In PC-based measurement and control systems, NI hardware products connect to a PC or laptop via USB or Ethernet. These systems feature two main architectures: connecting a multifunction I/O device directly to a PC, or connecting a CompactDAQ chassis to a PC and inserting conditioned I/O modules into that chassis. CompactDAQ offers solutions with excellent customizability for direct sensor connection. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/135447184/01_20e4b03707f759134aa87e89eee06e3e.png) Key Features of PC-based Measurement and Control Systems Quickly Capture and Explore Data, and Customize Your Measurement System All PC-based DAQ hardware comes with DAQExpress™ companion software, which allows --- ## Implementing the NI CompactRIO System with Real-time Linux + FPGA: A Detailed Guide - URL: https://intl.sienovo.cn/blog/135447124 - Date: 2024-01-07 - Tags: #FPGADev, #DataAcquisition, #Automation, #AI Leverage an integrated software toolchain, combined with signal conditioning I/O modules, to easily build and deploy real-time applications. What is CompactRIO? The CompactRIO system offers high processing performance, sensor-specific I/O, and tightly integrated software tools, making it an ideal choice for industrial IoT, monitoring, and control applications. Real-time processors provide reliable, predictable behavior, while FPGAs excel at smaller tasks requiring high-speed logic and precise timing. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/135447124/01_db2a599ad8cc0583750abe7dbed376ed.png) Flexible Development Options Using LabVIEW with the Real-Time Module and FPGA Module, abstract away low-level code and use tools to build and deploy deterministic applications on CompactRIO systems. Robust Data Acquisition Using integrated controllers running NI Linux Real-Time OS and sensor I/O modules, build and deploy robust applications directly on the CompactRIO contr --- ## X86-Based Edge Computing Empowers Intelligent Shipboard Monitoring Systems - URL: https://intl.sienovo.cn/blog/135432375 - Date: 2024-01-06 - Tags: #AI, #Marine, #DataAcquisition, #Acquisition The integrated shipboard monitoring system combines radar, AIS, CCTV, GPS, and other sensing technologies with highly fused real-time situational awareness and cognitive technologies. It enables effective monitoring of the vessel itself and surrounding ships, extends the surveillance range of shore-based control centers, ensures navigation safety, and provides maritime safety authorities with multiple technical means for shore-controlled data communication and dynamic data acquisition. **PART/1** **Customer Application Requirements** The shipboard remote data acquisition controller serves as an MEC (Multi-access Edge Computing) device that enables communication control between ship and shore, and collects vessel navigation data, engine room status, marine weather, and AIS data. It is a critical device for maritime safety authorities to achieve shore-based controllable data communication and dynamic data collection. ![图片](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/1354 --- ## ARM+FPGA多通道信号采集与处理模块开发方案 - URL: https://intl.sienovo.cn/blog/135415541 - Date: 2024-01-05 - Tags: #ARMDev, #FPGADev ## ******Development Solution for Multi-channel Signal Acquisition and Processing Module****** Develop a multi-channel optoelectronic signal acquisition and processing module to implement acquisition, processing, and storage functions for 64 sensor channels. It mainly comprises data acquisition and processing circuits, system control software, signal processing algorithm implementation, and data storage. This includes 8-channel ADCs, where each ADC's sampled data corresponds to 8 sensor signals, totaling 64 sensor signals acquired. The processing chip performs real-time signal processing on each of the 64 sensor signals and stores them to a hard drive. Signal Processing Flow: 8-channel AD acquisition (typical sampling rate 80MHz) -- Pre-processing to generate 64 raw signals with a typical sampling rate of several hundred kHz (typical value 400kHz) -- Real-time computational processing of 64 raw signals -- Storage to hard drive and transmission to external devices via network. Key T --- ## Marine Data Acquisition and Analysis Online Energy Monitoring Solution - URL: https://intl.sienovo.cn/blog/135372543 - Date: 2024-01-03 - Tags: #Energy ### I. Prospects for Marine Online Energy Monitoring Applications 　　Marine online energy monitoring has broad application prospects in areas such as energy efficiency optimization, fault diagnosis and predictive maintenance, energy saving and emission reduction and environmental regulation, data analysis and decision support, and automation and intelligence. As the marine industry's demands for energy management and environmental protection continue to rise, marine online energy monitoring technology will become an important tool in ship operation and management. ![船舶在线能源监控png](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/135372543/01_78d322ee4945640b43f48d733e153bd5.png) ### 　　II. Application Examples of Industrial PCs in Marine Online Energy Monitoring 　　Industrial PCs play a crucial role in marine online energy monitoring, used for data acquisition and processing, real-time monitoring and display, data storage and management, data communication and remote monitoring --- ## Customer Case Study: Unmanned Surface Vessel Codesys Controller Solution - URL: https://intl.sienovo.cn/blog/135372457 - Date: 2024-01-03 - Tags: #AI With the widespread application of AI and IoT technologies in the transportation industry, related technologies for unmanned transport systems have developed rapidly. As a primary transport tool in the shipping industry, Unmanned Surface Vessels (USVs) have an intelligence level that largely determines the economic efficiency and safety of waterborne transportation. Therefore, motion control problems have been extensively studied in recent decades. However, increasingly complex environments and diverse tasks pose new requirements for vessel intelligence, and simple intelligent control can no longer meet these demands. Consequently, an Unmanned Surface Vessel solution based on a fanless industrial PC has been proposed, which will reshape the landscape of global ocean shipping. Shenzhen XX Shipbuilding Co., Ltd. plans to launch an Unmanned Surface Vessel capable of carrying various detection instruments. Its requirements for the control computer are as follows: High-performance host c --- ## Marine Data Acquisition and Analysis Automation and Equipment Control System Solution - URL: https://intl.sienovo.cn/blog/135372311 - Date: 2024-01-03 - Tags: #Automation, #DevOps, #DataAcquisition, #AI **Project Introduction** A Jiangsu-based automation technology company, built on automation control, is dedicated to providing comprehensive solutions for marine power plant and power distribution systems, marine engine room automation systems, marine main engine control and steering control systems, marine network transmission systems, marine safety monitoring and explosion-proof systems, marine dynamic positioning systems, marine electric propulsion systems, and marine variable frequency drive and control systems. Leveraging the scientific research capabilities and marine industry background support of Jiangsu University of Science and Technology, the company primarily focuses on the production and services of marine power distribution series products, engine room automation consoles, variable frequency drive and electric propulsion products, main engine remote control and steering consoles, and safety monitoring system products. It provides reliable product support and technical --- ## STM32 EtherCAT Bus-Type (1-to-4) Stepper Motor Solution - URL: https://intl.sienovo.cn/blog/133064240 - Date: 2024-01-03 - Tags: #MCU, #EmbeddedHardware **Chapter 1 Overview**  **Technical Features**  Supports standard 100M/s bandwidth full-duplex EtherCAT bus network interface and CoE communication protocol with one input and one output (RJ45 interface), supports automatic mapping of multiple dynamic PDO groups and object dictionaries, supports automatic setting and saving of station ID, and supports SDO motor parameter setting and automatic saving.  Automatically adapts to commercially available EtherCAT bus master systems or PLC motion controllers, such as TwinCAT, Codesys, Omron, Trio, SOEM, IGH, Acontis, KPA, etc.  Supports standard CiA DS402 protocol, with built-in Cyclic Synchronous Position (CSP mode) and Homing control mode.  Supports driving up to 4 stepper motors, achieving multi-axis synchronous real-time control, offering the highest cost-performance ratio.  Built-in 12-channel 5V or 24V digital IO signal inputs, using bidirectional optocouplers, supporting NPN and PNP types, for general digital IO acquisition --- ## Industrial Soft PLC Solution Based on NXP i.MX8 + CODESYS - URL: https://intl.sienovo.cn/blog/135310513 - Date: 2023-12-30 - Tags: #EdgeComputing, #codesys, #I.MX8P > > > The new i.MX 8M Plus is a hybrid AI SoC, combining advanced embedded SoC capabilities with the latest AI/machine learning hardware NPU technology. It provides powerful machine learning capabilities for edge computing through its neural network accelerator, which is one of the most prominent advantages of the i.MX 8M Plus. The WEC-IMX8P core board is particularly well-suited for applications in machine learning, vision, advanced multimedia, and high-reliability industrial IoT. > > > > > > **▇ XM-IMX8P Core Board** > > > > > > High-Performance Edge AI Solution > > > > > > ⚪ High-performance i.MX 8M Plus processor: Quad-core ARM Cortex-A53 + Cortex-M7 + NPU; > > > > > > ⚪ Powerful edge AI capabilities: NPU computing power up to 2.3 TOPS; > > > > > > ⚪ Single 4GB LPDDR4 SD-RAM; > > > > > > ⚪ Supports 2-channel 10/100/1000Mbps Ethernet; > > > > > > ⚪ Supports rich peripheral interfaces: 4 serial ports, 1 USB 3.0, 1 USB 2.0, 2 MMCs, 3 IICs, 2 SPIs, 2 CAN buses, 2 MCASP audio ch --- ## Low-Cost ARM+FPGA+Codesys Soft PLC Solution Based on AM62x - URL: https://intl.sienovo.cn/blog/135310437 - Date: 2023-12-30 - Tags: #FPGADev, #ARMDev, #codesys **Introduction to GPMC Parallel Interface** GPMC (General Purpose Memory Controller) is a unique general-purpose memory controller interface specific to TI processors. It supports 8/16-bit data width, provides up to 128MB of addressable space, and operates at a maximum clock rate of 133MHz. GPMC is the dedicated interface used in processors such as AM62x, AM64x, AM437x, AM335x, and AM57x for connecting to external memory devices, including: (1) FPGA devices (2) ADC devices (3) SRAM memory (4) NOR/NAND flash **Three Key Features of GPMC Parallel Interface** (1) Small Data – Low Latency In industrial automation applications such as industrial PLCs, integrated drive and control units, motion controllers, CNC mainboards, relay protection equipment, and small-current grounding line selection systems, precision and speed are critical. The "small data – low latency" characteristic of the GPMC parallel interface stands out, significantly improving data transfer efficiency an --- ## STM32+Codesys Industrial Software PLC Solution - URL: https://intl.sienovo.cn/blog/135310332 - Date: 2023-12-30 - Tags: #codesys, #stm32 Industrial control systems play a crucial role in modern manufacturing and automation. CODESYS, a controller programming and development software platform based on the IEC 61131-3 standard, is suitable for developing control systems across various industries, enabling users to quickly and easily program and configure automation projects, and complete project development, software testing, and application debugging. This time, STM32, in collaboration with its partner CODESYS, will guide you through an in-depth understanding of how to leverage STM32 and CODESYS to create powerful industrial control systems, as well as the underlying logic of industrial control systems. Through practical examples, we will help you seamlessly apply the knowledge gained to real-world engineering projects. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/135310332/01_6308fbae88948675875b47e0863bf549.png) Tool Introduction CODESYS ([Industrial Control](https://baike.baidu.com/item/%E5%B7%A5%E --- ## Data Acquisition and Processing System for Ship Structure Health Monitoring (Part 1) System Architecture - URL: https://intl.sienovo.cn/blog/135188661 - Date: 2023-12-24 - Tags: #DataAcquisition, #PXI, #Marine The rapid development of world trade began in the Age of Sail. Ships, as important waterborne transportation tools, offer advantages such as large carrying capacity and low freight costs. However, issues of excessive stress values at certain structural points during ship operation often lead to significant losses for operating departments, and can even cause numerous casualties and severe environmental pollution. Therefore, real-time monitoring of stress conditions at ship monitoring points and tracking stress information at various critical monitoring points will enhance ship operational safety and prevent major economic losses due to hull structure damage. In the data acquisition and processing system, the supervisory computer adopts a C/S (Client/Server) architecture, and the embedded controller adopts a B/S (Browser/Server) architecture. It is divided into four parts: sensors, demodulator, embedded controller, and supervisory computer. The embedded controller can perform all syst --- ## RK3568 Nationwide Domestic Multi-Port Board with PoE, CAN Bus, Supporting HarmonyOS and Kylin Systems - URL: https://intl.sienovo.cn/blog/134971901 - Date: 2023-12-20 - Tags: #Networking, #HarmonyOSDevCommunity, #Community The Sienovo XM-3568-01 motherboard features the Rockchip RK3568 quad-core Cortex-A55 processor, with a maximum clock frequency of up to 2.0GHz, delivering significantly enhanced performance. It supports up to 8GB of memory with a frequency of up to 1600MHz and full-chain ECC support for improved data security and reliability. The board integrates dual gigabit adaptive RJ45 Ethernet ports and expands four additional Ethernet controllers (I211), suitable for applications such as gigabit routers, soft routers, and firewalls. Supports HarmonyOS, Android 11, and Linux. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134971901/01_333d85f4c1267088df784e0a5374db39.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134971901/02_10fe3ed104507918c35732832aabecb8.png) **Processor System** CPU RK3568, ARM Cortex A55, Quad-core, 2 GHz GPU G52 2EE, OpenGL ES1.1/2.0/3.0/3.1/3.2, Vulkan 1.1, OpenCL 2.0 NPU RK NN, 0.8 TOPS **Memory** Type 32-bit, LP4/LP4x Capaci --- ## Rockchip RV1126 Edge Computing Box with High Cost-Performance 2.0 TOPS INT8/INT16 - URL: https://intl.sienovo.cn/blog/135010873 - Date: 2023-12-15 - Tags: #EdgeComputing, #AI ## ## Edge Computing Box Rockchip RV1126 | 2.0 TOPS INT8/INT16 ● Integrated NPU with computing power up to 2.0 TOPS@INT8/INT16. ● Supports H.264/H.265/MJPEG video encoding and decoding; supports multi-level video quality configuration and encoding complexity settings. ● Encoding and decoding performance:     3840 x 2160@30 fps + 1080p@30 fps encoding     3840 x 2160@30 encoding + 3840 x 2160@30 fps decoding ● Maximum decoding resolution: 4096x2304@30fps. ● Supports a series of deep learning frameworks including TensorFlow, MXNet, PyTorch, Caffe, meeting diverse developer requirements. ● Rich peripheral interfaces: Ethernet, HDMI in/out, RS232, RS485, Line in/out, Wi-Fi, TF, etc. The edge computing box is a deep intelligent edge computing device designed by Xinmai Technology based on the RV1126. The core RV1126 adopts a highly integrated precision architecture, featuring a quad-core ARM Cortex-A7@1.5GHz and RISC-V architecture. The entire device features lightweight design, --- ## RK3568 Fully Domestic Multi-Port Board with Built-in UPS Support and Compatibility with Kylin and SylixOS National Operating Systems - URL: https://intl.sienovo.cn/blog/135010379 - Date: 2023-12-15 - Tags: #Networking The Sienovo XM-3568-01 motherboard features Rockchip's RK3568 quad-core Cortex-A55 processor, with a maximum frequency of up to 2.0GHz, delivering significantly enhanced performance. It supports up to 8GB of memory with frequencies reaching 1600MHz and offers full-chain ECC support for improved data security and reliability. The board is equipped with dual Gigabit adaptive RJ45 Ethernet ports and expands four additional Ethernet controllers via I211 chips, making it ideal for applications such as Gigabit routing, soft routers, and firewalls. Supports HarmonyOS, Android 11, and Linux. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/135010379/01_333d85f4c1267088df784e0a5374db39.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/135010379/02_10fe3ed104507918c35732832aabecb8.png) Support for Domestic Operating Systems * ### Galaxy Kylin Embedded Operating System V10 Galaxy Kylin Embedded OS V10 is a secure, real-time embedded operating system design --- ## 6U CPCI Measurement and Control Series Customizable Measurement and Control Chassis - URL: https://intl.sienovo.cn/blog/134976136 - Date: 2023-12-13 - Tags: #MCU, #EmbeddedHardware **CPCI Measurement and Control Series** ### **XM-3646** Built-in 300Wh smart lithium battery for ultra-long endurance Optional external battery for unlimited endurance Compliant with CPCI bus standard specifications Built-in 6U 4-slot CPCI backplane Built-in CPCI-9370 controller Can integrate functional modules such as data acquisition, avionics bus, and communication interfaces All aluminum-magnesium alloy ruggedized compact design Special anti-collision corner protectors and silicone handle design 15.6'' HD display with 1920x1080 resolution Industrial resistive touchscreen or multi-touch capacitive touchscreen Industrial touchpad and waterproof silicone keyboard 9V~32V DC wide voltage input (with dedicated 24V power adapter) CPCI card cage with 46mm recessed design Aviation plug design for power input connector Flexible customization for IO aviation plug interfaces ![](https://pub-048dcb96257f476697b113fcb5939cb8.r2.dev/blog/134976136/01_6e63c9611bea49deb9c72d516d04 --- ## PXI/PCIe/VPX Chassis ARM|x86 + FPGA Test and Measurement Board Solution - URL: https://intl.sienovo.cn/blog/134974961 - Date: 2023-12-13 - Tags: #DataAcquisition, #PXI, #CPCI, #VPX The portable PXI test and control system is a field-deployable measurement and control solution based on the PXI bus. It fills the gap left by conventional benchtop and rack-mounted instruments in field test and portable measurement applications. Widely used in military defense, aerospace, weapons electronics, naval systems, and scientific research, this system meets the demanding requirements of real-world testing environments. Due to the unique nature of portable PXI systems, different measurement and control projects have highly varied requirements. Major international and domestic vendors in the test and control industry rarely invest in R&D specifically for these low-volume, customized solutions. This article begins with an introduction to National Instruments (NI) and the PXI bus, then systematically explores the background and specific needs driving the development of portable PXI test and control systems. It details their unique characteristics and customization demands. The --- ## Intelligent Fault Diagnosis System for Marine Electrical and Mechanical Equipment - URL: https://intl.sienovo.cn/blog/134885345 - Date: 2023-12-08 - Tags: #Networking 1. Expert System for Marine Electrical Equipment Fault Diagnosis Architecture The overall system architecture adopts a browser/server (B/S) three-tier architecture (as shown in Figure 1). The B/S model is a system platform based on web technologies. It decomposes the server component of the traditional client/server (C/S) model into a data server and one or more application servers (web servers), forming a three-tier client-server architecture. The three-tier architecture enhances system scalability, effectively improves usability, and reduces system maintenance efforts. Moreover, the client requires only a simple and user-friendly browser, making operations easier for users. Since different vessels are equipped with different devices during actual voyages, a general-purpose fault diagnosis expert system—designed for multiple devices rather than dedicated to a single device—can be achieved by leveraging the extensibility, scalability, and flexibility of the three-tier architecture. --- ## Fault Diagnosis Documentation for Marine Electromechanical Equipment Vibration Acquisition Systems - URL: https://intl.sienovo.cn/blog/134885309 - Date: 2023-12-08 - Tags: #Database, #Marine, #DataAcquisition 0 Introduction Professional and advanced technologies are required to monitor and inspect the operation of ships during navigation. Currently, in China, the most commonly used method is the electromechanical equipment vibration acquisition system, which collects data from operating vessels and integrates the corresponding information. This approach enables more accurate identification of fault locations and specific issues. Such visualized analysis benefits the development of the maritime industry. 1 Research Background During operation, ships rely on various electromechanical devices to provide power. In this process, these devices generate significant noise while running. Once a fault occurs in an electromechanical device, it may be masked by the noise, making it difficult to identify the root cause. Continuous technological advancements are therefore necessary to address this issue. By employing vibration acquisition systems, faulty electromechanical equipment can be automatical --- ## Vibration Data Acquisition and Monitoring System Solution for Marine Mechanical and Electrical Equipment - URL: https://intl.sienovo.cn/blog/134882410 - Date: 2023-12-08 - Tags: #DataAcquisition During marine vessel operations, a vibration data acquisition system is typically required to monitor the performance of various mechanical and electrical equipment. This enables rapid early warning, diagnosis, analysis, and maintenance when equipment failures occur, ensuring the normal operation of marine mechanical and electrical systems, thereby safeguarding both crew members and the vessel itself. Various mechanical and electrical systems on board generate significant noise. When equipment malfunctions, these issues may be masked by ambient noise, making them difficult to detect even during manual inspections. Time-consuming processes, high error rates, and poor timeliness further increase the risk of undetected faults. By leveraging industrial intelligent gateways, automatic data collection and fault alarms can be achieved, enabling quick identification and resolution of problems, thus optimizing operational efficiency. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/bl --- ## Compact Data Acquisition Modules and Chassis: Domestic Alternatives - URL: https://intl.sienovo.cn/blog/134282158 - Date: 2023-12-08 - Tags: #linux, #Networking, #Server ### What is CompactDAQ? CompactDAQ systems can acquire and deliver validated data that meets your testing needs, regardless of distance or environment. These customizable, portable solutions are composed of different data acquisition modules, which can achieve synchronized measurements over a network, helping you digitize data. They can also be deployed closer to sensors, thereby minimizing noise and simplifying field wiring. ![CompactDAQ systems consist of a CompactDAQ chassis, CompactDAQ modules, and software such as DAQ Express, FlexLogger, or LabVIEW.](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134282158/01_33ce247f686ff2a003d38c6bdce82adb.png) ![Precise Sensor Measurements](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134282158/02_d3a60c55f75ab0bdd2c015686155cb9f.png) Precise Sensor Measurements NI offers over 70 models of high-quality C Series I/O modules with built-in sensor or signal conditioning capabilities for you to choose from. You can mix a --- ## RK3588+MCU Robot Controller Solution - URL: https://intl.sienovo.cn/blog/134794429 - Date: 2023-12-04 - Tags: #MCU, #Robotics, #EmbeddedHardware 1 Product Introduction The XMP04A is a high-performance, low-power edge computing device designed by Xinmai Technology based on the RK3588. It features a built-in NPU with computing power up to 6.0TOPS@INT8, and powerful video encoding and decoding capabilities, supporting up to 32 channels of 1080P@30fps decoding and 16 channels of 1080P@30fps encoding. It supports 4K@120fps or 8K@30fps HDMI image output. With its lightweight and highly flexible design, it can be widely applied in smart transportation, smart parks, smart gas stations, transparent kitchens, and other domain scenarios, delivering optimized performance for various AI application scenarios. 2 Product Features ****Powerful Processor**** ² Adopts a Big-Little heterogeneous architecture, featuring quad-core A76 + quad-core A55, with CPU clock speeds up to 2.4GHz. It provides 1MB L2 Cache and 3MB L3 Cache, offering stronger CPU computing power. ² High-performance quad-core Mali-G610 GPU, supports at least two 4K UIs, an --- ## Domestic AI Edge Computing Box, Dual-core A55 | 2.5 Tops Computing Power - URL: https://intl.sienovo.cn/blog/134754665 - Date: 2023-12-02 - Tags: #EdgeComputing, #AI ## Edge Computing Box Dual-core A55 | 2.5 Tops Computing Power ● 2.5 Tops@INT8 computing power, supports INT8/INT4/FP16 multi-precision mixed quantization. ● 4 channels or more of 1080p@30fps video encoding and decoding, IVE module independently provides image basic operator acceleration. ● Supports Caffe, ONNX/PyTorch deep learning frameworks, provides basic AI algorithm examples such as ResNet50 and YOLOv5. ● MindStudio graphical development environment, integrates model conversion and quantization, and network performance optimization tools to improve application development efficiency. ● Supports Docker containerized deployment and Ubuntu 20.04 system environment, facilitating cluster management and application expansion. ● Supports multiple network communication methods (dual Ethernet, WiFi/4G networking, etc.), providing convenience for remote management and control of edge computing nodes. ● Expandable with SATA hard drive or TF flash card to meet large-capacity data st --- ## Sophon-based Domestic AI Edge Computing Box, 8-core A53 | 10.6 TOPS Computing Power - URL: https://intl.sienovo.cn/blog/134754567 - Date: 2023-12-02 - Tags: #AI, #EdgeComputing ## Edge Computing Box 8-core A53 | 10.6 TOPS Computing Power ● Computing power up to 10.6 TOPS, a single chip supports real-time decoding of up to 8 channels of H.264 & H.265. ● Expandable with 4G/5G/WIFI wireless network connectivity, providing convenience for edge business deployment. ● Supports RS232 /RS485/USB2.0/USB3.0/HDMI OUT/Dual Gigabit Ethernet, etc. ● Low-power design, combined with enclosure heat dissipation. ● Supports -20℃～+60℃ wide operating temperature range. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134754567/01_278b76b2459f9a40b52c2562e462a157.png) A highly integrated smart workstation with powerful computing performance, featuring a built-in third-generation TPU. The processor is an 8-core ARM Cortex-A53 with a clock speed up to 2.3GHz, and INT8 computing power up to 10.6 TOPS. This smart workstation supports wide operating temperature environments and can be flexibly deployed in various AI scenarios, finding wide applications in smart fac --- ## Domestic AI Edge Computing Box Based on Sophon, with Powerful Built-in TPU | 32 TOPS INT8 Computing Power - URL: https://intl.sienovo.cn/blog/134754410 - Date: 2023-12-02 - Tags: #AI, #EdgeComputing ## Edge Computing Box Powerful Built-in TPU | 32 TOPS INT8 Computing Power ● TPU platform box supporting floating-point operations, with high computing power of 32 TOPS@INT8, 16 TFLOPS@FP16, and 2 TFLOPS@FP32. ● Single chip supports real-time decoding of up to 32 channels of H.264 & H.265. ● Supports the domestic AI framework PaddlePaddle, and is compatible with mainstream deep learning frameworks such as Caffe /TensorFlow/MxNet/PyTorch/ONNX. ● Supports Docker containerized deployment and Python development environment. ● Features OTA (Over-The-Air) upgrade capability. ● Low-power design, combined with passive cooling from the enclosure. ● Supports wide operating temperature range of -20℃ to 60℃. ● Compatible with the domestic Kylin operating system. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134754410/01_a4518a6ae6e01789da38e6b90d592e20.png) This highly integrated smart workstation offers ultra-strong computing performance with a powerful built-in TPU, de --- ## Sophon-powered Domestic AI Edge Computing Box: 8-core A53 | 17.6 TOPS Computing Power - URL: https://intl.sienovo.cn/blog/134754288 - Date: 2023-12-02 - Tags: #AI, #EdgeComputing ## Edge Computing Box 8-core A53 | 17.6 TOPS Computing Power ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134754288/01_b79d21dc0369d36312e78b822c2f91c4.jpeg) ● Provides 17.6 TOPS (INT8) peak computing power and 2.2 TFLOPS (FP32) high-precision computing power, with a single chip supporting up to 32 channels of H.264 & H.265 real-time decoding. ● Supports mainstream deep learning frameworks such as Caffe / TensorFlow / MxNet / PyTorch / ONNX / PaddlePaddle, making it one of the few edge computing devices in the industry that is compatible with both domestic and international deep learning frameworks. ● Supports Docker containerized deployment and Python development environment. ● Deep learning development toolkit, including underlying libraries (ffmpeg, OpenCV, etc.), inference deployment tools, and a series of other software tools, covering capabilities such as model optimization and efficient runtime support required during the neural network inference stage. ● --- ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Transparent Kitchens - URL: https://intl.sienovo.cn/blog/134734159 - Date: 2023-12-02 - Tags: #AI, #EdgeComputing ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Transparent Kitchens Transparent kitchen solutions have become increasingly popular in the food service industry, enabling customers to observe kitchen staff operations and ensuring a safe, hygienic, and trustworthy dining environment. In this article, we will delve into the implementation of a transparent kitchen solution using an AI edge computing box and AI algorithm integrated hardware-software solution. ### Solution Overview The transparent kitchen solution is designed to provide real-time monitoring and supervision of kitchen activities. It consists of several modules, each responsible for detecting specific aspects of kitchen operations. These modules include attire compliance detection, personnel behavior compliance, rodent activity monitoring, smoke and flame detection in safe zones, smoking detection, mask wearing monitoring, trash can lid status and overflow detection, and mobile phone usage --- ## Reservoir Monitoring AI Visual Algorithms and Edge Computing Box - URL: https://intl.sienovo.cn/blog/134739452 - Date: 2023-12-01 - Tags: #AI, #Algorithm, #EdgeComputing ## **01** ## **Riverbank Litter Accumulation** **Scenario Description:** River debris is often carried by currents and deposited on riverbanks. This system provides 24-hour real-time identification of litter accumulation along riverbanks, aiming to improve the efficiency of river cleanup and reduce the workload of environmental workers. **Applicable Scenarios:** Applicable for identifying litter accumulation around riverbanks during daytime or nighttime with good lighting conditions. **Model + Post-processing:** River Litter Detection **Camera:** Resolution: 1K and above, 4K and below Target Image: Litter Minimum Target Pixel Size: 75*75 pixels or more per 1K resolution **Lighting Conditions:** Illuminance: 90lux ≤ Illuminance ≤ 1200lux Lighting Type: Color visible light **Minimum Pixel Monitoring Distance Limit (meters):** **2.8mm** **4mm** **6mm** **8mm** 9m 13m 20m 27m **Algorithm Effect Diagram:** ## **02** ## **River Floating Object Identification** **Scen --- ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Finance - URL: https://intl.sienovo.cn/blog/134734354 - Date: 2023-12-01 - Tags: #BigData, #AI ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Finance In the rapidly evolving financial landscape, traditional service halls face numerous challenges, including outdated operational management models, inefficient resource allocation, suboptimal staff training outcomes, and fragmented customer experiences. To address these issues, deploying an AI edge computing box with an integrated hardware-software solution for smart finance can help enterprises transition from traditional to digital finance models. This article will explore how such a solution can enable personalized one-on-one services for each customer, precise advertising and business resource allocation, and actionable, continuous improvement plans for staff performance. ### Solution Overview The proposed solution leverages the power of big data analytics to drive business decisions and improve customer experiences. By integrating AI algorithms with hardware components, the solution p --- ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Factories - URL: https://intl.sienovo.cn/blog/134734311 - Date: 2023-12-01 - Tags: #AI, #EdgeComputing, #Retail ## The Case for AI at the Factory Edge Traditional manufacturing facilities face a familiar cluster of operational challenges: equipment failures that weren't predicted in time, safety incidents that could have been prevented, workers whose attendance and compliance are hard to verify at scale, and production lines where defects slip through until it's too late. These aren't edge cases — they're endemic to the industry. An AI edge computing box paired with pre-integrated AI algorithms offers a practical path to addressing all of them from a single hardware-software platform deployed on the factory floor, without routing sensitive video and sensor data through a remote cloud. This post walks through the smart factory solution architecture centered on Sienovo's edge AI hardware, covering the specific detection and recognition modules it supports, how they interact in a unified topology, and the measurable operational gains manufacturers can expect. ## Why Edge AI for Smart Manufacturi --- ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Retail - URL: https://intl.sienovo.cn/blog/134734243 - Date: 2023-12-01 - Tags: #AI, #Retail, #EdgeComputing ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Retail The retail industry is one of the largest and fastest-growing sectors globally, with China being the world's largest consumer market. As a result, internet giants like Alibaba and Tencent are heavily investing in this space to capitalize on its tremendous growth potential. Sienovo's Smart Retail solution is designed to cater to various retail sectors, including fast-moving consumer goods (FMCG), apparel, food and beverage, hospitality, home and beauty, consumer electronics, new retail operators, and more. By leveraging foot traffic analytics, the solution generates precise customer profiles and insights into consumer behavior, enabling targeted advertising, customer flow management, improved conversion rates, and increased average transaction value. ### Solution Topology The Sienovo Smart Retail solution is built on a robust edge-AI computing platform that integrates hardware and software --- ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Construction Sites - URL: https://intl.sienovo.cn/blog/134733998 - Date: 2023-12-01 - Tags: #AI, #EdgeComputing Construction sites are among the most hazardous work environments in the world, and traditional manual supervision has proven insufficient for managing the full scope of safety risks across large, dynamic job sites. AI-powered edge computing solutions address this gap by deploying real-time computer vision inference directly on-site — eliminating the latency of cloud round-trips and enabling immediate, automated alerts when safety violations occur. This post walks through a hardware-software integrated solution built specifically for smart construction site deployments, covering the detection scenarios it targets, its system topology, and the management platform that ties it all together. ## Why Edge AI for Construction Sites Cloud-based video analytics require video streams to be uploaded continuously, which creates bandwidth pressure and introduces hundreds of milliseconds of latency — unacceptable when detecting a worker without a hard hat near heavy machinery or a fire igniting i --- ## AI Edge Computing Box + AI Algorithm Hardware-Software Integrated Solution for Smart Communities - URL: https://intl.sienovo.cn/blog/134733860 - Date: 2023-12-01 - Tags: #AI, #EdgeComputing According to statistics, there are approximately 450,000 residential communities nationwide. Demands such as monitoring objects falling from height, managing illegal dumping, personnel management, fire and smoke detection, illegal occupation of public space, pedestrian flow detection, and vehicle type detection are closely related to every participant in creating community safety. According to publicly available court data, there are over 1,000 cases annually related to objects falling from height. Incidents of objects falling from height pose significant dangers and are increasing year by year, sounding an alarm for "overhead" safety. Deploying Xinmai's smart community management solution can effectively supervise behaviors such as objects falling from height, illegal dumping personnel management, fire and smoke detection, vehicle recognition, and delivery personnel recognition. The recognition accuracy rate reaches over 85%, playing a positive and beneficial role in providing pre-em --- ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Gas Stations - URL: https://intl.sienovo.cn/blog/134727286 - Date: 2023-12-01 - Tags: #AI Due to the unique nature of the gas station industry, oil depots and stations typically store large quantities of refined fuel to meet sales demands, making personnel and property safety a top priority. Sienovo's Smart Gas Station Solution focuses on station safety and digitalization, delivering an all-in-one intelligent safety solution for gas stations. The solution covers safety management in service areas and fuel unloading zones. By leveraging intelligent recognition and analysis technologies such as AI edge computing boxes and cameras, it enables real-time video content analysis to detect anomalies and predict risks. This provides the most efficient and direct method to enhance gas station safety. The system supports detection of fire and smoke in operational zones, mobile phone usage, unauthorized personnel intrusion, staff behavior compliance, on-duty/off-duty status, smoking, license plate recognition, and more—enabling proactive responses to potential threats. Its lightweight --- ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Parks - URL: https://intl.sienovo.cn/blog/134727215 - Date: 2023-12-01 - Tags: #EdgeComputing, #AI Industrial parks present some of the most demanding environments for physical security and operational management. Dense workforces, high contractor and migrant-worker populations, continuous vehicle movement, and sprawling perimeters all compound the challenge of keeping a facility safe, compliant, and efficient. This post walks through Yingma's (英码) hardware-software integrated AI edge computing solution for smart parks — what problems it solves, how its topology is structured, and what each AI module actually does on the ground. ## Why Traditional Surveillance Falls Short in Industrial Parks Legacy CCTV deployments in industrial parks typically rely on human operators reviewing footage after an incident, or at best triggering motion-based alerts that flood security teams with false positives. Neither approach scales well when you have thousands of workers rotating across shifts, dozens of entry points, and mixed vehicle-pedestrian zones operating simultaneously. The specific risk --- ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Transportation - URL: https://intl.sienovo.cn/blog/134727121 - Date: 2023-12-01 - Tags: #AI Urban traffic networks are the circulatory system of a modern city—moving people, goods, and emergency services while simultaneously generating enormous volumes of unstructured video data that no human operator team can monitor at scale. Sienovo's AI Edge Computing Box, paired with an integrated hardware-software stack purpose-built for smart transportation, addresses this challenge by bringing real-time inference directly to the roadside edge, eliminating the latency and bandwidth cost of sending raw video to a central data center before acting on it. ## The Problem: Traditional Traffic Enforcement at Scale Conventional traffic management relies on fixed cameras whose footage is shipped to back-end servers for analysis—often minutes or hours after an event. By the time a violation is flagged, the vehicle is long gone and the congestion has worsened. Enforcing regulations against over-length loads, overweight trucks, and speeding requires either dedicated weigh stations (capital-inte --- ## AI Edge Computing Box + AI Algorithm Integrated Hardware-Software Solution for Smart Power Safety - URL: https://intl.sienovo.cn/blog/134727002 - Date: 2023-12-01 - Tags: #AI, #EdgeComputing The power grid is among the most complex and geographically dispersed critical infrastructures in the world. Ensuring safety across generation, transmission, substation, distribution, and retail electricity stages demands real-time monitoring at a scale that human inspectors alone cannot reliably achieve. This post covers how Yingma Technology's edge-AI hardware-software integrated solution addresses that challenge across six concrete power-industry scenarios, using on-device computer vision deployed directly at substations, transmission corridors, and perimeter fences. ## Why Edge AI for Power Infrastructure Power facilities operate in remote locations with unreliable or high-latency network connections. Sending raw video streams to a central cloud for analysis introduces unacceptable latency for safety-critical events such as perimeter intrusion or a worker without a hard hat approaching live equipment. Edge computing boxes that run inference locally eliminate the round-trip and al --- ## AI Edge Box + AI Algorithm Integrated Solution for Smart City Management - URL: https://intl.sienovo.cn/blog/134726927 - Date: 2023-12-01 - Tags: #AI, #EdgeComputing Smart cities generate enormous volumes of visual data from surveillance cameras installed across streets, parks, waterways, and public spaces. Acting on that data in real time — without shipping every frame to a distant cloud — requires purpose-built AI inference hardware deployed at the edge. Sienovo's AI Edge Box + AI Algorithm integrated solution addresses this need for urban management departments by packaging a ruggedized edge computing platform with a pre-trained vision pipeline that covers more than a dozen distinct urban violation and non-compliance scenarios. The result is a system that can automatically flag incidents as they happen, reduce the burden on human inspectors, and close the feedback loop with the responsible parties far faster than traditional manual patrol workflows. ## Why Edge AI for Urban Management Cloud-based video analytics introduce unavoidable round-trip latency and depend on a stable, high-bandwidth uplink from every camera node. In dense urban deploym --- ## AI Edge Computing Box Based on Rockchip RK3588 + Cambricon | 38TOPS INT8 Computing Power for Intelligent Security, Smart Construction Sites, Smart City Management, and Smart Gas Stations - URL: https://intl.sienovo.cn/blog/134726568 - Date: 2023-12-01 - Tags: #AI, #EdgeComputing ## Edge Computing Box Rockchip RK3588 + Cambricon | 38TOPS INT8 Computing Power ● Features a Big-Little CPU architecture with quad-core A76 and quad-core A55, CPU frequency up to 2.4GHz, equipped with 1MB L2 Cache and 3MB L3 Cache for enhanced CPU performance. ● High-performance quad-core Mali-G610 GPU, supports at least dual 4K UI displays, capable of smoothly running complex graphics processing tasks. ● Expandable with 4G/Wi-Fi 6/BT wireless communication modules, facilitating edge computing deployment. ● Supports mSATA SSD expansion for large-scale data storage needs. ● Supports 1–2 AI acceleration modules, with up to 32TOPS@INT8 expandable AI computing power, achieving a maximum combined computing power of 38TOPS@INT8, delivering exceptional AI performance. ● Compatible with mainstream deep learning frameworks including TensorFlow, Caffe, PyTorch, TFLite, and ONNX; supports network models such as face detection, tracking, recognition, posture estimation, and hard hat detect --- ## RV1126-based Edge AI Computing Box for New Retail, Smart Urban Management, Smart Security, and Smart Classroom - URL: https://intl.sienovo.cn/blog/134726337 - Date: 2023-12-01 - Tags: #AI ## Edge Computing Box Rockchip RV1126 | 2.0TOPS INT8/INT16 ● Integrated NPU with computing power up to 2.0TOPs@INT8/INT16. ● Supports H.264/H.265/MJPEG video encoding and decoding; supports multi-level video quality configuration and encoding complexity settings. ● Encoding and Decoding Performance     3840 x 2160@30 fps + 1080p@30 fps encoding     3840 x 2160@30 encoding + 3840 x 2160@30 fps decoding. ● Maximum decoding 4096x2304@30fps.                       ● Supports a series of deep learning frameworks such as TensorFlow, MXNet, PyTorch, and Caffe, meeting diverse developer needs. ● Rich peripheral interfaces: Ethernet, HDMI in/out, RS232, RS485, Line in/out, Wi-Fi, TF, etc. The XM-RV1126 Edge Computing Box is a deep intelligent edge computing device designed by Xinmai Technology based on the RV1126. The core RV1126 adopts a highly integrated precision design architecture, based on a quad-core ARM Cortex-A7@1.5GHz & RISC-V architecture. The entire device features lightwe --- ## Essential Guide to Powering NI Automated Test Systems: Demystifying Power Planning - URL: https://intl.sienovo.cn/blog/134672137 - Date: 2023-11-28 - Tags: #NI Just as you need to plug in a computer before use, selecting the right power supply is a primary concern for automated test systems—albeit a more complex one. For example, geographical location must be considered, as public power grids in different countries or regions deliver varying line power levels. Practical experience in power layout and equipment selection includes adding approximately 20% headroom when powering the system to accommodate peak power usage and future expansion of the test system. As outlined in *Power Planning for Automated Test Systems*, other critical factors include electromagnetic interference (EMI) or line filtering, power budgeting, power distribution units (PDUs), and power status monitoring. _ps: Download the white paper at the end of this article._ **Connecting Power to the System** The best practice for powering an ATE system is to use a power inlet panel or line input panel. This isolates internal power wiring from the point where main voltage is --- ## [Domestic Virtual Instrument] 24-bit Data Acquisition Card Based on ARM+FPGA - URL: https://intl.sienovo.cn/blog/134664420 - Date: 2023-11-28 - Tags: #DAQCard ## A Domestically Developed 24-Bit DAQ Card Built on ARM + FPGA For engineers working in vibration analysis, structural health monitoring, and acoustic measurement, the choice of data acquisition hardware directly determines how much confidence you can place in your results. This post introduces a domestically developed, portable 24-bit data acquisition card built around an ARM + FPGA architecture — covering its core technical specifications, design philosophy, and the software ecosystem that ships with it. ## Core Acquisition Specifications At the heart of the card is a **24-bit Delta-Sigma ADC** operating in synchronous acquisition mode. Delta-Sigma converters are the standard choice for precision low-frequency measurement: oversampling and noise shaping push quantization noise out of the band of interest, delivering the high dynamic range that vibration and acoustic applications demand. Hardware anti-aliasing filters sit ahead of the ADC, eliminating the need to rely solely on di --- ## High-End Intelligent Terminal Robot Motherboard Based on RK3588 - URL: https://intl.sienovo.cn/blog/134495670 - Date: 2023-11-19 - Tags: #Robotics 1. Compact Board Design This motherboard features a compact form factor measuring only 125\*85mm, making it smaller and more space-efficient, perfectly suitable for various high-end intelligent self-service terminals; ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134495670/01_fab340c0a8af5d8acccb1263e1ccc7b5.png) 2. Octa-Core High-Performance Processor Powered by the RK3588S octa-core 64-bit processor built on 8nm LP process technology, with a maximum clock speed of up to 2.4GHz. It runs Android 12.0 and integrates an ARM Mali-G610 MP4 quad-core GPU along with a built-in AI accelerator NPU delivering 6TOPS of computing power, offering exceptional performance; 3. Multiple Display Interfaces with Triple Independent Displays Supports LVDS/eDP/MIPI output: LVDS displays support up to 1920\*1200 resolution, eDP up to 3840\*2160, and MIPI up to 1920\*1200. Triple independent display output is supported; ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134 --- ## 8K Multi-Screen Android Smart Network Set-Top Box Based on RK3588 - URL: https://intl.sienovo.cn/blog/134494735 - Date: 2023-11-19 - Tags: #RK ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134494735/01_4ae3f835c95b0d8789b6707ea88be0de.png) Rockchip's RK3588 has become the reference silicon for high-end Android TV and industrial media boxes, and this 8K smart network set-top box shows why. Built around the RK3588 chip platform and shipping with a clean Android 12 OS, the unit targets OEM and ODM buyers in export markets who need a powerful, flexible media appliance they can brand and configure to spec. ## Why RK3588? The RK3588 is an octa-core Rockchip SoC that combines four ARM Cortex-A76 performance cores with four ARM Cortex-A55 efficiency cores, a Mali-G610 GPU, and an integrated NPU. Its hardware video engine supports decode up to 8K at 60 fps across H.265, VP9, AV1, and other modern codecs, which is what makes 8K multi-screen output practical rather than aspirational on this platform. The chip also has broad OS support in the open-source community, which explains why this box can offer Android 12 as the --- ## RK3568+Codesys+Xenomai Real-time SoftPLC Motion Control Solution - URL: https://intl.sienovo.cn/blog/134325102 - Date: 2023-11-17 - Tags: #codesys ## ****CODESYS Software Architecture****      **CODESYS software is divided into a three-layer architecture, as shown in the diagram below:** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134325102/01_a5ca0ea1d334279d422f6676294c5952.jpeg) **1. Development Layer**       The CODESYS Development System (with comprehensive online and offline programming capabilities), compilers and their accessory components, visualization interface programming components, etc., are provided. Additionally, optional motion control modules are available to users, making its functions more complete and powerful. IEC 61131-3 Editor. CODESYS provides all five programming languages defined by IEC 61131-3: such as Structured Text (ST), Sequential Function Chart (SFC), Function Block Diagram (FBD), Ladder Diagram (LD), and Instruction List (IL). Furthermore, it also supports the Continuous Function Chart (CFC) programming language. Compiler: Responsible for converting applications in CODESYS --- ## 基于RK3568新零售智能售货柜解决方案 - URL: https://intl.sienovo.cn/blog/134387626 - Date: 2023-11-13 - Tags: #Retail --- Title: RK3568-Based Smart Vending Cabinet Solution for New Retail Content: **I Solution Overview** **Smart Vending Cabinet Solution for New Retail:** In the field of unmanned retail, vending machines remain a highlight alongside shelf-style无人retail solutions. However, many still believe that traditional vending machines are outdated and unlikely to become rising stars in the new retail landscape. With the widespread adoption of mobile and facial recognition payments, and continuous innovation in smart vending technology, unmanned shelves and vending machines have become increasingly user-friendly, offering richer product selections, more affordable pricing, and enhanced intelligence. As a result, consumers have gradually evolved from merely accepting smart retail to actively using and ultimately relying on it. Today, numerous mature new retail business models have emerged in the market. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134387626/01_8b4c619817c6028a --- ## Pre-Shift Alcohol Tester - URL: https://intl.sienovo.cn/blog/134387528 - Date: 2023-11-13 - Tags: #ComputerVision, #AI, #DeepLearning Pre-Shift Alcohol Tester: A triple-function intelligent device integrating "alcohol detection + smart temperature measurement + facial attendance". Alcohol Detection Function: Utilizes an electrochemical sensor to detect alcohol concentration, featuring blow interruption and airflow detection, anti-cheating design during blowing, breath temperature and inhalation detection; response time ≤20 milliseconds; measurement range: 0–2.0 g/L; indication error: minimal deviation within the alcohol concentration range. The breath-based detection can qualitatively determine alcohol consumption and its level, offering high sensitivity, accuracy, and stable performance, effectively preventing work or driving under the influence. Test data is uploaded and printed in real time. Smart Temperature Measurement Function: Non-contact body temperature detection using infrared thermal imaging; maximum detection distance up to 1 meter, optimal distance at 0.5 meters; temperature measurement speed <1 secon --- ## 基于RK3568的跑步机方案 - URL: https://intl.sienovo.cn/blog/134387494 - Date: 2023-11-13 - Tags: #RK --- Title: Treadmill Solution Based on RK3568 Content: **I  Solution Overview** **1. Origin of the Treadmill** Treadmills are common fitness equipment found in homes and gyms, and are currently the simplest type of home fitness device, making them the ideal choice for household workouts. The world's first home treadmill was invented in 1965 by Dontrick in Northern Europe, Finland. The designer adapted the concept based on conveyor belt principles. **2. Evolution of the Treadmill** The world's first heart rate training treadmill was introduced in 1969. \[1\] Integrating heart rate monitoring into treadmills was a groundbreaking innovation that set the direction for the future development of fitness equipment worldwide. Heart rate during exercise is the best indicator of the body's condition. In Europe and the United States, monitoring heart rate to scientifically control exercise intensity has become a widely adopted practice. Heart rate-based training has become a key fitness me --- ## Indoor Smart Fitness Mirror Solution Based on RK3399 - URL: https://intl.sienovo.cn/blog/134387450 - Date: 2023-11-13 - Tags: #RK **I. Background of the Solution** **1. The Rise of Fitness Mirrors** In 2020, the global pandemic led to widespread lockdowns, making staying at home a key preventive measure. As a result, home workouts surged in popularity, driving demand for home fitness equipment—among which the aesthetically pleasing and multi-functional smart fitness mirror stood out. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134387450/01_bfd67280147d3567c3ad8a12694439ed.png) **II. Solution Overview** **1. Introduction to the Fitness Mirror Solution** Our fitness mirror solution is built on a hardware mainboard powered by the RK3399 hexa-core chipset. It features a high-performance A72+A53 hexa-core processor with a maximum clock speed of 1.8GHz and a Mali-T860 GPU. On the software side, we've integrated "personalized" fitness programs including dance, aerobic exercise, boxing, running, and martial arts; multimedia features such as music playlists, online challenges, workout leaderboards --- ## Experimental Study on Dynamic Characteristics of Nuclear Reactor Core Components - URL: https://intl.sienovo.cn/blog/134233904 - Date: 2023-11-05 - Tags: #VirtualInstrument u  **Overview of Nuclear Reactor Testing** Reactors are one of the core components of the nuclear power industry. In-core components, such as reactor core fuel assemblies, can experience severe vibration induced by coolant flow impact, leading to unstable flow channels for test specimens within the reactor core. To ensure the safe operation of reactors, and in accordance with national nuclear safety regulations, it is necessary to conduct vibration characteristic tests on in-core components subjected to coolant impact. These tests aim to determine if there is a critical flow velocity within a certain flow rate range that could lead to component instability for the system and its parts. Due to the complexity of reactor core components and flow fields, it is currently very difficult to reliably calculate flow field distribution and pressure drop theoretically, and to solve for pulsating pressure loads acting on in-core components. This makes it impossible to study their actual effects --- ## SPM Vibration Monitoring System for an Offshore Platform Using Domestic Instruments - URL: https://intl.sienovo.cn/blog/134233850 - Date: 2023-11-05 - Tags: #VibrationMonitoring **Abstract:** Using distributed data acquisition units and a cloud-based intelligent monitoring system, single point SPM (steel structure with bearings above and below water) vibration monitoring for an offshore Floating Production Storage and Offloading (FPSO) vessel was achieved. The system has successfully withstood the test of variable climatic environments, including high humidity and large temperature fluctuations. **Keywords:** Offshore platform, Vibration monitoring, Environment An offshore Floating Production Storage and Offloading (FPSO) vessel is moored to a single point SPM (steel structure with bearings above and below water). The FPSO rotates around the single point with the current, at a very slow speed. The FPSO rotates around the single point via Mooring chains and a Yoke. The rotation speed is related to tides and sea conditions, and the direction of rotation changes with the current. The inner turret of the single point is connected to the seabed and does not rota --- ## Industrial Android Motherboard - Electronic Class Signage / Face Recognition Access Control / Indoor Intercom Access Control Solution Based on RK3568/3288/3588 (Part Two) - URL: https://intl.sienovo.cn/blog/134228140 - Date: 2023-11-05 - Tags: #RK ## Smart Class Card Display The smart electronic class card display can show comprehensive basic class information in real-time on its homepage, including weather, class name, timetable, duty roster, etc., and publish school and class announcements. Students can swipe their cards to automatically log into the system to provide classroom feedback. Teachers and parents can promptly access teaching feedback, thereby opening up an interactive channel among schools, teachers, and students. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134228140/01_f48dc8dda9a72a37c52d4013c5e29de0.png) ## Face Recognition Access Control Smart face recognition access control has become one of the hottest AI applications today. It maximizes the accuracy of verification results, effectively ensuring secure and efficient passage for visitors and internal staff, enhancing security levels and standardizing management. This significantly reduces the workload for management personnel, and visitor --- ## Industrial Android Motherboards – AI-Powered Smart Digital Signage/Vending Machines/POS Systems Based on RK3568/3288/3588 (Part 3) - URL: https://intl.sienovo.cn/blog/134228063 - Date: 2023-11-05 - Tags: #CLanguage ## Digital Signage Smart networked digital signage allows multimedia content such as audio, video, images, documents, and web pages to be freely laid out and published as programs to endpoint devices via the internet. Different endpoints can be centrally managed and uniformly updated. Depending on whether the application scenario is centralized or distributed, either LAN-based management or cloud server management can be adopted. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134228063/01_c6f16d7850b3cbbd13d2e48bdc147701.png) ## Vending Machines With the rise of IoT, big data, and artificial intelligence, smart devices are now deeply integrated into people's daily lives. Intelligent vending machines serve as a key hub connecting online consumption with offline experiences. Combined with customized operation models and big data collection and analysis, they enable traditional retail vendors in niche markets to easily transform their business roles. ![](https://pub-04 --- ## 行业安卓主板-基于RK3568/3288/3588的AI视觉秤/云相框/点餐机/明厨亮灶行业解决方案（一） - URL: https://intl.sienovo.cn/blog/134228032 - Date: 2023-11-05 - Tags: #AI, #Scale Industrial Android motherboards built on Rockchip's RK3568, RK3288, and RK3588 SoCs have become a versatile platform for edge-AI applications across retail, hospitality, and food-safety industries. This post walks through four representative solution categories — AI vision scales, cloud digital photo frames, self-ordering kiosks, and transparent kitchen systems — and explains what the hardware enables in each case. ## AI Vision Scale Fresh-produce retail has always faced a labour-intensive bottleneck at the weighing counter. Customers queue, staff must manually look up produce codes, and mis-identification leads to pricing errors. AI vision scales address all three pain points at once. The single-screen AI scale described here integrates an independent NPU directly on the SoC, delivering up to **0.8 TOPS** of dedicated neural-network compute. Because inference runs on-chip rather than round-tripping to a cloud server, recognition latency is kept low enough to match the speed of plac --- ## RK3568-based New Energy Storage Energy Management System (EMS) - URL: https://intl.sienovo.cn/blog/134211966 - Date: 2023-11-03 - Tags: #DomesticReplacement, #EnergyStorage, #EMS ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134211966/01_8b104ffc99e5a414db75ec5e16f3bda3.jpeg) A New Energy Storage Energy Management System (EMS) is a system based on modern technology, designed to manage and optimize the energy usage of new energy storage devices. The system ensures efficient energy utilization and sustainable development by monitoring, dispatching, and controlling new energy storage equipment. This article will introduce the principles, functions, and future development of new energy storage energy management systems from various perspectives. I. Principles of New Energy Storage Energy Management Systems New energy storage energy management systems are integrated systems based on technologies such as the Internet of Things (IoT), big data, and cloud computing. By connecting various new energy storage devices and smart grids, it achieves real-time energy monitoring, analysis, and dispatch. The system primarily consists of the following compon --- ## NI-9236 Domestic Product: 10 kS/s/ch, 350 Ω Quarter-Bridge Strain Gauge, 8-Channel C Series Strain/Bridge Input Module - URL: https://intl.sienovo.cn/blog/134167557 - Date: 2023-11-01 - Tags: #CLanguage, #ProgrammingLanguage ### 10 kS/s/ch, 350 Ω Quarter-Bridge Strain Gauge, 8-Channel C Series Strain/Bridge Input Module The NI‑9236 can simultaneously measure dynamic strain on all channels, enabling high-speed synchronous measurements. This feature is crucial for applications requiring comparison of multiple channels at specific moments, such as impact testing.\\n\\nThe NI‑9236 features built-in voltage excitation for quarter-bridge sensors. It also offers 60 VDC isolation and 1,000 Vrms transient isolation, providing high common-mode noise rejection and enhanced safety. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134167557/01_b8c34e2c5a480f7fc61b825a76b0bf7a.png) III. Product Applications The XM-USB-4431 is a USB 2.0 bus-based data acquisition card that can be directly connected to a computer's USB port to form data acquisition, waveform analysis, and processing systems in various fields such as laboratories and product quality inspection centers. It can also be used to build industria --- ## NI‑9237 50 kS/s/ch, Bridge Analog Input, 4-Channel C Series Strain/Bridge Input Module - URL: https://intl.sienovo.cn/blog/134167518 - Date: 2023-11-01 - Tags: #CLanguage, #Networking, #ProgrammingLanguage ### 50 kS/s/ch, Bridge Analog Input, 4-Channel C Series Strain/Bridge Input Module The NI‑9237 provides all signal conditioning functions to power and measure up to four bridge-based sensors. This module offers strain or load measurements with zero phase delay between channels. It also features 60 VDC isolation and 1,000 Vrms transient isolation, providing high common-mode noise rejection and enhanced safety. The NI‑9237 can be programmed for use with half-bridge and full-bridge sensors that have built-in excitation. Four RJ50 connectors allow direct connection to most torque sensors or load cells, enabling custom cable solutions with minimal tools. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134167518/01_8d907fcf51dfb02a1b55d5ee33b113a8.png) III. Product Applications The XM-USB-4431 is a USB2.0 bus-based data acquisition card that can be directly connected to a computer's USB port to form data acquisition, waveform analysis, and processing systems in various field --- ## NI-9219 100 S/s/ch Domestically Produced 4-Channel C Series General-Purpose Multi-Function Analog Input Module, Supports Various Sensors - URL: https://intl.sienovo.cn/blog/134167375 - Date: 2023-11-01 - Tags: #CLanguage, #ProgrammingLanguage, #NI9219 ### 100 S/s/ch, 4-Channel C Series General-Purpose Analog Input Module The NI-9219 is designed for multi-function testing. The NI-9219 can be used to measure signals from various sensors (such as strain gauges, resistance temperature detectors (RTDs), thermocouples, load cells, and other active sensors), as well as perform quarter-bridge, half-bridge, and full-bridge current measurements, and features built-in voltage and current excitation. You can select different measurement types independently on each channel. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134167375/01_28018b9203560b1df01700546b8844e2.png) ### III. Product Applications The XM-USB-4431 is a data acquisition card based on the USB 2.0 bus, which can be directly connected to a computer's USB port, forming data acquisition, waveform analysis, and processing systems for various fields such as laboratories and product quality inspection centers. It can also form industrial production process monitoring s --- ## NI USB9218 Domestic Counterpart: 51.2 kS/s/ch, 2-Channel C Series Universal Analog Input Module - URL: https://intl.sienovo.cn/blog/134167176 - Date: 2023-11-01 - Tags: #CLanguage, #ProgrammingLanguage, #NI, #DAQCard ### 51.2 kS/s/ch, 2-Channel C Series Universal Analog Input Module The NI‑9218 is designed for multi-purpose measurements. It provides built-in support for accelerometers, powered sensors, full-bridge and voltage measurements, as well as quarter-bridge, half-bridge, 60V, and current measurements using adapters tailored for specific measurements. Each channel is individually selectable, allowing users to perform different measurements on each channel. The NI‑9218 is an ideal choice for developing universal test systems required for automotive, off-highway, and data logging applications. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134167176/01_90ad29fac3d90d4597356a81956112d0.png) III. Product Applications The XM-USB-4431 is a data acquisition card based on the USB2.0 bus, which can be directly connected to a computer's USB port to form data acquisition, waveform analysis, and processing systems in various fields such as laboratories and product quality inspection ce --- ## Domestic Alternative 4-Channel Synchronous Acquisition Card Solution Comparable to NI USB-4431 - URL: https://intl.sienovo.cn/blog/134164061 - Date: 2023-11-01 - Tags: #NI, #USB4431, #DomesticReplacement ### 102.4 kS/s, 100 dB, 0.8 Hz AC/DC Coupled, 4-Input/Single-Output Sound and Vibration Device The USB-4431 is designed specifically for sound and vibration applications. The input channels integrate Integrated Electronic Piezoelectric (IEPE) signal conditioning for accelerometers and microphones. The four input channels of the USB-4431 can synchronously digitize input signals. The analog output (AO) channel is ideal for excitation-response testing and can be synchronized with the AI channels. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134164061/01_e3233191a496925a7e36525be91db933.png) **III. Product Applications** The XM-USB-4431 is a data acquisition card based on the USB2.0 bus, which can be directly connected to a computer's USB port to form data acquisition, waveform analysis, and processing systems in various fields such as laboratories and product quality inspection centers. It can also form industrial production process monitoring systems. Its main applic --- ## 基于RK3588/RK3568/RK3288的全国产储能“大脑”——EMS管理系统 - URL: https://intl.sienovo.cn/blog/134104351 - Date: 2023-10-29 - Tags: #EMS, #DomesticEnergyStorage, #EnergyStorage #### What is EMS (Energy Management System)? When it comes to energy storage, the public's first thought is usually batteries. Their quality affects important aspects such as energy conversion efficiency, system lifespan, and safety. However, for energy storage to function as a valuable system, the core component acting as its "brain" — the EMS (Energy Management System) — plays an equally crucial role. On one hand, the EMS is directly responsible for the control strategies of the energy storage system. These control strategies, in turn, influence the battery degradation rate and cycle life within the system, thereby determining the economic viability of energy storage. On the other hand, it also monitors faults and anomalies during system operation, playing a vital role in promptly protecting equipment and ensuring safety. If the energy storage system is likened to the human body, then the EMS is the human brain and mind. The brain and mind determine a person's occupation, regulate --- ## Energy Management System (EMS): The Intelligent Brain of the New Energy Storage Industry - URL: https://intl.sienovo.cn/blog/134104142 - Date: 2023-10-29 - Tags: #AI Introduction: The Energy Management System (EMS) is a crucial intelligent technology in the new energy storage industry. Its role is similar to a brain, capable of monitoring, controlling, and optimizing the operation of energy systems, providing efficient and stable energy management for energy storage facilities. This article will introduce the basic concepts, functions, and applications of Energy Management Systems. I. What is an Energy Management System (EMS)? An Energy Management System (EMS) is an intelligent system integrating both hardware and software, used for monitoring, controlling, and optimizing energy flow and consumption within energy systems. Based on data acquisition, analysis, and decision support technologies, it can real-time monitor the operating status of energy equipment, energy consumption, and environmental conditions, thereby achieving efficient management and optimization of energy. II. Functions of Energy Management Systems 1. Monitoring and Data Acqui --- ## Cost-Effective All-Domestic RK3568-Based EMS Energy Storage Solution (Part 2) Design Scheme - URL: https://intl.sienovo.cn/blog/134104001 - Date: 2023-10-29 - Tags: #EMS, #EnergyStorage **Table of Contents** [Revision History](#_Toc147746227) [1. Product Introduction](#_Toc147746228) [1.1. What is](#_Toc147746229) XM3568-EP [1.2. Product Features](#_Toc147746230) [1.3. Enclosure Dimensions](#_Toc147746231) [1.4. Enclosure Appearance](#_Toc147746232) [1.5. Specifications](#_Toc147746233) [2. Device Usage Introduction](#_Toc147746234) [2.1. Download Required Drivers and Debugging Tools](#_Toc147746235) [2.2. Starting the Gateway](#_Toc147746236) [2.3. How to Use the DEBUG Serial Port](#_Toc147746237) [2.4. LED Indicator Description](#_Toc147746238) [3. Using the Linux System](#_Toc147746239) [3.1. Distribution Type and Kernel Version](#_Toc147746240) [3.2. System Pre-installed Software](#_Toc147746241) [3.3. System Default Login Accounts and Passwords](#_Toc147746242) [3.4. Network Connection Configuration and Function Test](#_Toc147746243) [3.5. HDMI Terminal](#_Toc147746244) [3.6. (DI) Digital Input](#_Toc147746245) [3.7. (DO) Digital Output](#_To --- ## Cost-effective All-domestic EMS Energy Storage Solution Based on RK3568 (Part 1) Overview - URL: https://intl.sienovo.cn/blog/134103768 - Date: 2023-10-29 - Tags: #EMS, #DomesticEnergyStorage **Energy Storage Industry Chain Framework** The energy storage industry chain can be divided into upstream "raw materials and production equipment," midstream "energy storage systems," and downstream "energy storage application scenarios and after-sales services." ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/134103768/01_54c4ed00b3db094c508d57a6b1828d4a.png) Figure 1 Energy Storage Industry Chain Framework Diagram The "energy storage battery system" in the midstream of the industry chain mainly comprises four parts: "Energy Management System (EMS)," "Battery Management System (BMS)," "Energy Storage Converter (PCS)," and "battery pack." The battery pack feeds status information back to the Battery Management System (BMS). The BMS shares this information with the Energy Management System (EMS) and the Energy Storage Converter (PCS). The EMS then sends control information to the PCS and BMS based on optimization and scheduling decisions, controlling individual cells/ --- ## Design of a High-Precision Data Acquisition System Based on ARM+FPGA+AD - URL: https://intl.sienovo.cn/blog/134103463 - Date: 2023-10-29 - Tags: #microsoft With the rapid development of fields such as image processing, industrial control, and wireless communication, the demands for data acquisition systems' performance, including speed and precision, are continuously increasing. These requirements pose new challenges for the design and implementation of data acquisition systems. Currently, data acquisition system design solutions are generally categorized as follows: 1) Primarily based on a single microprocessor control chip and an A/D converter. This design is simple, and for applications with low performance requirements, microprocessors with integrated A/D converters can even be used to reduce costs [1]. 2) Using a general-purpose computer configured with a data acquisition card [2]. This typically requires developing computer-side applications capable of complex calculations. However, different acquisition cards require different drivers, and if requirements change and the acquisition card needs to be replaced, the corresponding appli --- ## Development and Experimental Verification of a Multi-type Synchronous Signal Acquisition Instrument Based on ARM+FPGA+AD Platform (Part 1): Host Computer Software Design - URL: https://intl.sienovo.cn/blog/134048616 - Date: 2023-10-26 - Tags: #FPGADev Host Computer Software Design for the Acquisition Instrument This chapter develops a C#-based host computer software for operating various functions of the multi-type synchronous signal acquisition instrument. Starting from the data transmission requirements of the acquisition instrument, the host computer uses the Ethernet UDP protocol to achieve data interaction with the acquisition instrument, including sending control and configuration information to the acquisition instrument, receiving AD data transmitted from the acquisition instrument, and then parsing the data. Following user-oriented principles, a graphical user interface (GUI) is developed to implement performance configuration, data visualization, and local storage functions. 4.1 Overall Design The multi-type synchronous signal acquisition instrument developed in this paper can configure the AD chip based on configuration information received via the UDP protocol, and send synchronously acquired AD chip data via the UDP --- ## Development and Experimental Verification of a Multi-type Synchronous Signal Acquisition Instrument Based on ARM+FPGA+AD Platform (Part Two) Overall Board Design - URL: https://intl.sienovo.cn/blog/134048382 - Date: 2023-10-26 - Tags: #FPGADev 2.2 Overall Board Design This chapter develops a multi-type sensor signal synchronous conditioning board based on AD7193+RJ45, as shown in Figure 2.4. It is responsible for converting analog electrical signals from sensors into digital signals for acquisition by the data acquisition system. It achieves the functions of free switching of sensor signal types in a single channel and synchronous acquisition of multiple types of sensor signals (including bridge circuit signals, IEPE sensor signals, current, and voltage, a total of four types of sensor signals). This module has the following functions: (1) Conditions bridge circuit signals, IEPE sensor signals, voltage, and current sensor signals, converting these four types of sensor signals into 0~2.5V voltage signals; (2) Free switching of the acquired sensor signal type within a single channel; (3) Synchronous acquisition of signals from each channel; (4) Possesses hardware-level filtering and noise reduction functions. ![](https --- ## Development and Experimental Verification of a Multi-Type Synchronous Signal Acquisition Instrument Based on an ARM+FPGA+AD Platform (Part 1) - URL: https://intl.sienovo.cn/blog/134048028 - Date: 2023-10-26 - Tags: #FPGADev Real-time monitoring and diagnosis of the operational status of engineering structures, timely detection of structural damage, assessment of their safety performance, prediction of performance degradation trends and service life, and proposing improvement measures are of paramount importance for enhancing the efficiency of engineering structures and safeguarding people's lives and property. This has become an increasingly urgent technical requirement for engineering structures [2]. Structural Health Monitoring (SHM) systems can collect various data reflecting the operational status of structures, use structural health diagnosis methods to real-time determine the location and extent of structural damage, assess their safety performance, predict performance degradation trends, and provide early warnings for dangerous situations. They are an effective means to ensure the safety of major engineering structures throughout their entire lifecycle, from construction and operation to demolitio --- ## Validation and Production Test Automation Based on Domestic ARM+FPGA+AD - URL: https://intl.sienovo.cn/blog/134023559 - Date: 2023-10-24 - Tags: #ProgrammerDay TestStand is a test execution software that helps engineers accelerate system development and deployment in validation and production stages. ### Validation and Production Test Automation TestStand leverages its features to automate, accelerate, and standardize the entire test process across all user test systems: * Call and execute tests written in LabVIEW, Python, C/C++, or .NET * Execute complex tasks such as parallel testing, scanning, looping, and synchronization * Create custom operator interfaces and powerful tools for deployment and debugging * Track devices, create automated reports, and store results to local or network databases #### What are the applications of TestStand? Develop tests and deploy them to systems. Standardize and streamline workflows. Learn how TestStand helps test engineers overcome time-to-market limitations by improving efficiency: #### What are the applications of TestStand? Develop tests and deploy them to systems. Standardize and stream --- ## Multi-Channel Precision Data Acquisition System Based on ARM+FPGA+AD - URL: https://intl.sienovo.cn/blog/134023242 - Date: 2023-10-24 - Tags: #ProgrammerDay The XM series is a data acquisition instrument designed to meet essential requirements such as "simple operation, portability, and versatility for various measurement needs." With an ultra-compact, lightweight palm-sized design, it supports eight types of measurement modules and enables multi-channel measurements of up to 576 channels. Additionally, it features a wiring reduction system that significantly cuts down wiring time. Users don't need to worry about wiring duration, wiring errors, or restoration work in the event of cable disconnection. The system also includes helpful setup assistance functions and intuitive icons, enabling even beginners to operate it "effortlessly." Furthermore, power can be selected from AC, DC, or battery options, with a high-capacity lithium-ion battery supporting data acquisition for up to 800 minutes. Data transmission via a wireless LAN module minimizes cabling constraints at measurement sites. ### Product Features #### Capable of measuring tempera --- ## NI 9234 4-Channel, ±5 V, 24-bit Software-Selectable IEPE and AC/DC Analog Input Module for Vibration Testing: A Domestic Alternative - URL: https://intl.sienovo.cn/blog/133918917 - Date: 2023-10-23 - Tags: #AI NI's automated test and measurement systems empower you to break through barriers and make the impossible possible. Let us work together to select the optimal combination of hardware, software, and services, fully equipping you to achieve extraordinary results. Purchasing NI products or services is not merely a one-time transaction. Should you have any questions or require support, our industry experts are always available to assist you. We want to understand what is preventing you from achieving your goals. You can always discuss your challenges with a solutions expert. No matter the situation, we are always by your side. We will accompany you throughout the entire application lifecycle, providing service and support. Growing energy demands and increasing interest in sourcing various energy types make stable production and distribution more critical than ever. NI solutions help ensure equipment quality and output consistency throughout the entire process. Ensure Quality NI's unp --- ## Accurate Measurements with DAQ: A More Reliable Basis for Decision-Making - URL: https://intl.sienovo.cn/blog/133916943 - Date: 2023-10-18 - Tags: #EmbeddedHardware, #AI, #FPGADev ## Accurate Measurements with DAQ: A More Reliable Basis for Decision-Making In industrial and embedded systems, accurate measurements are crucial for making informed decisions. However, setting up and configuring measurement hardware can be a complex and time-consuming process. DAQExpress, a powerful tool for data acquisition and analysis, aims to simplify this process and provide a more reliable basis for decision-making. DAQExpress provides an interactive analysis panel that allows users to easily configure compatible measurement hardware and view analyzed measurement data. This eliminates the need for programming and enables users to capture measurement data instantly. Additionally, users can create a basic LabVIEW VI in the DAQExpress editor to perform basic automation tasks. ### Key Benefits #### Simplified System Configuration and Setup Once plugged in, DAQExpress allows users to quickly and clearly access all measurement data supported by the DAQ device. This streamlined s --- ## Analysis of the Market Outlook for the Data Acquisition Instrument Industry in 2023 - URL: https://intl.sienovo.cn/blog/133916832 - Date: 2023-10-18 - Tags: #BigData, #AI Analysis of the Market Outlook for the Data Acquisition Instrument Industry in 2023 The data acquisition instrument industry refers to instrument equipment used for collecting, inputting, converting, processing, storing, and outputting data from various physical, chemical, optical, and electromagnetic quantities. With the rapid development of industrialization and informatization, the data acquisition instrument industry has experienced significant growth. This article will analyze the market outlook for the data acquisition instrument industry from aspects such as industry development overview, market demand, competitive landscape, opportunities, and challenges. I. Industry Development Overview The data acquisition instrument industry is a high-tech industry, with its main classifications including sensors, precision instruments, automation instruments, and testing equipment. As a critical technical equipment, data acquisition instruments can be widely applied in manufacturing, energ --- ## ARM + FPGA GPIB IP Core Implementation - URL: https://intl.sienovo.cn/blog/133843089 - Date: 2023-10-15 - Tags: #FPGADev, #ARMDev Currently, Tektronix and Agilent, both US companies, are leaders in data generator technology. Agilent's family of benchtop pulse/data generators offers a maximum clock frequency of 3GHz (timing generator). The E81200 data generator achieves a data rate of 660Mb/s with 8 channels, meaning it can produce waveform outputs up to 330MHz. Tektronix's typical benchtop data generator, the Tek DG2020A, has a clock frequency of 200MHz and can produce graphical data output at 100MHz, featuring powerful waveform editing software. Data patterns can be generated using the data pattern editor, which includes capabilities such as graphical editing, timing waveform sequence combination editing, and table editing. Some domestic universities and research institutions are dedicated to developing data generators, with some capable of producing 100M programmable digital signals. However, due to shortcomings in product design and manufacturing processes, they have not yet formed commercial data generator --- ## Application of ARM/X86 Industrial PCs in Rail Transit Central Control Room Systems (5) - URL: https://intl.sienovo.cn/blog/133303570 - Date: 2023-09-26 - Tags: #Networking Central Control Room System Monitoring room systems in transportation systems aim to provide optimal communication, security, monitoring, and related technologies, thereby bringing a safe, convenient, comfortable, efficient, and environmentally friendly travel experience to all passengers. Many cities around the world are improving their control room systems, and Xinmai also hopes to contribute its humble efforts. Xinmai's flexible, high-performance professional industrial-grade servers, industrial storage devices with reliable data protection and backup capabilities, and video wall control products supporting 8-40 outputs all provide ideal solutions for system integrators. Central Control Room System Products * High-performance server-grade IPCs * Industrial-grade storage with reliable data protection capabilities * Video wall controller solutions * Remote management Application Cases ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133303570/01_1d7379d5031c --- ## Application of ARM/X86 Industrial PCs in Rail Transit Traffic Management Systems (4) - URL: https://intl.sienovo.cn/blog/133296061 - Date: 2023-09-26 - Tags: #AI Traffic Management Systems The Xinmai XM-3000 series is specifically designed for road surveillance applications. With the rapid development of urbanization, the number of vehicles on the road is increasing daily, making road surveillance essential for ensuring urban safety at all times. Thanks to its powerful performance and wide operating temperature support, the XM-3000 series is an ideal choice for traffic management system applications. System Architecture ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133296061/01_1eaa2508959ada88ccfc5f46726eebae.gif) Traffic Management Products * Dedicated for road surveillance * Supports -25~60℃ (-13~140℉) wide-temperature operation * Supports 9~36V wide-range DC voltage input * Easy access to CF/DOM modules * Enhanced vibration resistance testing Application Cases ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133296061/02_85097e3c3fc28b0594b66ed96d0bdb5f.gif) Traffic Management Surveillance Syst --- ## Applications of ARM/X86 Industrial PCs in Rail Transit Train Vehicle Control Systems (3) - URL: https://intl.sienovo.cn/blog/133295929 - Date: 2023-09-26 - Tags: #EmbeddedHardware Train Vehicle Control System Xinmai XM-5000 series is specifically designed for railway vehicle applications, including Passenger Information Systems, Public Address Systems, Surveillance Systems, etc. All XM-5000 series products comply with EN 50155 standard requirements and feature M12 connectors to prevent shock and vibration in railway operating environments. The XM-5000 series and EKI (Ethernet Switch) products provide optimal solutions for railway vehicle systems. System Architecture ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133295929/01_b842ed1b143fa88e4eeea1fa91c983e4.jpeg) Train Vehicle Control System Products * Fully compliant with EN 50155 and EN 45545 standards * Temperature standard: EN 50155 TX (-40~70℃) * Compliant with EN 50121-3-2 EMC test standard * Rugged M12 connectors * DC 24V/ 48V/ 72V/ 110V input * Supports hot-swappable HDD/SSD/CF modules Application Cases ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133295 --- ## ARM/X86 Industrial PC Applications in Rail Transit Ground Control Systems (2) - URL: https://intl.sienovo.cn/blog/133295700 - Date: 2023-09-26 - Tags: #EmbeddedHardware Ground Control System The XM-2000 series can serve as a front-end wayside controller, compliant with the EN50121-4 standard, making it an ideal ground controller product perfectly suited for various systems such as Centralized Traffic Control (CTC) and Automatic Train Control (ATC). Sienovo's robust and reliable systems and platforms enable precise monitoring of ground control applications, thereby enhancing safety in railway operating environments. System Architecture ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133295700/01_e21d3f06bbe1db28c95c43acf29e5886.jpeg) Ground Control System Products * Fully compliant with EN 50121-4 standard * Wide operating temperature range * Supports easy-to-install power modules * Rich serial, Ethernet, and other I/O connectivity Application Cases ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133295700/02_d96df19494861ed8d600dc657157f910.gif) Automatic Train Control System Requirements Automatic Train Con --- ## Application of ARM/X86 Industrial PCs in Rail Transit Station Management Systems (1) - URL: https://intl.sienovo.cn/blog/133295191 - Date: 2023-09-26 - Tags: #Networking, #DevOps, #Server Station Management System A Station Management System (SMS) is an integrated platform, including the Integrated Supervisory Control System (ISCS), Fire Alarm System (FAS), Building Automation System (BAS), and more. Due to its complexity, the SMS requires hardware that is stable and scalable to ensure 24/7 continuous operation. Xinmai's industrial server-grade systems are renowned for their ruggedness and extensive expandability, which often play a crucial role in specialized applications. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133295191/01_9bd0f6327a833c22cb08588593d4cf46.png) Station Management System Products * Rugged Design * Stable, Scalable System for Easy I/O Expansion Application Cases ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133295191/02_ec6b581f297cff0247a4c912058642b4.gif) Integrated Supervisory Control System System Requirements The Integrated Supervisory Control System (ISCS) includes: various levels of railway operati --- ## ARM+FPGA-based ISA Bus / MMи Bus Interface Conversion Design for Rail Transit Applications - URL: https://intl.sienovo.cn/blog/133283165 - Date: 2023-09-25 - Tags: #FPGADev, #ARMDev Rail transit and defense test systems often inherit legacy hardware from multiple national standards — a combination that can make inter-system integration a serious engineering challenge. This article documents the design of an FPGA-based conversion circuit that bridges the American ISA bus and the Russian MMи (MMи) dedicated test bus, enabling a domestic industrial-control computer to communicate reliably with Russian-standard programmable unit modules in a missile test system. The design uses Altera's EPF10K30 FPGA as the core logic engine and has been validated in field deployment. ## Background: Two Incompatible Bus Standards ### ISA Bus The ISA (Industrial Standard Architecture) bus was introduced by IBM in 1984 as an extension of the earlier XT bus standard. Its key electrical and logical characteristics include: - **24-bit address bus, 16-bit data bus** - **11 interrupt levels**: IRQ3–IRQ7, IRQ9–IRQ12, IRQ14–IRQ15 - **7 DMA channels**: DRQ0–DRQ3, DRQ5–DRQ7 - Support for mas --- ## lS1028 + Six-Port TSN Hardware Switching + QNX/Linux Real-time System Solution for Rail Transit Applications - URL: https://intl.sienovo.cn/blog/133278182 - Date: 2023-09-25 - Tags: #LS1028, #TSN, #6PortEthernet ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133278182/01_ba97cbb55257de976cc20d4537a0ec22.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133278182/02_3bc92191710f6f24c8620386fe1ff7ee.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133278182/03_46656bd78bb2db77ac4857cbee4fddcb.png) lS1028 + Six-Port TSN Hardware Switching + QNX/Linux Real-time System Solution for Rail Transit Applications The following are physical examples for rail transit applications: CPU NXP LS1028A Architecture Dual-core Cortex-A72 Clock Speed 1.5GHz RAM 2GB DDR4 ROM 8GB eMMC OS Ubuntu20.04 Power Supply DC 12V Operating Temperature \-40℃~ +80℃ ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133278182/04_2da7785e258aec8f55b62c9f188adeba.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133278182/05_cc5819f377e3e10cc3050419948348dc.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/133278182/06_ba --- ## EtherCAT Bus-Type 4-Axis Motor Control Card Solution - URL: https://intl.sienovo.cn/blog/133013427 - Date: 2023-09-19 - Tags: #MCU, #EmbeddedHardware  **Technical Features**  Supports standard 100M/s full-duplex EtherCAT bus network interface and CoE communication protocol with one input and one output (RJ45 interface), supports automatic mapping of multiple dynamic PDO groups and object dictionaries, supports automatic setting and saving of station ID, and supports motor parameter setting and automatic saving via SDO.  Automatically adapts to mainstream EtherCAT bus master systems or PLC motion controllers on the market, such as TwinCAT, Codesys, Omron, Trio, SOEM, IGH, Acontis, KPA, etc.  Supports standard CiA DS402 protocol, with built-in Cyclic Synchronous Position (CSP mode) and Homing control mode (Homing mode).  Supports control of up to 4 stepper or servo motors, achieving multi-axis synchronous real-time control, offering the highest cost-performance ratio.  Built-in 4-channel 24V digital I/O signal input, using bidirectional optocouplers, supporting NPN and PNP types, for general digital I/O acquisition or left --- ## ARM+Codesys Standard General-Purpose Controller - URL: https://intl.sienovo.cn/blog/132761254 - Date: 2023-09-08 - Tags: #ARMDev Industrial-grade design for the entire unit, communication peripherals with isolated protection, wide voltage power supply design (9~36V DC). Rich communication interfaces to meet control and communication needs for various scenarios. Quad-core industrial-grade processor with high performance, low power consumption, and high reliability. Fanless design with a compact enclosure. Equipped with SylixOS, a large-scale real-time operating system with a 100% independently developed kernel, supporting POSIX interface specifications. It possesses fully independent and controllable intellectual property rights, meeting localization requirements, and features high real-time performance, high reliability, and high security. A convenient and mature programming development suite, RealEvo-IDE, is provided. Supports CODESYS for user secondary development. Supports protocol stacks such as EtherCAT and CANOpen. Supports QT, providing a convenient graphical development environment. Supports hard --- ## ARM + Codesys Runtime Core Board + Baseboard Solution - URL: https://intl.sienovo.cn/blog/132761118 - Date: 2023-09-08 - Tags: #ARMDev Product Features: Rich communication interfaces to meet control and communication requirements in various scenarios. Quad-core industrial-grade processor, offering high performance, low power consumption, and high reliability. Fanless design with a compact enclosure. Equipped with SylixOS, a large-scale real-time operating system with 100% independently developed kernel, supporting POSIX interface specifications. It possesses fully independent and controllable intellectual property rights, meeting localization requirements, and features high real-time performance, high reliability, and high security. It provides the convenient and mature programming development suite RealEvo-IDE. Supports CODESYS, enabling user secondary development. Supports protocol stacks such as EtherCAT, CANOpen. Supports QT, providing a convenient graphical development environment. Supports hard real-time capabilities, with task switching in microseconds and interrupt response in nanoseconds. ![](https:// --- ## ARM/X86 Industrial-Grade Data Acquisition (DAQ) and Control Product Solutions - URL: https://intl.sienovo.cn/blog/132743289 - Date: 2023-09-08 - Tags: #ARMDev I/O devices, including signal conditioning modules, embedded PCI/PCIe cards, portable USB modules, DAQ embedded computers, modular DAQ systems, as well as DAQNavi/SDK software development kit and DAQNavi/MCM equipment condition monitoring software. Industrial I/O products are suitable for various industrial automation applications, from machine automation control and test & measurement to equipment condition monitoring. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/132743289/01_75349b08e768d2bcc066d10086d1109a.png) #### Industrial-Grade Data Acquisition (DAQ) and Control Products * High Speed: Sampling rates up to 125 MS/s * High Accuracy: Resolution up to 26 bits * High Density: Up to 128 channels per card * Synchronization: Synchronous acquisition ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/132743289/02_8e44c3b99f0faedc604b3bce63e2ef66.png) #### Excellent Measurement Quality for Various Industrial Automation Applications * Sound and Vi --- ## Multi-Port Embedded Edge Computing Platform with 11th Gen Intel® Core Processors - URL: https://intl.sienovo.cn/blog/132662288 - Date: 2023-09-04 - Tags: #EdgeComputing, #AI Deploying AI inference and data-intensive workloads at the edge demands hardware that balances raw compute power with rugged reliability. Sienovo's multi-port embedded edge computing platform, built around 11th Gen Intel® Core™ processors, is designed to meet exactly that brief — combining modern x86 processing muscle, a dense I/O complement, and a hardened fanless form factor suitable for factory floors, transportation systems, and unmanned field installations. ## Processor and Memory At the heart of the platform sits an 11th Gen Intel® Core™ processor — available in i7, i5, i3, or Celeron® variants — paired with 8 GB of DDR4 memory running at 3200 Mb/s. Intel's 11th Gen (Tiger Lake) lineup introduced the Willow Cove core architecture, which delivered meaningful single-thread IPC gains over the previous Skylake-derived generations. Crucially for edge AI, the integrated Intel® Iris® Xe graphics on Tiger Lake SKUs support hardware-accelerated inference through OpenVINO, enabling objec --- ## LabVIEW-based Equipment Condition Monitoring and Fault Diagnosis (Part 1): Introduction to NI Hardware and Software - URL: https://intl.sienovo.cn/blog/132444260 - Date: 2023-08-23 - Tags: #labview, #EmbeddedHardware As modern industry gradually moves towards mechatronics, with the continuous improvement in the automation, intelligence, large-scale, and complexity of equipment, the economic losses caused by equipment failures to enterprises are increasing. Therefore, real-time monitoring and fault diagnosis of equipment operating conditions are imperative. It can be said that condition monitoring and fault diagnosis technology for mechanical equipment are important means and key technologies for modern industry to ensure the stability and reliability of production systems, and to improve product quality and production efficiency. This technology is increasingly attracting the attention of researchers engaged in applied basic and engineering technology, and has developed rapidly. **Condition Monitoring**: refers to selecting various sensors to online monitor and record parameters that reflect the current operating status of equipment (such as vibration, temperature, pressure, flow, switching time, --- ## Design of a Data Acquisition and Transmission Subsystem Based on Domestic Anlogic FPGAs - URL: https://intl.sienovo.cn/blog/132367135 - Date: 2023-08-18 - Tags: #DomesticFPGA The structure of the distributed data acquisition system is shown in Figure 2.1, primarily consisting of a sensor network, a data acquisition and transmission subsystem, a data aggregation platform, and a data acquisition system control terminal. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/132367135/01_574a1f164321dbe734633b97b5de5cdb.png) 1) Sensor Network: The sensor network includes multiple sensors and analog-to-digital converter devices. After sampling the signals to be acquired and converting them into digital signals via analog-to-digital conversion, they are sent to the data acquisition and transmission subsystem. 2) Data Acquisition and Transmission Subsystem: Upon receiving digital signals sent by the sensor network, the data acquisition and transmission subsystem transmits them to the FPGA for data processing. The data acquisition and transmission subsystem communicates via Ethernet to complete the reception of commands and the transmission of data. 3) --- ## X86-based Six-wheeled Differential Drive Mobile Robot Motion Controller Design and Implementation (Part 2) Planning and Control Algorithms - URL: https://intl.sienovo.cn/blog/132332934 - Date: 2023-08-17 - Tags: #Algorithm, #GreedyAlgorithm MPC Path Tracking Control with Input Constraints The MPC algorithm is a control method based on a control object model. Its advantage lies in considering various physical constraints of the system during control. Additionally, the method of predicting future robot pose information based on the model and current robot feedback can address the issue of control lag. 4.1 MPC Path Tracking Controller Framework Based on the algorithmic principles in Chapter 2, a robot controller framework can be established. First, a prediction equation is constructed using the robot's kinematic model. A loss function (also known as an objective function) is then formulated with the minimum control increment as the performance index. The reference path information and the output of the prediction equation are substituted into the loss function, and the current optimal solution is obtained by incorporating the constraints. The optimal solution for the current control increment is combined with the control --- ## X86-based Six-Wheeled Differential Mobile Robot Motion Controller Design and Implementation (Part 1) Software and Hardware Architecture - URL: https://intl.sienovo.cn/blog/132332739 - Date: 2023-08-17 - Tags: #HardwareArchitecture The Six-Wheeled Differential Mobile Robot (SWDMR) studied in this paper is designed to meet the point-to-point material transportation needs from resource stations to resource sites, thus requiring high obstacle-crossing capabilities. Compared to traditional four-wheeled mobile robots, six-wheeled mobile robots can provide stronger driving force. Furthermore, with six wheels compared to four, the overall vehicle load is distributed among more wheels, reducing the driving torque required by each wheel's motor, which facilitates motor selection. Compared to eight-wheeled mobile robots, although they have more wheels than six-wheeled ones and can provide greater overall driving torque, they increase control complexity and raise the cost of building the mobile system. The mobile robot's structure abandons the traditional centralized drive in favor of a distributed drive. A distributed structure eliminates systems like transmission, differential, and gearbox found in traditional vehicles, --- ## Low-Cost Solution for a Self-Developed EtherCAT Bus 4-Axis Open-Loop Stepper Driver - URL: https://intl.sienovo.cn/blog/132326601 - Date: 2023-08-16 - Tags: #ethercat Building a self-developed EtherCAT bus driver from scratch is a non-trivial undertaking, and the result described here — a 4-axis open-loop stepper driver with full EtherCAT fieldbus support — is a compelling low-cost alternative to off-the-shelf industrial motion controllers. This post covers the hardware capabilities, EtherCAT feature set, and compatibility story for this in-house design. ## What This Driver Does The board drives up to four independent stepper motor axes over a single EtherCAT network segment. Each axis is rated for up to 4 A continuous drive current, which is sufficient for the three most common NEMA frame sizes in Chinese industrial automation: 42 mm (NEMA 17), 57 mm (NEMA 23), and 86 mm (NEMA 34) motors. Because these are open-loop axes, there is no encoder feedback loop — position is commanded and assumed to be followed, which is the standard operating model for stepper drives in light-duty automation, CNC routers, pick-and-place machines, and conveyor indexing --- ## Development of CAM Functionality for Wire-cut EDM CNC System - URL: https://intl.sienovo.cn/blog/132311200 - Date: 2023-08-16 - Tags: #MCU, #EmbeddedHardware In Chapter 3, we completed the kernel customization and software porting of the Windows CE system. The CAWEP software developed by our laboratory achieved functionalities ranging from graphic drawing and editing to motion simulation and code output. However, it did not truly achieve control of the wire-cut EDM machine. In this chapter, we will conduct research and development based on the existing software to improve its CAM module and achieve control of the wire-cut EDM machine through a combination of software and hardware. **4.1 Introduction to Wire-cut EDM CAM Functionality** This paper, after completing the setup of the existing Windows CE development environment and porting the existing software, notes that the existing software has achieved CAD/CAM functionalities. To achieve intelligent and automatic control of wire-cut EDM machines, we must implement CAM functionalities from both software and hardware perspectives. CAM functionality refers to a series of computer-aided acti --- ## 嵌入式电火花线切割控制系统总体设计 - URL: https://intl.sienovo.cn/blog/132306450 - Date: 2023-08-15 - Tags: #EmbeddedHardware, #FPGADev Wire Cut Electrical Discharge Machining (Wire Cut EDM) is a precision non-contact machining process that cuts conductive materials using the erosive effect of controlled spark discharges. This article walks through the overall design of an embedded CNC control system for a high-speed reciprocating wire EDM machine, covering the working principle of the machine tool, the software architecture choices made during development, and the hardware modules selected to drive the worktable, wire transport system, and high-frequency pulse power supply. ## How Wire Cut EDM Works The fundamental operating principle of Wire Cut EDM is straightforward: a thin electrode wire — typically molybdenum or brass — is held under tension on a guide frame and moved continuously along a fixed track. A pulsed high-voltage source is applied between the wire and the conductive workpiece. When the gap between them is sufficiently small, the voltage breaks down the dielectric fluid, producing a spark that locally --- ## Design of an Integrated Drive-Control Robot Controller Based on ARM+FPGA - URL: https://intl.sienovo.cn/blog/132015349 - Date: 2023-07-31 - Tags: #ARMDev, #FPGADev, #Robotics Currently, industrial robots, CNC machine tools, and other multi-axis motion control systems on the market generally adopt a distributed control architecture consisting of a motion controller and servo drives. In this configuration, the controller handles both human-machine interaction and the interpretation and execution of NC code, interpolation calculations, then sends the calculated position commands to individual servo drives via an axis group module. This transmission is typically completed through a fieldbus with a cycle time of 4ms or less. The servo drives receive the position commands, subdivide them, and ultimately drive the motor through a three-loop control system. Usually, one servo drive controls one motor; for example, a six-joint robot requires six drives. Each servo drive independently performs position control, enabling the robot's end-effector to reach the desired position. Data exchange between servo drives relies on the fieldbus, but due to limitations in communi --- ## Rolling Bearing Condition Monitoring System Based on ARM+FPGA (STM32+ Cyclone 4) - URL: https://intl.sienovo.cn/blog/132007168 - Date: 2023-07-30 - Tags: #FPGADev Condition monitoring systems can detect abnormal states of mechanical equipment in the early stages of failure, preventing further deterioration of faults and avoiding unnecessary losses. Rolling bearings are vulnerable components in mechanical equipment. This paper focuses on the research and development of a condition monitoring system for rolling bearings. Existing monitoring techniques often involve periodically uploading monitoring data. Most of the data uploaded throughout the entire lifespan of a rolling bearing represents normal operation, leading to a waste of resources. This paper analyzes the lifecycle of rolling bearings. Considering that the degradation phase of rolling bearings accounts for a small proportion of their overall lifespan, a novel rolling bearing condition monitoring system is proposed. This system provides real-time monitoring of rolling bearings, uploading collected data only when abnormalities are detected in the rolling bearing. A monitoring device is de --- ## Edge Computing Algorithm Solution Based on RK3588+AI: Smart Parks, Smart Communities, Smart Logistics - URL: https://intl.sienovo.cn/blog/131995711 - Date: 2023-07-29 - Tags: #AI, #RK3588, #AIAlgorithmService ## RK3588 AI Edge Computing: Powering Smart Parks, Communities, and Logistics The Rockchip RK3588 has emerged as one of the most capable SoCs for edge AI deployments, combining a high-performance octa-core CPU with a dedicated 6 TOPS Neural Processing Unit in a single 8nm package. This post walks through the hardware specification of an RK3588-based AI edge computing motherboard and examines four real-world vertical deployments — smart parks, smart communities, smart logistics, and smart manufacturing — illustrating how the platform's compute density translates into measurable operational improvements. --- ## Platform Hardware Overview The board is built around the Rockchip RK3588, a 64-bit SoC manufactured on an 8nm LP process. Its CPU integrates four Cortex-A76 performance cores and four Cortex-A55 efficiency cores in a big.LITTLE configuration, with peak clock speeds up to 2.4 GHz. Compared to the previous-generation RK3399, CPU throughput is roughly 3× higher, and GPU performan --- ## Customized Smart Transportation and Smart Security Solution Based on RK3588 + FPGA + AI Algorithms - URL: https://intl.sienovo.cn/blog/131993024 - Date: 2023-07-29 - Tags: #AI, #RK3588 With the rapid development of technologies such as the Internet of Things (IoT), big data, and artificial intelligence, edge computing has become a hot topic in the field of information technology. In the IoT domain, edge computing is widely applied in various fields such as smart transportation, smart security, and industrial applications. Therefore, industrial motherboard design solutions based on edge computing technology are also receiving increasing attention. The RK3588 AI is an AI chip launched by Rockchip, primarily designed for edge computing. This chip integrates Rockchip's latest AI algorithms, enabling various AI applications such as speech recognition, natural language processing, and image recognition. Additionally, the RK3588 AI also supports automatic speech-to-vision conversion technology, allowing for gesture control without physical touch. Therefore, integrating the RK3588 AI chip into industrial motherboard designs can significantly enhance device intelligence and --- ## Design of a Desktop CNC Lathe Control System Based on Dual STM32 and FPGA - URL: https://intl.sienovo.cn/blog/131952835 - Date: 2023-07-27 - Tags: #FPGADev, #stm32, #EmbeddedHardware Desktop CNC equipment offers significant advantages for small-sized part processing in terms of cost, power consumption, and footprint. There are roughly three implementation schemes for desktop CNC equipment: The first is a miniature machine tool paired with a traditional CNC system, but desktop CNC equipment is cost-sensitive. The second is a PC-based CNC system software and its corresponding interface card controlling a miniature machine tool [1]. Due to complex software settings, it's difficult to modify for different requirements, resulting in poor accuracy and low stability. The third scheme involves independently completing the CNC system design on a specific hardware platform. Within scheme three, depending on the hardware platform, it can be divided into PC-based [2-3] and embedded chip-based [4-7]. PC-based CNC systems can simplify tasks like task scheduling and communication, enabling complex human-machine interaction functions such as simulation processing and trajectory --- ## Design of a General-Purpose Industrial Controller Based on STM32+FPGA (Part 1) System Design Scheme - URL: https://intl.sienovo.cn/blog/131952318 - Date: 2023-07-27 - Tags: #FPGADev The two 信迈 mentions in the Chinese source both fall in sections (2.3 and 2.5.4) that are entirely absent from the truncated English translation — the English cuts off mid-sentence inside the Siemens S7-200 description, well before either mention. There is no corresponding English passage to insert "Sienovo" into. --- This chapter first introduces an overview of existing PLC systems, then proposes the overall architectural design of the general-purpose industrial controller designed in this paper, analyzes the functions to be implemented in hardware and software, and finally analyzes the functions of each part and proposes specific implementation schemes. **2.1 Introduction to PLC Systems** A Programmable Logic Controller (PLC) is a new type of general-purpose automatic control device \[14\] based on microprocessors, developed by integrating computer technology, automatic control technology, and communication technology. It uses a type of programmable memory for internally storing p --- ## STM32+FPGA Abnormal Vibration Signal Acquisition and Storage System - URL: https://intl.sienovo.cn/blog/131945311 - Date: 2023-07-27 - Tags: #stm32, #FPGADev Abstract: To address the potential damage to important factory equipment during transportation, this paper designs a wireless vibration signal acquisition and storage system based on an STM32F103+FPGA framework, which can be used for real-time monitoring of abnormal vibrations during the transportation of important equipment. First, the system is rigidly attached to the equipment being transported. Vibration data is obtained through a three-axis vibration sensor. The FPGA collects and stores the data. The STM32 sends the data to the corresponding host computer via a wireless module, where corresponding vibration parameters are judged to determine the transportation status of the equipment. Vibration table experiments and actual collision experiment results prove that this wireless three-axis vibration signal acquisition and storage system can be applied to abnormal vibration monitoring of transported equipment, and features easy installation, fast, and accurate measurement. 0 Introdu --- ## The Competitive Edge of FPGA+x86 in Building High-Performance Domestic Network Testers - URL: https://intl.sienovo.cn/blog/131792557 - Date: 2023-07-18 - Tags: #FPGADev, #Networking As is well known, Ethernet has become ubiquitous in our daily lives. Enterprises, campuses, large data centers, and homes all rely heavily on networks; without them, our lives would be severely impacted. Ethernet interface speeds have also evolved rapidly: from 10M, 100M, GE, 10GE, 40GE, and 100GE, to the now increasingly mature 2.5GE, 5GE, 25GE, 50GE, and even 400GE—essentially following a trend of tenfold speed increases every decade. Many data centers and operators are already preparing to upgrade their networks from 100GE to 400GE to support the bandwidth and latency requirements of emerging technologies such as fifth-generation wireless (5G), artificial intelligence (AI), virtual reality (VR), the Internet of Things (IoT), and autonomous vehicles. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/131792557/03_.png)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/131792557/02_270d206b6328dcd407e2298cf054c0b5.png) ![](https://pub-048dcb96257f476697b113fcb --- ## RK3399/RK3588+pcie+Zynq Multi-core Architecture Design Solution for Wearable Devices - URL: https://intl.sienovo.cn/blog/131770682 - Date: 2023-07-17 - Tags: #Architecture In many fields, there are very high demands for the reliability of wearable devices. These use cases are not only rich and diverse but also complex and dynamic. This means that wearable devices must not only cope with state changes in the applications and the system itself but also consider abnormal situations caused by the device's environment. Therefore, formulating different scheduling strategies for tasks of different safety criticality levels helps wearable devices maximize system reliability in complex operating environments. 3.2 Scheduling Platform Requirements Analysis Wearable devices are characterized by rich application scenarios and numerous task categories. However, for most scenarios, the available volume for wearable devices is very limited, thus imposing high requirements on system power consumption and heat dissipation. Addressing these characteristics, an analysis of wearable devices leads to the following summarized requirements for the computing platform: (1) The --- ## RK3588-Camera: MIPI-CSI and ISP Debugging - Path Analysis - URL: https://intl.sienovo.cn/blog/131767085 - Date: 2023-07-17 - Tags: #RK3588, #ISP This article introduces the path analysis for Camera: MIPI-CSI debugging on the RK3588 platform. The MIPI Alliance, which stands for Mobile Industry Processor Interface (MIPI) Alliance. MIPI (Mobile Industry Processor Interface) is an open standard and specification initiated by the MIPI Alliance, developed for mobile application processors. The purpose is to standardize internal mobile phone interfaces such as camera, display, RF/baseband interfaces, etc., thereby reducing the complexity of mobile phone design and increasing design flexibility. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/131767085/01_25cdacf02200b05c3bc1172317f2767d.png) CSI & DSI • CSI (Camera Serial Interface): Camera interface • DSI (Display Serial Interface): Display interface ## II. Terminology Explanation: ISP (Image Signal Processor): Refers to the image signal processing module. Its main function is to post-process the signals output by the front-end image sensor. It relies on the ISP --- ## RK3588+FPGA Real-time Video Processing, Dual-Screen Display, and Storage Solution - URL: https://intl.sienovo.cn/blog/131759080 - Date: 2023-07-17 - Tags: #FPGADev Schematic Diagram of Main Functional Circuits on the Mainboard Platform ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/131759080/01_6cf5ba0adbad0b49ee72c955d48c6248.png) On the ARM side: The footswitch uses dual-channel level input on port 10. The touch panel connects to the mainboard via UART, with an external 12V power supply. The keyboard is a self-developed product, transmitting UART data transparently over USB and supplying 12V power. USB and Gigabit Ethernet are interfaces on the mainboard, with the USB being a 3.0 host interface. The SSD is an internal drive. The main video output interfaces include HDMI, DVI, DP, SDI, analog RGB, CVBS, and S-video. Among these, HDMI, DP, and SDI support 4K 60fps. On the FPGA side, image input interfaces include SDI and MIPI. SDI input supports 1080P 60FPS. Its main application scenario is interfacing with external systems to achieve Picture-in-Picture display of image data from multiple devices. MIPI serves as the signal interf --- ## Design of an 8K Smart Camera Solution Based on RK3588 - URL: https://intl.sienovo.cn/blog/130505909 - Date: 2023-07-17 - Tags: #RK3588, #8k, #Camera ## Design of an 8K Smart Camera Solution Based on RK3588 High-resolution imaging has entered a new era as 8K displays (7680×4320, approximately 33 million pixels) move from broadcast studios into consumer living rooms. Building a camera system that can feed those displays end-to-end — from sensor to screen — demands careful co-selection of processor, image sensor, interconnect, and thermal management. This article walks through the hardware architecture of an 8K smart camera built around the Rockchip RK3588 SoC and Sony IMX435 sensor, with graphene-based heat dissipation, and covers the key PCB layout rules that keep the system stable in production. --- ## System Architecture The signal chain is straightforward but demanding at every stage: **IMX435 → MIPI CSI-2 → RK3588 (ISP + encode) → HDMI 2.1 → 8K TV** The Sony IMX435 captures raw 8K imagery and streams it over MIPI differential pairs to the RK3588. The SoC's on-chip ISP decodes and processes the raw frames, then the encoded --- ## STM32 ARM+FPGA Servo Control System (Part Two) Software and FPGA Design - URL: https://intl.sienovo.cn/blog/131730593 - Date: 2023-07-14 - Tags: #FPGADev, #stm32, #ARMDev A complete servo system involves numerous modules, making it impractical to detail each one. This article focuses on the more challenging FPGA implementation, providing a brief overview of the ARM-side workflow. The FPGA is central to the control system, handling critical functions like the Field-Oriented Control (FOC) algorithm, current sampling, and encoder sampling. The performance of these FPGA-based algorithms directly dictates the quality of motor control. Due to the inherent parallelism and real-time constraints of FPGA operation, careful consideration of design timing and the coordinated scheduling of various tasks is paramount, significantly increasing design complexity. Below, we will delve into the design specifics of key FPGA program parts, primarily covering the Space Vector Pulse Width Modulation (SVPWM) algorithm module, the BISS-C encoder feedback module, and the Tamagawa encoder feedback module. ## 4.1 SVPWM Algorithm Program Design As established in prior discussion --- ## 基于STM32 ARM+FPGA伺服控制系统总体设计方案(一） - URL: https://intl.sienovo.cn/blog/131730439 - Date: 2023-07-14 - Tags: #FPGADev, #ARMDev **Title: Overall Design Scheme for STM32 ARM+FPGA Servo Control System (Part 1)** **Design Requirements** A complete servo control solution comprises a host computer, an integrated drive and control unit, and a power board. The operator sends various commands via the host computer, and the controller parses these commands to execute corresponding servo functions. Next, the controller transmits drive signals to the power board to drive the motor. Finally, the controller collects feedback information for closed-loop control and uploads the data. Considering the current development status and functional requirements of embedded servo controllers both domestically and internationally, the main functional requirements for the servo control system in this paper are defined as follows: (1) Develop an integrated drive and control board. (2) Develop a servo control system for rigid-flexible coupled platforms while also accommodating control for ordinary rigid platforms. (3) Compatible with --- ## Hardware Design of ZYNQ-based Array Eddy Current Testing System (Part 1) - URL: https://intl.sienovo.cn/blog/131715908 - Date: 2023-07-14 - Tags: #FPGADev Array eddy current (AEC) testing is a well-established non-destructive evaluation (NDE) technique used to detect surface and near-surface defects in conductive materials. Unlike single-probe eddy current, an array system distributes dozens of drive and sense coils across a probe footprint, enabling rapid C-scan imaging without mechanical raster scanning. Building such a system from scratch demands careful co-design of analog front-end hardware and real-time digital signal processing — a task well suited to a ZYNQ SoC that pairs a hard ARM processor with programmable logic on the same die. This article walks through the hardware architecture of a multi-channel AEC acquisition system built around the Xilinx Zynq-7020, covering the DAC excitation path, power amplifier stage, analog multiplexing, and ADC acquisition chain. ## System Architecture Overview The signal chain follows a classic lock-in topology adapted for multi-channel operation: 1. **Excitation path** — ZYNQ PL reads a sinu --- ## RK3568+FPGA+SylixOS Application in Power Products - URL: https://intl.sienovo.cn/blog/130061237 - Date: 2023-07-07 - Tags: #SylixOS, #RK3568 **What are the advantages of ARM + FPGA architecture?** In recent years, with the continuous advancement of China's New Infrastructure and Made in China 2025 initiatives, single ARM processors are increasingly struggling to meet the functional requirements of industrial sites. Industries such as energy and power, industrial control, and smart healthcare often require ARM + FPGA architecture processor platforms to achieve specific functionalities, such as multi-channel/high-speed AD acquisition, multiple Ethernet ports, multiple serial ports, multi-channel/high-speed parallel DI/DO, and high-speed data parallel processing. **So, what exactly are the advantages of ARM + FPGA architecture?** ARM: Rich interface resources, low power consumption, excels at multimedia display, logic control, etc. FPGA: Excels at multi-channel or high-speed AD acquisition, interface expansion, high-speed signal transmission, high-speed data parallel processing, etc. Therefore, the ARM + FPGA architecture --- ## Design of a VME Bus Controller Based on RK3399 + FPGA (Part 2): Hardware and FPGA Logic Design - URL: https://intl.sienovo.cn/blog/131548213 - Date: 2023-07-05 - Tags: #FPGADev, #RK3399+FPGA, #VME 3.2 FPGA Minimal System Design An FPGA minimal system refers to the most basic system required for the FPGA to operate properly, including power circuits, configuration circuits, clock, and reset circuits. The FPGA used in this design is the PG2L100H from TsingMicro. The following sections detail the circuit design of each component in the FPGA minimal system. (1) Power Circuit Design The FPGA requires multiple power supply voltages: 3.3V, 1.8V, 1.2V, and 1V. Specifically, the core logic and dedicated RAM (DRAM) modules use 1V; the auxiliary power supply is 1.8V; the IO BANKs use 3.3V; and the HSST high-speed serial interface requires both 1V and 1.2V analog supplies. The FPGA power design block diagram is shown in Figure 3-5 below. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/131548213/01_803daaf2ad1a23362419e07a976c66dc.png) The input 5V power is converted using Shanghai Belling's power chips BL1084 and BL9309. BL1084 is an LDO regulator that provides a fixed --- ## VME Bus Controller Design Based on RK3399+FPGA (Part 1) Overall Design - URL: https://intl.sienovo.cn/blog/131548096 - Date: 2023-07-05 - Tags: #FPGADev, #RK3399+FPGA, #VME 2.1 Requirements Analysis and Technical Specifications 2.1.1 Requirements Analysis The VME bus controller needs to implement functions such as data transmission, interrupt handling, and measurement display. It also needs to have an operating system, low-level drivers, and functional interfaces to facilitate user development and use of upper-layer application software. This project requires the localized development of a VME controller, thus necessitating the selection of a domestic processor as the main control unit. The VME controller needs video interfaces, USB interfaces, network ports, etc., for connecting peripherals, and also requires PCI, PCIe, or other bus interfaces for communication with an FPGA. Major domestic CPU manufacturers include Phytium, Loongson, Sunway, and Rockchip. Phytium FT-2000A/2 uses the ARMv8 architecture, but its technical support and open-source resources are limited, and related development boards are scarce. The Loongson 2K1000 processor features PC --- ## [Domestic Virtual Instrument] Multi-channel Synchronous Data Acquisition Design Scheme Based on ZYNQ7045+V7 FPGA (Part 2) - URL: https://intl.sienovo.cn/blog/131469011 - Date: 2023-06-30 - Tags: #FPGADev, #DAMODevMatrix, #Community The main process of the multi-channel data acquisition circuit is to achieve 4-channel analog signal reception, with data undergoing analog-to-digital conversion and signal processing before being transmitted via optical fiber to the central station. The multi-channel data acquisition circuit consists of an analog signal acquisition unit, a digital signal processing unit, and a signal adapter board. The block diagram is shown in Figure 4-1.![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/131469011/01_d74f32c36273a42fe23b2eda56f4cbac.png) To perform reconnaissance and monitoring of multiple key frequency points within the bandwidth, the digital signal processing unit utilizes 8 receiver channels from 4 ADRV9009 analog-to-digital converter chips. The 4-channel analog signal processing circuit is divided into 8 paths connected to the 8 inputs of the ADCs, enabling a single ADC to focus on monitoring two key frequency points within the bandwidth. Each frequency point has 4 sy --- ## [Domestically Developed Virtual Instruments] Multi-channel Synchronous Data Acquisition Design Solution Based on ZYNQ7045+V7 FPGA (Part 1) - URL: https://intl.sienovo.cn/blog/131429316 - Date: 2023-06-30 - Tags: #FPGADev, #DAMODevMatrix, #Community Multi-channel data acquisition devices are widely used in today's era of information digitalization. Various measured information, such as light, temperature, pressure, humidity, and position, must be sampled and processed by multi-channel signal acquisition systems before they can be further analyzed and utilized by us [37]. In fields with high acquisition rate requirements, such as military, aerospace, aviation, and industrial manufacturing, higher demands are placed on the sampling and processing rates of signal acquisition systems to meet the real-time requirements of signal analysis. The demand for high-speed signal acquisition systems is continuously increasing. 2.2.1.3 JESD204 Interface To address the high-speed transmission limitations of parallel interfaces, JEDEC, the Solid State Technology Association, introduced JESD204, a serial data interface with transmission rates up to 10G. Combining the advantages of differential LVDS current-mode drivers and using CML (Current Mode --- ## RK3568/RK3588+LinuxCNC+EtherCAT Solution - URL: https://intl.sienovo.cn/blog/131423799 - Date: 2023-06-27 - Tags: #linuxcnc The RK3588 is Rockchip's new-generation flagship high-end processor, featuring high computing power, low power consumption, powerful multimedia capabilities, and rich data interfaces. It is equipped with an octa-core CPU (quad-core A76 + quad-core A55) and an ARM G610MP4 GPU, with a built-in NPU offering 6.0 TOPs of computing power. It boasts five major technical advantages: 1. Built-in multiple powerful embedded hardware engines, supporting 8K@60fps H.265 and VP9 decoders, 8K@30fps H.264 decoder, and 4K@60fps AV1 decoder; supports 8K30fps H.264 and H.265 encoders, high-quality JPEG encoder/decoder, and dedicated image pre-processor and post-processor. 2. Built-in 3D GPU, compatible with OpenGL ES1.1/2.0/3.2, OpenCL 2.2, and Vulkan 1.2. A special 2D hardware engine with MMU will maximize display performance and provide a smooth user experience. 3. Built-in Rockchip self-developed 48MP ISP (Image Signal Processor), supporting numerous algorithm accelerators such as HDR, 3A, LSC, --- ## RK's Most Powerful ARM Series: RK3588 + AI + EtherCAT (Linux + Xenomai + IGH) Real-time Solution - URL: https://intl.sienovo.cn/blog/130940945 - Date: 2023-06-27 - Tags: #AI, #ethercat, #RK3588, #XENOMAI The RK3588 is Rockchip's new-generation flagship high-end processor, featuring high computing power, low power consumption, powerful multimedia capabilities, and rich data interfaces. It is equipped with an octa-core CPU (quad-core A76 + quad-core A55) and an ARM G610MP4 GPU, with a built-in NPU offering 6.0 TOPs of computing power. It boasts five major technical advantages: 1. Built-in multiple powerful embedded hardware engines, supporting 8K@60fps H.265 and VP9 decoders, 8K@30fps H.264 decoder, and 4K@60fps AV1 decoder; supports 8K@30fps H.264 and H.265 encoders, high-quality JPEG encoder/decoder, and dedicated image pre-processor and post-processor. 2. Built-in 3D GPU, compatible with OpenGL ES1.1/2.0/3.2, OpenCL 2.2, and Vulkan 1.2. A special 2D hardware engine with MMU will maximize display performance and provide a smooth operating experience. 3. Built-in Rockchip's self-developed 48-megapixel ISP (Image Signal Processor), supporting numerous algorithm accelerators such --- ## Design of a Distributed Data Acquisition System Based on Domestic FPGA - URL: https://intl.sienovo.cn/blog/131390460 - Date: 2023-06-26 - Tags: #DataAcquisition, #VirtualInstrument Design of a Distributed Data Acquisition System Based on Domestic FPGA =========================================================== A distributed data acquisition system is a complex network of sensors, data processing units, and storage devices that work together to collect and analyze data from various sources. In this article, we will explore the overall architecture of a distributed data acquisition system based on domestic FPGA (Field-Programmable Gate Array) technology. The structure of the distributed data acquisition system is shown in Figure 2.1, mainly comprising a sensor network, a data acquisition and transmission subsystem, a data aggregation platform, and a data acquisition system control terminal. ### Sensor Network The sensor network is the core of the distributed data acquisition system, responsible for collecting data from various sensors and transmitting it to the data acquisition and transmission subsystem. The sensor network can be composed of various types of s --- ## [Domestic Virtual Instruments] Design of a Power Quality Analyzer Based on ARM+FPGA+8-channel High-speed AD to Replace National Instruments' Solution (Part 1) Introduction to the NI Solution - URL: https://intl.sienovo.cn/blog/131200541 - Date: 2023-06-26 - Tags: #FPGADev, #PowerQualityAnalyzer, #ARM+FPGA, #NI I. Background: Introduction to the Acquisition Solution Based on National Instruments The data analysis system for the power quality analyzer designed in this paper uses National Instruments LabVIEW 2018 as its software development platform. Combined with the hardware platform, it achieves data acquisition, waveform display, and data analysis. The primary role of the hardware circuit is to attenuate and condition grid signals. It is responsible for converting grid signals into signals that can be input into a computer for analysis, making the hardware structure crucial for the entire design. 3.1 Signal Conditioning Circuit Design 3.1.1 Overall Structure of the Conditioning Circuit Conditioning circuits typically include filtering, amplification, and isolation circuits. In practical power quality analysis systems, the signal amplitude output by Hall voltage and current sensors often does not match the range of data acquisition cards, and the signal-to-noise ratio is low, preventing di --- ## STM32 ARM+FPGA-based Power Quality Analyzer Solution (Part 1) Hardware Design - URL: https://intl.sienovo.cn/blog/131320466 - Date: 2023-06-23 - Tags: #FPGADev This chapter primarily presents the design goals and hardware design scheme of this system. It then details the hardware circuit design process, including the data acquisition board and the FPGA+ARM control board. 3.1 System Design Goals The main objective of this system is to achieve high-precision measurement and data analysis of power quality indicators. The specific technical specifications are as follows: 1. Power Quality Indicator Measurement Accuracy: (1) Voltage: ±0.3% of rated voltage; (2) Current: ±0.5%; (3) Frequency: ±0.01 Hz; (4) Three-phase unbalance: ±0.2%; (5) Harmonic analysis: 1st-17th. 2. Capable of real-time display of power quality indicators and three-phase voltage and current waveforms, enabling data sharing and good human-machine interaction. 3. Capable of storing grid operation data. 3.2 System Overall Scheme Control circuit structures in measurement systems vary widely, including control circuits with standalone FPGA, ARM, or DSP chips, as well as mult --- ## STM32 ARM+FPGA-based Power Quality Analyzer Solution (Part 2) Software Design - URL: https://intl.sienovo.cn/blog/131320640 - Date: 2023-06-21 - Tags: #FPGADev This section primarily introduces the software design of the FPGA+ARM control unit. The FPGA+ARM control unit involves development in Verilog HDL (Hardware Description Language) and C language. The FPGA part mainly controls AD7606 analog-to-digital conversion, digital three-phase phase-locked loop (PLL) and FFT harmonic calculation modules, SDRAM controller design, FSMC interface module, etc. The ARM part primarily completes the porting of the FreeRTOS embedded real-time operating system, data reading and writing between FPGA and ARM, serial communication between ARM and the host PC, and the derivation of various power quality parameters after floating-point operations. 4.1 FPGA Module Software Design 4.1.1 Advantages of FPGA Design FPGA adopts a top-down design methodology, dividing complex systems into lower-level functional modules, and then further dividing these lower-level modules into sub-modules, continuing until basic modules can be used. This approach significantly improv --- ## AM62X+FPGA+AD+VxWorks Real-time Operating System Data Acquisition and Processing Solution - URL: https://intl.sienovo.cn/blog/131240288 - Date: 2023-06-16 - Tags: #AM62X, #FPGADev The AM62X processor family from Texas Instruments has become a compelling choice for industrial-grade embedded systems that demand real-time determinism, robust I/O, and long lifecycle support. This post walks through three hardware reference designs built around the AM6231 SoC and VxWorks RTOS — a PrPMC-form-factor compute module, an industrial environmental monitoring unit, and a heavy-machinery controller — each targeting a distinct segment of the industrial edge-computing market. ## Why AM6231 + VxWorks? The AM6231 is part of TI's Sitara AM62x family, featuring an ARM Cortex-A53 application processor running at up to 1.0 GHz (dual-core 64-bit on higher-tier variants) and up to 1.2 GHz on the single-core AM6231. The AM62x line is designed specifically for industrial HMI, machine control, and data acquisition — offering a deterministic hardware architecture that pairs well with a hard real-time RTOS. VxWorks, developed by Wind River, is a certified hard real-time operating system --- ## 【Domestic Virtual Instruments】ZYNQ-based Acoustic Emission Acquisition System Solution - URL: https://intl.sienovo.cn/blog/131162261 - Date: 2023-06-12 - Tags: #DataAcquisition, #Sound, #VirtualInstrument The overall design process of the system involves selecting hardware equipment according to the aforementioned design requirements and building the hardware platform for the acoustic emission acquisition system. On this platform, the acoustic emission acquisition board will be designed, and the host software will be designed according to the requirements. The working process of this system is as follows: The host software connects to the lower-layer device via Ethernet using a pre-set IP address and port number, and sends a "start acquisition" command to the lower-layer device. Upon receiving the command, the lower-layer device returns an "acquisition started" command to the host software and waits for data acquisition. The sensor module continuously monitors the acquired signal. The signal is amplified by the amplification module and then transmitted to the ZYNQ 7010 board via the A/D analog-to-digital conversion module. When the signal exceeds a threshold, transmission begins. The --- ## Design and Implementation of a Low-Latency Video Transmission System Based on RK3399/RK3588 H.265/HEVC - URL: https://intl.sienovo.cn/blog/131096055 - Date: 2023-06-07 - Tags: #h.265, #AudioVideo, #AI In recent years, with the rise of short video live streaming, video transmission equipment has become increasingly prevalent in daily life. Demands for technical indicators such as image clarity, frame rate, and bitrate are continuously increasing, and the amount of data contained in video frames is also rapidly growing. Under limited network bandwidth, traditional video capture devices face technical bottlenecks such as insufficient compression ratio, low frame rate, and high latency, which prevents their application in ultra-high-definition image transmission scenarios. Therefore, in the face of continuously improving video quality, enhancing the encoding and decoding efficiency of video transmission systems and reducing transmission latency becomes particularly crucial. To address the aforementioned issues, this paper proposes a low-latency video transmission system based on the H.265 encoding and decoding protocol, designed to solve the problem of high transmission latency in ult --- ## RK3588-based High-Performance AI Edge Computing Gateway - URL: https://intl.sienovo.cn/blog/131095790 - Date: 2023-06-07 - Tags: #Networking, #RK3588, #DataCanvasCompute, #Community The intelligent O&M system is divided into terminal layer, edge layer, platform layer, and application layer from bottom to top, as shown in Figure 1. The terminal layer acts as the nerve endings of the entire system, responsible for on-site data collection, including various sensors, controllers, and other IoT devices, in addition to cameras. The edge layer aggregates unstructured video data and IoT data from various on-site terminals, performs pre-processing, triggers action responses according to predefined rules, and uploads processing results and relevant data to the cloud. The platform layer is responsible for global information processing and storage, undertaking computing tasks that the edge layer cannot perform, issuing business rules and intelligent algorithms to the edge layer, and providing standard API interfaces for open integration with various applications. The application layer utilizes analyzed and processed structured/semi-structured data, combined with specific bus --- ## RK3399+FPGA-based Ground Test Bench Multi-parameter Data Logger Solution (Part 1) Software Design and Testing - URL: https://intl.sienovo.cn/blog/131095204 - Date: 2023-06-07 - Tags: #FPGADev This blog post delves into the software design and testing aspects of an RK3399+FPGA-based ground test bench, specifically focusing on a multi-parameter data logger solution. We will explore the software's architecture, its core functionalities, the underlying Qt communication mechanisms, and the practical implementation and testing of its user interface, providing a comprehensive overview for engineers working with similar embedded systems and data acquisition challenges. ## Software Design Principles for the Ground Test Bench The development of the test bench software began with a thorough analysis of the operational requirements for a specific type of data logger. The primary goal was to create a fully functional, user-friendly, and intuitive test bench application using Linux-Qt as the main development framework. The software's architecture is structured around three distinct operating modes, each managed by its own functional window: * **Analog Signal Source:** Responsible f --- ## RK3399+FPGA-based Ground Test Bench Multi-parameter Data Logger Solution (Part 1) Hardware Design - URL: https://intl.sienovo.cn/blog/131095009 - Date: 2023-06-07 - Tags: #Networking, #RK3399+FPGA The only brand mention in the Chinese source is a figure caption in section 2.3.1: "深圳信迈RK3399开发板外观及接口". That section is entirely absent from the English text provided — the translation ends mid-sentence well before reaching it. There is no location in the supplied English text where "Sienovo" needs to be inserted. The ground test bench is a supporting test equipment for a certain model of data logger. Its main tasks include: functional checks of the logger before flight, testing its operational status and stability; after the experiment, reading back and further processing the data stored in the logger, analyzing the data to determine the changes in various missile parameters during flight tests, and thus providing feedback on the missile's operational status. Therefore, the stability and data processing capabilities of ground testing play a crucial role in missile research. This chapter will start with requirements, conduct an overall analysis of the logger's main tasks, and determi --- ## NXP IMX8M + EtherCAT+CODESYS Industrial Real-time Motion Control Solution - URL: https://intl.sienovo.cn/blog/131060757 - Date: 2023-06-06 - Tags: #ethercat The new i.MX 8M Plus heterogeneous application processor for edge computing applications features a dedicated neural network accelerator, an independent real-time subsystem, dual camera ISP, high-performance DSP, and GPU. NXP Semiconductors announced the launch of the i.MX 8M Plus application processor, further enriching its industry-leading product portfolio. This is NXP's first i.MX series processor to integrate a dedicated Neural Processing Unit (NPU), enabling advanced machine learning inference at the edge in industrial and IoT domains. **i.MX 8M Plus Offers**       High-performance NPU with 2.3 TOPS (Tera Operations Per Second) of compute power       Quad-core Arm Cortex-A53 subsystem clocked at up to 2GHz       Independent real-time subsystem based on Cortex-M7, clocked at up to 800MHz       High-performance 800MHz audio DSP for voice and natural language processing       Dual Camera Image Signal Processor (ISP)       3D GPU for rich graphics rendering By combining the high- --- ## LS1028/LS1043/LS1046 + FPGA + TSN Multi-path Time-Sensitive Networking Smart Industrial Gateway Solution - URL: https://intl.sienovo.cn/blog/131060263 - Date: 2023-06-06 - Tags: #Server, #CloudComputing, #LS1028 With the rapid development and application of technologies such as the Internet of Things (IoT), big data, and artificial intelligence, traditional cloud computing models face enormous challenges. This has spurred a transformation in computing paradigms, thus giving rise to edge computing. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/131060263/01_26de3c838d9195911cd4cebfb1d33024.jpeg) Edge computing refers to an open platform that integrates core capabilities such as networking, computing, storage, and applications, located closer to physical objects or data sources, to provide services at the nearest point. Simply put, it means that after data is computed and processed locally at the data collection point (e.g., timestamping, data formatting, classifying event and process data), "on-site" decisions are made based on the results, and operations such as storing and forwarding the processed data to cloud platforms are performed. ![](https://pub-048dcb96257f476697b113f --- ## 3U VPX Solution Based on Domestic RK3588 and Multi-Channel H.265 Video Encoding/Decoding and Transcoding - URL: https://intl.sienovo.cn/blog/131053928 - Date: 2023-06-05 - Tags: #VideoCodec, #ffmpeg, #DAMODevMatrix, #Community ## 1. Overview The 3U VPX audio and video transcoding module is a solution developed by Xinmai Technology based on the RK3588 platform, designed for audio and video encoding, decoding, and transcoding. This module supports SDI video and analog audio input, enabling resolution and frame rate conversion for video, as well as sample rate and bitrate conversion for audio. It can decode or transcode video streams received via network interfaces, and supports SDI, CVBS, and analog audio output. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/131053928/01_98b220bfabc8eb53577523e13d4dd7d0.jpeg) ## 2. Product Features 1. The system supports one channel of 3G/HD-SDI HD signal acquisition, with support for multiple resolutions. It can encode the acquired signals or output them locally for display according to application requirements. 2. Supports transcoding of various types of network audio and video streams, including RTSP/RTMP/ONVIF/SIP/TS; transcoding function provides both --- ## RK3588+FPGA+Cameralink High-Speed Camera Solution - URL: https://intl.sienovo.cn/blog/131051184 - Date: 2023-06-05 - Tags: #FPGADev, #RK3588, #ImageProcessing 1. Video input, with visible light using LVDS and infrared using CameraLink. 2. H.264 low-bitrate compression encoding for local storage. 3. H.264 compression outputs real-time streams using a synchronous 422 interface or network port UDP protocol. 4. Uses serial port for communication, such as between visible light, infrared, laser, or ground control software. 5. Network connection for UDP-based communication control. 6. Integrates common algorithms for optoelectronic payloads:         a. Target localization, target velocity and direction measurement         b. Target tracking         c. Moving target detection         d. Electronic image stabilization         e. Target detection         f. ... ... 7. Servo control algorithms are planned for addition, using interfaces like SPI or serial port to access data from encoders, gyroscopes, etc., for servo control (to be completed in the next phase). ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/131051184/01_9961cadb56a --- ## Industrial Internet-based RV1126+AI Security Monocular/Binocular HD Visual Analysis and Counting Solution - URL: https://intl.sienovo.cn/blog/130937885 - Date: 2023-05-29 - Tags: #AI, #ComputerVision, #DeepLearning, #ModelEngineCommunity, #Community ## ### **1 Product Introduction** 1. 1. **Product Overview** The Monocular Vision Analysis Counter is a regional statistical counter developed by Xinmai Technology based on monocular image analysis and deep learning algorithms. It can accurately identify objects within a monitored area, count the number of people/vehicles staying in the area, and also count the number of people entering and leaving the area. It is suitable for various scenarios requiring passenger flow statistics, such as buses, coaches, shopping malls, ferries, and scenic spots, and can also be used for scenarios requiring vehicle counting. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130937885/01_c1a8f9d677b89be8f624fa5a9916d273.png) #### **1.2 Product Principle** First, a monocular camera captures image information. The deep learning model simulates the human brain's visual perception system, directly extracting features such as object movement, color, and contour from raw images. These feat --- ## Based on Fudan Micro FMQL45T900 All-Domestic ARM+FPGA Core Board Solution - URL: https://intl.sienovo.cn/blog/130934572 - Date: 2023-05-29 - Tags: #FPGADev The XM745D is a fully domestically produced ARM core board based on Shanghai Fudan Microelectronics FMQL45T900. This core board integrates the minimum system of Fudan Micro's FMQL45T900 (compatible with XILINX's XC7Z045-2FFG900I) onto an 87*117mm core board. It can serve as a core module for functional expansion, enabling rapid construction of a signal processing platform, which facilitates user product development. The core board features DDR3 SDRAM, EMMC, SPI FLASH, Ethernet PHY chips, and other components. IO expansion for the PL (Programmable Logic) side is achieved through two board-to-board FMC connectors. The FMQL45T900 is a fully programmable fusion chip developed by Fudan Microelectronics. It integrates a Processing System (PS) based on a feature-rich quad-core processor and Programmable Logic (PL) on a single chip, utilizing the most advanced 28nm process technology. Coupled with corresponding development software, it enables an integrated hardware and software platform, fac --- ## High-Speed Data Acquisition and Image Processing Solution Based on Fudan Micro JFM7K325T Fully Domestic FPGA - URL: https://intl.sienovo.cn/blog/130934525 - Date: 2023-05-29 - Tags: #FPGADev, #ImageProcessing, #AI, #FMSH Board Overview The PCIE-XM711 is a high-performance data preprocessing FMC carrier board based on the PCI Express bus architecture. It features Fudan Micro's JFM7K325T FPGA as the real-time processor to enable interconnection between various interfaces. This board supports 100% domestic production. The board provides one FMC (HPC) interface, one PCIe x8 host interface, and onboard 64-bit DDR3 SDRAM for large-capacity buffering. It also supports one 1000BASE-T Gigabit Ethernet interface and four RS422 interfaces, along with GPIO input and output capabilities. By integrating different FMC daughter cards, this board enables rapid development of server-based hardware platforms for data acquisition, real-time processing, and high-performance storage. The board conforms to the standard full-height PCI Express form factor, making it compatible with mainstream servers and workstations. It is widely applicable to server-based data acquisition, graphics and image processing, and video/i --- ## 【Domestic Virtual Instrument】High-Speed Data Acquisition Platform Based on JFM7K325T (Fudan Micro FPGA) - URL: https://intl.sienovo.cn/blog/130934355 - Date: 2023-05-29 - Tags: #FPGADev, #DomesticVirtualInstrument, #FMSH Board Overview The XM714 is a domestically developed 5-channel HD-SDI video capture and image processing platform. This platform utilizes Shanghai Fudan Micro's high-performance Kintex series FPGA and Huawei HiSilicon's high-performance video processor HI3531DV200. Huawei HiSilicon's HI3531DV200 is a powerful neural network engine integrating an ARM A53 quad-core processor, supporting various intelligent algorithm applications. It integrates multiple MIPI video interfaces, breaking through the performance bottleneck of digital interface video input, and features a high-performance H.265 video codec engine, which further enhances the algorithmic effects and performance of traditional video image processing. The onboard powerful FPGA processor primarily handles video image pre-processing algorithms. It features an onboard 1GByte ultra-large capacity DDR3 SDRAM data cache, supporting a maximum memory bandwidth of 12GByte/s, breaking through the bottleneck of traditional video image proc --- ## [Domestic Virtual Instrument] Design of a Dual-Channel 6.4GSPS High-Speed Data Acquisition Module Based on FPGA and JESD204B Clocking (Part 1) Overall Scheme - URL: https://intl.sienovo.cn/blog/130466924 - Date: 2023-05-29 - Tags: #FPGADev, #6GSPS, #HighSpeedDAQ, #DomesticVirtualInstrument Designing high-speed data acquisition (DAQ) modules is a complex endeavor, especially when targeting demanding applications like virtual instruments that require exceptional sampling rates and precision. This post, the first in a series, delves into the overall design scheme for a dual-channel 6.4 GSPS high-speed data acquisition module. We will explore the critical specifications, analyze different Analog-to-Digital Converter (ADC) selection strategies, detail the analog front-end design, discuss the intricate JESD204B clocking requirements, and outline the high-capacity data storage solution necessary to handle the immense data throughput. ## 2.1 High-Speed Data Acquisition Module Specifications and Scheme Analysis The foundation of any high-performance DAQ system lies in its core specifications. For this module, designed to operate within an AXIe test bus platform, the following key technical parameters define its capabilities and guide the subsequent design choices. ### 2.1.1 Hi --- ## Domestic Virtual Instrument: DSP+FPGA+ADS1282-Based 32-bit High-Precision Data Acquisition Solution (Part 1) - URL: https://intl.sienovo.cn/blog/130419213 - Date: 2023-05-29 - Tags: #FPGADev, #DomesticVirtualInstrument ## Introduction Designing a high-precision inertial navigation data acquisition platform requires balancing three competing demands: the raw throughput needed to digitize analog sensor signals at publication-grade resolution, the real-time compute horsepower to run navigation algorithms, and the rich I/O fabric to talk to GPS receivers, gyroscopes, barometers, and odometers simultaneously. This post walks through the system requirements, architecture decisions, and key component selections for a DSP+FPGA+ADS1282-based 32-bit acquisition platform aimed at inertial navigation applications — covering everything from power-supply rails through ADC figure-of-merit choices. --- ## System Requirements Analysis ### Functional Design Requirements The hardware processing platform is responsible for three categories of work: 1. **Data acquisition** — collecting analog output signals from inertial measurement units (IMUs), digitising three axes of accelerometer current, and receiving externa --- ## [Domestic Virtual Instrument] Simulation Design of High-Speed Data Acquisition Circuit for Semiconductor Motion Stage Based on DSP+FPGA+AD+ENDAC (Part 4) - URL: https://intl.sienovo.cn/blog/130419014 - Date: 2023-05-29 - Tags: #FPGADev, #DSPFPGACircuitSimulation, #endac, #DomesticVirtualInstrument The entire debugging, verification, and simulation analysis is divided into three steps: The first step involves PCB inspection and electrical characteristic testing, primarily to verify whether the hardware design functions correctly. The second step involves functional testing of each sub-module, including stability and reliability testing of high-speed fiber optic serial communication, A/D and D/A conversion characteristic testing, EnDat serial communication timing testing and verification, etc., primarily to verify whether the FPGA software core operates correctly and meets the expected design requirements. The third step involves system joint testing and verification, which mainly includes the DSP system sending control command data to the remote servo control subsystem, and requesting and verifying remote position data from EnDat, incremental position data, and remote data from various digital or analog sensors. 5.1 Debugging and Verification Simulation Platform To verify and te --- ## [Domestic Virtual Instruments] High-Speed Data Acquisition FPGA EnDat Design for Semiconductor Motion Stages Based on DSP+FPGA (Part 3) - URL: https://intl.sienovo.cn/blog/130414089 - Date: 2023-05-29 - Tags: #FPGADev, #dsp+fpga, #endac, #SemiconductorStage, #DomesticVirtualInstrument ## Implementation of the EnDat Bidirectional Serial Communication Protocol Semiconductor motion stages demand absolute position feedback with sub-micron repeatability and deterministic latency. This post covers Part 3 of a DSP+FPGA design series focused on implementing the EnDat 2.2 bidirectional serial communication protocol in an FPGA, including line delay compensation, mode command framing, CRC verification, and the full data-request pipeline driven by a DSP top-level controller. ## Protocol Overview and Physical Layer Data — whether measured position values, encoder parameters, or diagnostic information — flows bidirectionally between the position encoder and the EnDat protocol core. The physical layer uses RS-485 differential signaling, which provides excellent common-mode noise rejection suited to the electrically noisy environment of a semiconductor fab. All data transfers are synchronous: the clock pulses are generated by the servo control system on the DSP side and propagat --- ## [Domestic Virtual Instrument] PXI 24-Bit Dynamic Signal Data Acquisition Module Hardware and Software Design Solution, Supporting Domestic Production - URL: https://intl.sienovo.cn/blog/130390058 - Date: 2023-05-29 - Tags: #HighPrecisionDAQ, #DomesticVirtualInstrument [IEPE Sensors (Audio Testing, Noise Testing, Vibration Analysis)] Complies with PXI Specification 2.2 24-bit Sigma-Delta ADC and DAC Maximum sampling rate up to 432 KS/s, software-programmable Programmable input ranges: ±40 V, ±10 V, ±3.16 V, ±1 V, ±0.316 V Programmable output ranges: ±10 V, ±1 V, ±0.1 V AC or DC input coupling, software-selectable Trigger I/O connector for external digital trigger signals IEPE excitation supported on each analog input channel, software-configurable. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130390058/01_eaf45dc7fac7c03743d7a7504010aed6.png) **Dynamic Signal Assistant** Sienovo Dynamic Signal Assistant is an on-demand software tool designed for dynamic signal acquisition modules such as PCI/PXI-9527. In addition to displaying real-time visual data on screen, the Dynamic Signal Assistant features a Windows-based configuration interface (for parameter settings) and an instrument-like user interface (enabling basic wa --- ## 【Domestic Virtual Instrument】DSP+ARM+FPGA-based Solution for Sound and Vibration Signal Acquisition - URL: https://intl.sienovo.cn/blog/130510976 - Date: 2023-05-25 - Tags: #FPGADev, #DomesticDAQ, #VirtualInstrument, #DomesticVirtualInstrument ## Sound and Vibration Sound and vibration products can connect microphones and accelerometers to acquire acoustic and vibration signals. These products can be used for audio testing, machine condition monitoring, and Noise, Vibration, and Harshness (NVH) applications. Provides dynamic signal acquisition for sound and vibration applications based on CompactDAQ and CompactRIO systems. C Series sound and vibration input modules integrate software-selectable AC/DC coupling, IEPE open/short detection, and IEPE signal conditioning. Input channels allow for synchronous signal measurement. Each channel also features a built-in anti-aliasing filter that automatically adjusts to the sample rate. These modules are compatible with smart TEDS sensors. C Series sound and vibration input modules also include NI-DAQmx drivers and configuration utilities to simplify setup and measurement. NI-DAQmx supports NI programming environments as well as Python, ANSI C, C#.NET, and MathWorks MATLAB ® softwa --- ## [Domestic Virtual Instruments] Design of a Dual-Channel 6.4GSPS High-Speed Data Acquisition Module Based on FPGA+JESD204B Clock (Part 2) Research on JESD204B Link Establishment and Synchronization Process - URL: https://intl.sienovo.cn/blog/130476877 - Date: 2023-05-25 - Tags: #FPGADev, #HighPrecisionADC, #DomesticVirtualInstrument ## Design of Acquisition and Data Reception Circuit Based on JESD204B This article is Part 2 of a series on building a dual-channel 6.4 GSPS high-speed data acquisition module using FPGA and JESD204B. Here we focus on the JESD204B protocol internals: how the interface is structured, how a link is established from scratch, and how multi-device synchronization is achieved using deterministic latency under Subclass 1. Engineers integrating high-speed ADCs such as the TI ADC12DJ3200 into FPGA-based acquisition systems will find the link bring-up sequence and SYSREF calibration procedure especially practical. --- ## 3.1 JESD204B Protocol Overview To address the ever-increasing data throughput demands of high-sampling-rate, high-resolution data converters, the JEDEC association developed **JESD204** — a high-speed serial communication protocol bridging data converters and logic devices — and has released successive revisions since. The second revision, **JESD204B**, has been widely adopt --- ## [Domestic Virtual Instrument] High-Precision 32-Bit Data Acquisition Solution Based on DSP+FPGA+ADS1282 (Part 3): System Performance Testing - URL: https://intl.sienovo.cn/blog/130432458 - Date: 2023-05-25 - Tags: #FPGADev, #ADCPerformance, #DomesticVirtualInstrument ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130432458/01_9a2cfbafa78ee44bbb01818dafd9beea.png) **System Performance Analysis and Testing** This chapter first analyzes the circuit noise and temperature drift of the system, then conducts performance testing on the data acquisition system and performs analysis on the test data. **5.1 Noise and Temperature Drift Analysis of High-Precision AD Conversion Circuit** **5.1.1 Resistor Noise and Temperature Drift** **1. Resistor Noise** Resistors are a source of noise, the severity of which depends on resistance value, temperature, applied voltage, and resistor type. Proper selection of resistors is one of the most effective methods to avoid or reduce noise or distortion in signal paths. Thermal noise in resistors arises from the random motion of electrons within the conductor. The overall noise of a resistor consists of multiple components, with thermal noise being the most typical. A notable characteristic of thermal no --- ## 【Domestic Virtual Instrument】DSP+FPGA+ADS1282-based 32-Bit High-Precision Data Acquisition Solution (II) Analog Circuit Design - URL: https://intl.sienovo.cn/blog/130419477 - Date: 2023-05-25 - Tags: #FPGADev, #ADS1282, #HighPrecisionADC, #DomesticVirtualInstrument This article walks through the analog front-end and ADC circuit design for a 32-bit high-precision data acquisition system built around the TI ADS1282 delta-sigma ADC, an FPGA, and a DSP. Part II focuses on the signal-conditioning chain from sensor current output all the way to the FPGA's SPI interface, covering component selection rationale, filter design, ADC operating-mode selection, pin-level interfacing, SPI timing constraints, multi-channel synchronization, and register-level control. ## System Architecture Overview Figure 4.1 shows the hardware signal block diagram. The digital signal processing board centers on two processing chips: an FPGA and a DSP. The FPGA acts as the bridge between the DSP and all peripheral interfaces and handles data pre-processing, while the DSP is the computation core. The FPGA receives data from external devices over various data buses, performs packetization and other pre-processing, and stores results in designated on-chip memory. The DSP reads t --- ## [Domestic Virtual Instrument] Zynq-Based Radar 10Gbps High-Speed PCIe Data Acquisition Card Solution (Part 3) Software Design - URL: https://intl.sienovo.cn/blog/130786114 - Date: 2023-05-24 - Tags: #DriverDev, #DomesticVirtualInstrument **4.1 Introduction** This chapter presents the system software design based on the analysis conclusions from Chapter 2. The software design encompasses logic design, embedded software design, and host PC software design. In the logic design, the ADC module, Aurora module, DDR3 SDRAM module, and PCIe module are analyzed and designed. Based on the IP cores provided by Vivado, the logic code for each module is implemented, and data interfacing issues among modules are resolved. The embedded design involves system and kernel porting, enabling system boot-up through the PS core of Zynq. For the host PC software design, driver development tools are first introduced, followed by an overview of the overall host software architecture. **4.2 Logic Software Design** Since the data on the FMC interface of the carrier card depends on the type of mezzanine card connected, either the ADC module or the Aurora module is selected accordingly. When an AD mezzanine card is connected, the ADC module is --- ## Domestic Virtual Instruments: Zynq-based Radar 10Gbps High-Speed PCIe Data Acquisition Card Solution (Part 2) Hardware Design - URL: https://intl.sienovo.cn/blog/130781818 - Date: 2023-05-24 - Tags: #FPGADev, #DomesticVirtualInstrument This article details the hardware design of a Zynq-based 10 Gbps PCIe radar data acquisition card, covering chip selection, power architecture, clock distribution, high-speed interfaces, DDR3 memory, and the design of both the ADC daughter card and fiber-optic daughter card. Engineers working on FPGA-based data acquisition systems will find a practical reference for how to partition carrier-board and daughter-card responsibilities, select appropriate power management ICs, and configure the Xilinx Zynq-7100 SoC for high-throughput signal capture. ## 3.1 Introduction The hardware design of the acquisition card is the foundation for realizing its capture functions. A well-conceived hardware design makes the acquisition feature easier to implement and streamlines subsequent software development. This chapter builds on the hardware architecture described in Chapter 2 and provides a detailed walkthrough of chip selection, configuration, and specific circuit design for both the carrier boar --- ## Domestic Virtual Instruments: Zynq-based Radar 10Gbps High-Speed PCIe Data Acquisition Card Solution (Part 1) Overall Design - URL: https://intl.sienovo.cn/blog/130781495 - Date: 2023-05-24 - Tags: #FPGADev, #DomesticVirtualInstrument ## Introduction This article details the overall architecture of a Zynq-based high-speed PCIe data acquisition card designed for a radar emitter identification project. The card must capture, buffer, and transfer radar intermediate-frequency (IF) signals at sustained throughputs exceeding 19.2 Gbps — a requirement that drives every major design decision from ADC selection through PCIe lane count. The design uses a Xilinx Zynq7000 SoC as its central processor, combining an FPGA fabric (PL) with dual ARM Cortex-A9 cores (PS) on a single chip, and connects to an off-card recognition platform over a PCIe 2.0 x8 link. --- ## 2.1 Introduction This project originates from a radar emitter identification initiative that requires acquisition, transmission, and storage of radar emitter intermediate-frequency (IF) signals. Based on those project requirements, this chapter introduces the overall design solution for the data acquisition card, covering both hardware and software. The chapter begi --- ## Domestic Virtual Instrument: Design of a ZYNQ-based High-Speed Data Acquisition System for Power Quality - URL: https://intl.sienovo.cn/blog/130781294 - Date: 2023-05-24 - Tags: #FPGADev, #ZYNQ+AD7606, #DomesticVirtualInstrument With the continuous increase of nonlinear loads in power grids, power quality issues are becoming increasingly severe. High-precision data acquisition systems can provide accurate data support for power quality analysis, serving as a critical basis for addressing power quality problems. By comparing existing high-speed acquisition system designs, the main control circuits often adopt architectures such as ARM microcontrollers paired with AD converter chips, ARM+DSP paired with converter chips, or FPGA+DSP paired with AD converter chips \[1-5\]. ARM possesses excellent decision-making and control characteristics and is widely used in industrial control, but its data processing speed is slow and cannot meet the real-time requirements of systems. Due to the serial instruction stream characteristic of DSPs, complex data processing can only be performed in low-speed systems. FPGAs, with their full programmability and parallel data processing capabilities, are increasingly favored in digita --- ## [Domestic Virtual Instrument] 4-Channel 12.6GSPS Sampling Rate 16-bit DA Playback FMC JESD204B Interface Daughter Card Module Based on AD9172/AD9176 - URL: https://intl.sienovo.cn/blog/130698466 - Date: 2023-05-24 - Tags: #FPGADev, #AD9172, #DomesticVirtualInstrument **Board Overview** The FMC_XM131 is a 4-channel, 12.6GSPS sampling rate, 16-bit DA playback FMC daughter card module. This board adheres to the FMC+ standard, complying with the VITA57.4 specification. It can serve as an ideal I/O module for coupling to an FPGA frontend. Its 16-lane JESD204B interface connects to the FPGA's high-speed serial port GTH via the FMC+ connector. The board supports an onboard programmable sampling clock and an external reference clock. Multiple boards can achieve output synchronization through trigger (input/output) signals. The board's four analog signal outputs are routed through 50Ω characteristic impedance SSMC RF connectors and utilize AC transformer coupling. This board can be widely applied in scenarios such as radar simulators, communication and navigation simulators, and jammers. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130698466/01_a8245c73fe875b27701d316dd3077ff8.png) **Software Support** * Optional integrated board-level --- ## Domestic Virtual Instrument: 4-Channel 3.2 GSPS (or configurable to 2-Channel 6.4 GSPS) 12-bit ADC Acquisition FMC+ Daughter Card Module - URL: https://intl.sienovo.cn/blog/130698334 - Date: 2023-05-24 - Tags: #FPGADev, #DomesticVirtualInstrument Board Overview The FMC_XM134 is a 4-channel 3.2 GSPS (or configurable to 2-channel 6.4 GSPS) 12-bit ADC acquisition FMC+ daughter card module. This board adheres to the FMC+ standard and complies with the VITA57.4 specification. It can be coupled as an ideal I/O module to the FPGA front-end. After digitization, RF analog signals are transmitted to the FPGA via a 16-lane JESD204B interface. The board supports a maximum of 2 channels of 6.4 GSPS RF direct sampling, with a -3dB analog input bandwidth of up to 8 GHz. Signals with instantaneous bandwidths below 3 GHz can all be digitized within the first Nyquist zone. The board supports an on-board programmable sampling clock and an external reference clock. Multiple boards can also perform synchronized acquisition via trigger (input/output) signals. The board's 4 analog signal inputs are connected via 50Ω characteristic impedance SSMC RF connectors, using AC transformer coupling. The board can be widely used in radar signal processing, e --- ## Domestic Virtual Instruments: Application of China-made Data Acquisition Virtual Instrument Boards with LabVIEW - URL: https://intl.sienovo.cn/blog/130677092 - Date: 2023-05-24 - Tags: #FPGADev, #VirtualInstrument As is well known, virtual instrument technology is a system where software defines the functions of general-purpose test hardware according to user requirements. By applying reconfigurable hardware to a virtual instrument system, engineers can use software to develop algorithms and deploy them to an embedded chip, thereby extending the reconfigurability of virtual instrument software to hardware. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130677092/01_8ec2d4118b21595293f6013bee8d12d8.png) Previously, only hardware designers familiar with low-level programming languages like VHDL could leverage FPGA technology. However, engineers can now use LabVIEW FPGA (a graphical development environment developed by NI for Field-Programmable Gate Array chips) to develop custom control algorithms and download them to FPGA chips. LabVIEW FPGA is a graphical programming environment that allows users to easily configure the FPGA during the testing process. The system automatically --- ## [Domestic Virtual Instrument] FPGA+JESD204B Clock Dual-Channel 6.4GSPS High-Speed Data Acquisition Design (Part 3) Continuous Multi-Segment Triggered Storage and Transmission Logic Design - URL: https://intl.sienovo.cn/blog/130608191 - Date: 2023-05-24 - Tags: #FPGADev, #DomesticVirtualInstrument This chapter delves into the design of continuous multi-segment triggered storage for high-speed data acquisition, specifically targeting 80 channels of parallel sampled data at an 80MHz data rate with a 12-bit width. We will explore the overall framework, the critical role of the Memory Interface Generator (MIG) user interface, its settings, and read/write timing. A significant focus will be on the design of the data cross-clock domain module and the memory control module, both essential for achieving robust continuous multi-segment triggered storage. Finally, we will touch upon the high-speed serial data transmission of this triggered data to an AXIe carrier board. ## 4.1 Continuous Multi-Segment Triggered Storage ### 4.1.1 Overall Framework Design for Triggered Storage For high-speed data acquisition systems, implementing triggered storage is crucial for capturing transient events or specific data segments. This design ultimately leverages DDR3 memory modules for the triggered st --- ## 【Domestic Virtual Instruments】Design of Data Acquisition and Analysis Software in a Domestically Developed PXI Test System - URL: https://intl.sienovo.cn/blog/130551858 - Date: 2023-05-24 - Tags: #DataAnalytics, #DataVisualization, #PXI, #DataAcquisition, #DomesticVirtualInstrument Requirements Analysis and Overall Design of the Data Acquisition and Analysis System The Data Acquisition and Analysis System is the host computer software subsystem of the PXI test system, playing a crucial role within the system. This chapter will first briefly introduce the PXI test system, analyze its overall structure and functions, and explain the relationship between the data analysis system and the PXI test system; then, it will analyze the functional and non-functional requirements of the data acquisition and analysis system; finally, it will present the overall architecture, functional structure, and data structure design of the system. 2.1 Introduction to the PXI Test System The PXI test system is an automatic test equipment for a certain weapon control system. Its function is to perform the acquisition and analysis of six types of interface data from the weapon control system under test: analog quantities, switch quantities, SDC data, 1553B bus data, RS422 serial port da --- ## Application of SylixOS + Phytium All-Domestic Real-time Operating System and All-Domestic Motherboard Industrial Control Solution in Power Products - URL: https://intl.sienovo.cn/blog/130829864 - Date: 2023-05-23 - Tags: #DomesticRTOS, #FullyDomesticMotherboard ****Introduction to SylixOS（M********S-RTOS********）Applications in Power Products**** I. Traditional Power Grid Devices: 1. Relaying protection, measurement & control, stability control, PMU, time synchronization, fault recording, and other devices (transmission and substation) Typically, AMP solutions are used, with a few customers using SMP solutions. In November 2019, China's first 100% domestically produced 500kV relay protection device using SylixOS was commissioned in Henan (Xuji Group). A month later, 100% domestically produced relay protection devices using SylixOS from customers like Sifang Automation and NARI Group were successively deployed at Foshan Sanzhou Substation and Guangzhou Liede Substation. The software block diagram is as follows: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130829864/01_dd938e408e57f90e61f317d58f60d0b0.png) In October 2020, customers such as NARI Technology, Jicheng Electronics, and Dongfang Electronics conducted network a --- ## Design of a Robotic System with Handheld Control Based on IMX8 and Real-time EtherCAT - URL: https://intl.sienovo.cn/blog/130829782 - Date: 2023-05-23 - Tags: #Smartphone, #Robotics Structure: 1. The following structure is a control handle, used to acquire human hand motion signals, transmit them to the host computer, and remotely control other devices. 2. The handle incorporates a robotic arm with 4 motor-driven revolute joints, featuring built-in 16-bit resolution rotary encoders to record angular displacement. 3. The host computer connects to the handle motors, instrument motors (actuators controlled by the handle's motion output), gantry motors (for linear motion controlled by the handle), and the electrosurgical unit (for on/off control via the handle). ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130829782/01_debfaa36acf2d7e72b95643345d08c2b.png) Functional Modules: * Forward Control (Handle as Control End): 1. Handle rotary encoder (5) angular displacement signals control the instrument motors. 2. Handle buttons: control the equipment's gantry motors. 3. Handle buttons: active braking and release of the handle motors. 4. Han --- ## CameraLink HD Medical Imaging Analysis Module - URL: https://intl.sienovo.cn/blog/130739797 - Date: 2023-05-18 - Tags: #cameralink The FMC-XM202 is a sub-card module based on the FMC interface standard, supporting 1-channel CameraLink Full mode (or 2-channel CameraLink Base mode) acquisition and 1-channel HDMI (DVI) video output. This module features two CameraLink ports (SDR, 26-PIN) and can be configured via hardware for 1-channel Full input or 2-channel Base mode input. The CameraLink interface supports 80-bit Deca mode (i.e., Full Plus mode). The module supports 1-channel DVI video output (HDMI connector), with a maximum resolution of 1080P. This module is specifically designed for FMC mezzanine cards, and by pairing it with different FMC carrier cards, a CameraLink video interface-based image analysis and verification platform can be quickly established. It can be widely used in scientific research, education, and the development of high-end video and image products. It is a standard FMC sub-card, compliant with the VITA57 specification. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130739797 --- ## AD96808 FMC Module, Featuring 8-Channel, 14-bit, 500MSPS/1GSPS/1.25GSPS ADC Acquisition - URL: https://intl.sienovo.cn/blog/130739308 - Date: 2023-05-18 - Tags: #5G Module Overview The FMC-XM148 is a JESD204B interface FMC mezzanine module based on the VITA57.4 standard. This module provides 8-channel, 14-bit, 500MSPS/1GSPS/1.25GSPS ADC acquisition capabilities. The ADC device on this board uses ADI's AD9680 chip, with a full-power -3dB analog input bandwidth of up to 2GHz. The ADC's host interface to the FPGA is interconnected via 16 high-speed serial GTX transceivers. This board is primarily designed for applications such as communications and wireless infrastructure, radar, wideband communications, millimeter-wave communications, and automated test equipment. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130739308/01_e5d8f212d321b5698c5d1fe637b8557f.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130739308/02_571b6d11b945e0345f78eb702e75cd58.png)   Software Support  Optional integrated Board Support Package (BSP):  Supports Xilinx development boards;  Supports Kintex UltraScale, etc.;  Customize --- ## AD9680 + JESD204B Interface + FPGA FMC High-Speed Data Acquisition Board - URL: https://intl.sienovo.cn/blog/130697868 - Date: 2023-05-16 - Tags: #FPGADev Board Overview: 【FMC\_XM155】 FMC\_XM155 is a VITA57.1 standard-based FMC daughter card module that implements 2-channel, 14-bit, 500MSPS/1GSPS/1.25GSPS DC-coupled ADC synchronous acquisition. This module complies with the VITA57.1 specification and can be directly used with an FPGA carrier card. The board's ADC device uses Analog Devices' AD9680 chip, which features two analog input channels and two JESD204B output data lane pairs, capable of sampling broadband analog signals up to 2GHz. The ADC front-end employs a wideband, low-noise, low-power fully differential amplifier with a gain-bandwidth product of up to 8GHz, offering excellent linear performance and up to 12dB gain from DC to 2GHz. This board is primarily designed for applications such as radar, broadband communications, millimeter-wave communications, and automated test equipment. \[FMC\_XM121\] FMC\_XM121 is an FMC standard-compliant daughter card module that implements 2-channel, 14-bit, 1GSPS ADC synchronous acquisitio --- ## Software Defined Radio Processing Platform Based on MPSOC, C6678, and High-Precision AD/DA - URL: https://intl.sienovo.cn/blog/130685218 - Date: 2023-05-15 - Tags: #FPGADev Board Overview The VPX_XM630 is a high-speed signal processing platform based on the 6U VPX bus architecture. This platform utilizes a Xilinx Kintex UltraScale series FPGA (XCKU115) as the main processor to perform complex data acquisition, playback, and real-time signal processing algorithms. A high-performance embedded processor ZU9EG with an ARM core is employed as a co-processor to handle communication and management functions. The main processor XCKU115 on this platform is externally connected to two groups of 72-bit DDR4 SDRAM for ultra-large capacity data caching, with a data cache bandwidth of up to 2400MHz. The PL (Programmable Logic) side of the co-processor ZU9EG supports two groups of DDR4 SDRAM. The PS (Processing System) side of this co-processor is a powerful ARM processor, featuring one 64-bit quad-core ARM Cortex-A53 processor, one dual-core ARM Cortex-R5 real-time processor, and one ARM Mali™-400MP graphics processor. The PS side is externally connected to 72-bit DDR --- ## High-Performance Integrated Video and Image Processing Platform Based on HiSilicon Hi3531 ARM + Kintex-7 FPGA - URL: https://intl.sienovo.cn/blog/130677528 - Date: 2023-05-15 - Tags: #FPGADev Board Overview XM703 is a self-developed high-performance integrated video and image processing platform based on the PCIe bus architecture. This platform combines Xilinx's high-performance Kintex UltraScale series FPGA with Huawei HiSilicon's advanced video processor. The HiSilicon Hi3531DV200 integrates a powerful quad-core ARM A53 processor and a neural network engine, supporting various intelligent algorithm applications. It features multiple MIPI video interfaces, overcoming performance bottlenecks associated with digital interface video input, and includes a high-performance H.265 video codec engine that significantly enhances traditional video and image processing algorithms in both effect and performance. The board integrates a powerful FPGA processor primarily responsible for video and image processing algorithms. It is equipped with 32 GByte of large-capacity DDR4 SDRAM data buffer, supporting up to 32 GByte/s memory bandwidth—breaking through traditional bandwidth limitat --- ## Implementation Solution for a Large-Capacity Solid-State Storage Board Based on NXP + FPGA - URL: https://intl.sienovo.cn/blog/130653947 - Date: 2023-05-13 - Tags: #FPGADev 1 Overview In recent years, large-capacity data storage devices have primarily relied on stacked combinations of mechanical hard drives due to limitations in software and hardware development. Mechanical hard drives use platters as the storage medium and mechanical motors, suffering from drawbacks such as low vibration resistance, poor low-temperature performance, and high noise. Solid-state drives (SSDs), on the other hand, use semiconductors as both the storage medium and control carrier. Lacking mechanical components, they offer advantages such as shock resistance, wide operating temperature range, noiseless operation, high reliability, and energy efficiency, playing an increasingly significant role in large and complex electronic equipment. Large-capacity solid-state storage technology is attracting widespread attention. This article, in response to the needs of a specific project, adopts an implementation method where an ARM processor and a Field-Programmable Gate Array (FPGA) --- ## Intel i3/i5/i7 + FPGA-based Vision Controller with 4 POE GigE Ports - URL: https://intl.sienovo.cn/blog/128275849 - Date: 2023-05-13 - Tags: #5G, #intel i3, #fpga The XM-5143 is a high-performance industrial computer designed for GigE camera applications in the machine vision industry. It can utilize Intel 6th/7th generation 65W high-performance CPUs to handle rapid inspection tasks. It features four independent Intel network chips and supports PoE power supply, which reduces wiring. It is also equipped with fast isolated programmable DI/O chips. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128275849/01_733a712237137554aba9790243323c6e.png) XM-5143 Specifications Product Type Machine Vision Controller Protection Rating IP4X Chipset Intel® H110 CPU 6th Gen i3-6100, i5-6500, i7-6700 7th Gen i3-7100, i5-7600, i7-7700T Memory Dual-channel DDR SO-DIMM 2133MHz, up to 32GB BIOS AMI UEFI GbE x2 Intel i211 RJ45 Gigabit Ethernet PoE x4 Intel i211 RJ45, max 15W DC48V output per port USB 3.0 x4 Front Panel USB 2.0 x1 Internal DI x8, 2ms response time, 2500Vrms isolation DO x8, 2ms response time, 2500Vrms isolation Serial Port --- ## Robot Controller Based on Intel x86 + FPGA, Supporting SLAM, LiDAR, and AI Acceleration - URL: https://intl.sienovo.cn/blog/128270208 - Date: 2023-05-13 - Tags: #intel, #RobotController ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128270208/01_9a1c05827da525a7365e8ef2d4edd5ed.png) The 9th/8th gen Intel® Core™ i7/i5/i3 & Celeron® XM-5149 is an industrial computer product designed specifically for the robotics industry. Its high-performance processing capabilities accelerate AI training, while its diverse I/O interfaces support rich peripherals such as cameras and radar. The fully enclosed chassis allows the system to operate stably at high temperatures without throttling. **Product Specifications** Chipset Intel® H310 CPU Supports Intel Gen8/9 Coffee Lake LGA1151 Core i3/i5/i7/Pentium/Celeron CPUs with TDP 35–65W Memory Dual-channel SODIMM DDR4, up to 64GB maximum capacity BIOS AMI UEFI GbE x2 Intel i211 RJ45 Gigabit Ethernet USB 3.0 x6 USB 2.0 x2 Serial Ports x4 RS232 terminal blocks (COM1 & COM2 support RS232 or optional RS485) SATA 3.0 x1 2.5-inch SSD or HDD mSATA x1 Full-size, supports SANDISK protocol, maximum speed 3Gb/s Po --- ## Key Considerations for Custom Industrial Motherboard Selection - URL: https://intl.sienovo.cn/blog/130629606 - Date: 2023-05-11 - Tags: #IndustrialMotherboard, #PartSelection, #Customization Industrial motherboards are the core components of industrial PCs (IPCs). IPCs integrate various components like CPUs and external devices through the industrial motherboard to form a complete system. Therefore, the overall operating speed and stability of an IPC largely depend on the performance of the industrial motherboard. Industrial motherboards are widely used in complex environments, leading to high user demands for their functionality, compatibility, and reliability. The key considerations for industrial motherboard customization are as follows: I. Size Specifications Industrial motherboards come in various form factors, including 3.5-inch, 5.25-inch, ATX, Micro-ATX, half-size cards, full-size cards, and other specifications. Classified by chip type: X86 architecture, ARM architecture, etc. These can meet the requirements of various operating environments and performance demands. II. Components Industrial motherboard components differ from commercial-grade materials; they --- ## RK3588s-based Industrial Gateway Switch with High AI Computing Power and Multi-port Networking, Supporting 5 Gigabit HD Cameras - URL: https://intl.sienovo.cn/blog/130620966 - Date: 2023-05-11 - Tags: #AI, #Compute RK3588/RK3588S AI BOX Functional Interface Description Interface Requirements Function Definition and Requirements Remarks Cost and Goals Hardware design aims for full domestic production. 6+32GB Version RK3588S PCBA Dimensions 146*102 Silkscreen Version Number RK3588S AI BOX V1.0 eMMC Supports SanDisk SDINBDA4-32/64/128G 4GB-8GB Standard 8GB 5 Gigabit Ethernet Ports 1 WAN, 4 LAN One port requires PCIe expansion WIFI+BT Supports WIFI6 & BT5.0, domestic Aicov AIC8800D HDMI 2.1 Out Interface Supports 1 HDMI output interface, supports 8K output MIPI Camera*2 Board-to-board connector MIPI, LVDS Interface Requires LVDS voltage jumper eDP Interface Reserved connector on board Backlight Control Reserved connector 6-pin Touchscreen Interface Reserved connector on board USB Interface 4 USB 3.0 interfaces USB power supply needs to consider supporting mobile hard drive power Type-C Interface For flashing and supporting ADB debug port TF Card Supports 128GB --- ## RK3588 Flagship 32TOPS AI Multi-Network Port Edge Intelligent Gateway Switch - URL: https://intl.sienovo.cn/blog/130614745 - Date: 2023-05-11 - Tags: #AI, #RK3588, #MultiEthernet, #Image #### 32TOPS Edge Intelligent Gateway Launched, Empowering Digital Transformation Across Multiple Industries, Reducing O&M Costs and Increasing Efficiency, Powered by the Flagship RK3588 Chip The XM-RK3588 Edge Intelligent Gateway, powered by the Rockchip RK3588 chip, offers computing power expandable to 32TOPS, **making it suitable for digital transformation in fields such as electric power and energy, smart transportation, smart cities, smart security, smart healthcare, and industrial internet.** Currently, Xinmai has launched a series of edge intelligent gateway products based on Rockchip RK3568, RK3566, RV1126, and other platforms. These products cover various computing power requirements and cater to high-end, mid-range, and entry-level performance needs with dual or multi-network ports. They have been deployed and applied in areas such as intelligent O&M, digital cities, smart security, smart factories, and smart transportation. The highlights and application cases of several e --- ## Vehicle-mounted Railway M12 Industrial Switch 3U Rail Transit Board-Level Switch Design Solution - URL: https://intl.sienovo.cn/blog/130593489 - Date: 2023-05-10 - Tags: #Networking, #VehicleSwitch, #TSN ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130593489/01_b9d36f6af2fd013b22f8007bd9ab3836.png) Supports dual power redundancy Supports Bypass Ethernet data communication equipment specifically designed and manufactured for rail transit applications Train-level backbone Ethernet core equipment implemented according to IEC61375-2-5 and IEC61375-2-3 protocols China Railway Product Certification ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130593489/02_aaec85bc3b2ad88d4173b1a452a68294.png) The XM-5145 industrial switch is a Layer 2 managed switch specifically designed and developed for harsh environments such as rail transit, marine, and vehicle-mounted applications. The product design complies with rail transit industry certifications. The product uses M12 connectors to ensure stable network communication in vibrating environments. The entire unit adopts a fanless passive cooling design, ensuring long-term stable operation in working environments f --- ## AI Cross-Modal Person Re-Identification Method and Application Based on RK3588+TensorFlow - URL: https://intl.sienovo.cn/blog/130506112 - Date: 2023-05-05 - Tags: #AI, #DeepLearning, #ComputerVision Abstract: Cross-modal person re-identification (cm-ReID) technology aims to identify the same person across images from different modalities, such as visible light and infrared. It has important applications in intelligent systems and equipment for human-machine collaboration, the Internet of Everything, cross-domain integration, and ubiquitous intelligence. This paper proposes a data augmentation method for cross-modal person re-identification that performs data augmentation in the wavelength domain while preserving the structural information of visible images to bridge the gap between different modalities. Based on this, an edge AI terminal was designed and implemented using Rockchip's RK3588 chip, and the cross-modal person re-identification algorithm was deployed on it. 0 Introduction Person re-identification (Re-ID) is widely used in various applications such as video surveillance, security, and smart cities. It aims to retrieve a person of interest across multiple non-overlappi --- ## Domestic Alternative Solution for NI Virtual Instrument High-Precision Data Acquisition Card Controllers - URL: https://intl.sienovo.cn/blog/130503404 - Date: 2023-05-05 - Tags: #NI, #VirtualInstrument, #ImportSubstitution, #Domestic ### What is CompactDAQ? CompactDAQ systems can acquire and deliver validated data to meet your testing needs, regardless of distance or environment. These customizable, portable solutions consist of various data acquisition modules that enable synchronized measurements over a network. They help you digitize data and can be deployed closer to sensors, minimizing noise and simplifying field wiring. CompactDAQ offers a cost-effective benchtop measurement approach. You can combine sensor-specific conditioned I/O modules with software optimized for DAQ applications. **Ideal for:** * High-channel-count distributed DAQ applications  * Benchtop testing and measurement  * Mixed-sensor measurements  ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130503404/01_762693b47d65c79619a363e6e7458542.png) Accurate Sensor Measurements NI offers over 70 high-quality C Series I/O modules with built-in sensor or signal conditioning capabilities. You can mix and match --- ## Semiconductor Motion Stage High-Speed Data Acquisition FPGA Design Based on DSP+FPGA+AD+EnDat (Part 2) - URL: https://intl.sienovo.cn/blog/130413201 - Date: 2023-04-27 - Tags: #FPGADev, #dsp+fpga, #endac, #adc 4 System FPGA Program Design 4.1 Design Methodology and Logic Design Overview 4.1.1 Development Environment and Design Flow Quartus II is Altera's integrated development tool. It integrates all tools and third-party software interfaces required during FPGA/CPLD development, supporting multi-clock analysis, LogicLock block-based design, System-on-a-Programmable-Chip (SOPC), embedded in-system logic analyzer SignalTap II, power estimator, and various other advanced tools. Quartus II offers rich input methods, including schematic, VHDL, Verilog HDL, and other forms for logic program design, making FPGA program development very convenient for designers. The LogicLock feature partitions different logic into distinct FPGA regions, allowing for independent design, implementation, and optimization without modules affecting each other. If an error occurs during design integration, only the specific module needs modification, without impacting other modules. The SignalTap II in-system logic a --- ## Lithography Machine High-Speed Data Acquisition and Servo Interface System Design Based on DSP+FPGA+AD+EnDat Fiber Optic Transmission (Part 1) - URL: https://intl.sienovo.cn/blog/130412618 - Date: 2023-04-27 - Tags: #dsp+fpga, #HighSpeedDAQ, #endac, #SemiconductorStage The lithography machine dual-stage motion control system involves highly complex control tasks, demanding extremely high speed and precision. Furthermore, the equipment is bulky, with significant spatial distances between various sensors and actuators, numerous cables, and severe on-site electromagnetic interference. To meet the control system requirements, this paper leverages the high-speed floating-point computing capability of DSP, the powerful parallel processing capability of FPGA, and the long transmission distance and strong anti-interference characteristics of fiber optic communication, proposing a data acquisition and servo interface system solution based on FPGA+DSP+high-speed fiber optic transmission. The entire system is divided into two parts: the core computing and control unit and the remote sensing and servo control unit. Based on the overall system design, the system hardware circuits were designed, including FPGA system circuits, DSP system circuits, fiber optic se --- ## Architecture and Operating Principles of a DSP+FPGA+ADC-Based High-Speed Data Acquisition System - URL: https://intl.sienovo.cn/blog/130412509 - Date: 2023-04-27 - Tags: #FPGADev ## Architecture and Operating Principles of a DSP+FPGA+ADC-Based High-Speed Data Acquisition System High-speed data acquisition systems are critical components in various industries, including industrial automation, scientific research, and medical applications. These systems require high-speed data processing and analysis capabilities to capture and process large amounts of data in real-time. In this article, we will explore the architecture and operating principles of a high-speed data acquisition system based on a DSP+FPGA+ADC configuration. ### System Hardware Architecture The hardware composition of the high-speed data acquisition platform, which employs a time-interleaved sampling structure, is shown below: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130412509/01_29884ef86edf934e2152e80ea93233d2.png) The high-speed data acquisition system is mainly divided into four modules: #### Power Monitoring and Management Module The power monitoring and management mo --- ## VPX and PXI Boards: High-Precision Data Acquisition and Virtual Instrument Design - URL: https://intl.sienovo.cn/blog/130379243 - Date: 2023-04-26 - Tags: #EmbeddedHardware, #PXI ## Innovative Cooling Mechanism Xinmai Technology has adopted an innovative thermal design. The cooling fan is located at the rear of the chassis, drawing cooling air in through bottom intake vents and exhausting it from the rear. This new design provides consistent cooling airflow to every PXI slot, offering excellent cooling capacity. When installed in a rack, this novel cooling design minimizes the intake of hot air exhausted by other equipment from the rear of the chassis, thereby maintaining a stable internal temperature. ### Applications ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130379243/01_3556172b7379d7a56886f0522cee1658.jpeg) ## Smart Chassis Management To ensure system operational stability, an intelligent monitoring system is designed to provide protection and system regulation functions. Five sets of sensors are configured above the backplane to monitor temperature changes within the chassis. Through configurable settings, the fan speed is increase --- ## LS1028-Based TSN Switch Software System Design and Implementation (Part 3) - URL: https://intl.sienovo.cn/blog/130251781 - Date: 2023-04-19 - Tags: #linux, #TSN NXP launched OpenIL as a Linux distribution for industrial applications. New additions in OpenIL include extensions supporting real-time operating systems and Time-Sensitive Networking for automated OEMs in industrial plants. The biggest advantage of OpenIL as an open industrial Linux system is that it removes obstacles to real-time computing in networks. OEMs will gradually enter the Industry 4.0 era by leveraging the standard, community-driven OpenIL distribution. 4.1 Basic Design Philosophy of TSN Switch Software In this paper, the switch software supporting the TSN system uses the Open Industrial Linux system (OpenIL). This is because a key characteristic of TSN is strong real-time performance, and OpenIL is a specialized Linux version developed for industrial applications. It extends real-time operating systems and supports Time-Sensitive Networking for automated OEMs in industrial plants (including stream filtering and policing, time-aware shaper, and 802.1AS time synchronizat --- ## LS1028 TSN Switch Hardware System Design and Implementation (Part 2) - URL: https://intl.sienovo.cn/blog/130251705 - Date: 2023-04-19 - Tags: #Networking, #TSN, #LS1028 3.1 LS1028A Chip Research Currently, there are few chips on the market that support TSN systems. Among the two larger companies, Broadcom launched its StrataConnect BCM53570 series of Ethernet switches in 2017. The new technologies supported by this series aim to help users address the networking challenges posed by emerging applications such as IoT, automotive networks, and video. The LS1028A, on the other hand, is built on NXP's Layerscape family of SoCs and adds many important features, including two upgraded 64-bit ARM® Cortex-v8 processor cores for real-time industrial control, a dedicated 4-port TSN switch to handle TSN L2 data, two independent TSN Ethernet controllers to support IT and OT network convergence, an integrated 3D GPU and LCD controller for human-machine interaction systems, and the ability to function as a TSN END POINT. The LS1028A provides rich I/O interfaces and high-speed interconnects, meeting the demands of various industrial IoT scenarios, as shown in Figur --- ## Implementation Method for ARM+FPGA+AD Multi-Board Multi-Channel Synchronous Acquisition Based on JESD204B Protocol - URL: https://intl.sienovo.cn/blog/130251551 - Date: 2023-04-19 - Tags: #FPGADev 0 Introduction With the continuous advancement of digital signal processing technology, the processing of digital signals has become a fundamental method in most current engineering applications. Since analog signals are the original signals in real life, for the feasibility of engineering research, analog signals must be converted into digital signals for processing in engineering. Analog-to-Digital (AD) conversion, as a critical link in converting analog signals to digital signals, has also become an important research subject in engineering \[1\]. The interfaces of data sampling converters have evolved from traditional CMOS interfaces to differential LVDS interfaces. Due to the low speed of CMOS interfaces, the initial AD sampling rates were limited. Differential LVDS interfaces achieved higher data rate AD sampling. However, with the rapid development of current AD converters, higher sampling rates and higher channel density have become new demands. LVDS interfaces have become s --- ## LS1028+TSN+VxWorks Real-time System Solution - URL: https://intl.sienovo.cn/blog/130228181 - Date: 2023-04-19 - Tags: #tsn, #vxworks TSN (Time-Sensitive Networking) is gaining traction across various markets. It can provide real-time communication for new applications that previously didn't exist. For example, decoupling control functions from drives and moving them to edge computing. Next-generation automated controllers can process various workloads in parallel, such as video streams and control streams, run all deep learning algorithms on a single machine, and simultaneously communicate with other controllers in the factory. To ensure deterministic behavior in such an environment, real-time operating systems must be installed at both ends. For applications that require both time synchronization (coordinated events) and timeliness (timely events), such as robotic arms, motion controllers, or autonomous vehicles, it is necessary to combine TSN with the VxWorks Real-Time Operating System (RTOS) to synchronize device networks and thus enhance deterministic behavior. Combining TSN with the real-time behavior of the --- ## LS1028 TSN Time-Sensitive Networking Switch Solution (Part 1) Introduction to TSN - URL: https://intl.sienovo.cn/blog/130228270 - Date: 2023-04-18 - Tags: #tsn, #Networking 2.1 Introduction to Time-Sensitive Networking The predecessor of the Time-Sensitive Networking group was AVB, which stands for Ethernet Audio/Video Bridging (Ethernet AVB) **\[10\]**. Building upon traditional Ethernet, it ensures Quality of Service (QoS) through precise time synchronization, bandwidth reservation, and traffic shaping, thereby supporting various network multimedia applications based on audio and video. Over the past decade, the demand for audio and video entertainment has intensified, rendering the original Ethernet, which was based on static, non-real-time data processing, unsuitable. Packet order and latency were not prioritized. Although Layer 2 networks employed priority mechanisms and Layer 3 networks utilized QoS mechanisms, these could not eliminate resource contention issues between real-time data streams and ordinary asynchronous TCP (Transmission Control Protocol) traffic. The resulting latency and jitter significantly impacted the transmission of real-time --- ## DSP+FPGA-based Multi-axis Motion Control Platform (Part 1) Hardware Design - URL: https://intl.sienovo.cn/blog/130182973 - Date: 2023-04-16 - Tags: #FPGADev **2 Overall Scheme and Hardware Design of the Experimental Platform** 2.1.1 Functional Requirements Analysis of the Experimental Platform To facilitate research into multi-axis motion control technology and cultivate talent in this field, the experimental platform should be capable of achieving high-speed and high-precision control for multi-axis motion, while ensuring system openness and compatibility with various algorithms and parameter configurations. The experimental process should align with actual work processes. Before completing the control system design, software simulation should be performed to verify its effectiveness. In-depth research into the core control algorithms of the platform should enable the execution of classic and commonly used interpolation algorithms and acceleration/deceleration algorithms, while also integrating newer velocity look-ahead algorithms and curve fitting pre-processing algorithms, to compare experimental results. Furthermore, regarding hard --- ## Design of an Underwater Information Fusion System Based on DSP+FPGA+1553B Bus - URL: https://intl.sienovo.cn/blog/130182822 - Date: 2023-04-16 - Tags: #FPGADev In a large-scale underwater system, different communication protocols are typically adopted to suit the characteristics of various subsystems. Serial communication, with its strong anti-interference capability and long transmission distance, is suitable for subsystems requiring long-range communication. The MIL-STD-1553B bus offers extremely high reliability and real-time performance in data transmission, making it suitable for inertial navigation and fire control subsystems that demand high signal accuracy and real-time performance [1]. DSP can process data quickly and offers high integration and stability, making it a mainstream processing chip in the control field [2]. However, the DSP's on-chip communication resources are limited and fixed, which can lead to poor system scalability. Furthermore, frequent interrupt responses by the DSP can negatively impact its operational efficiency. Compared to DSP, FPGA offers the following advantages: it supports parallel operations, can proc --- ## Design and Implementation of a Blast Wave Overpressure Test System Based on DSP+FPGA+AD9238 - URL: https://intl.sienovo.cn/blog/130074321 - Date: 2023-04-14 - Tags: #DSP+FPGA, #TestSystem Reliable and accurate evaluation of blast wave key characteristic parameters is a prerequisite and basis for military operation planning. Test results can provide a reference for warhead design and an effective basis for the R&D and manufacturing of weapon body materials. In recent years, with breakthrough achievements in integrated electronic technology and software systems, blast wave testing technology has achieved stable development. 2.2 Overall Framework of the Test System 2.2.1 System Composition Traditional data acquisition systems use microcontrollers for software design to control ADCs for acquisition. However, due to the high real-time requirements of blast wave testing, software-controlled methods cannot obtain precise clock signals, and processor speed is often insufficient. Therefore, a suitable controller is required for system design. Blast wave test systems require high-speed, real-time sampling of high-frequency signals, with high demands on both clock and data ac --- ## DSP+FPGA-based Airborne Radar Servo Control System (Part 2) Power Simulation - URL: https://intl.sienovo.cn/blog/130075389 - Date: 2023-04-11 - Tags: #FPGADev, #FPGASimulation, #DSPSimulation Analysis and Simulation of Board-Level Power Distribution Networks In hardware circuit design, the design of the power system is one of the key steps. A good power system ensures the transmission of various signals on the circuit board. This chapter will investigate issues related to power integrity and propose a series of measures to improve power quality. **3.1** **Power Integrity** Power Integrity, abbreviated as PI, refers to the ability of the Power Distribution Network (PDN) to meet the power demands of load chips. Its design objectives are mainly twofold: first, to provide clean supply voltage to the load, and second, to provide a low-noise reference path for signals \[21]. With the continuous increase in chip switching speeds and transistor counts, chip power consumption is constantly increasing, and the transient current demand required during switching is growing. These changes pose significant challenges to the design of power distribution networks. The power distributi --- ## Hardware Design and Development of an Airborne Radar Servo Control System Based on DSP+FPGA (Part 1) Overall Design - URL: https://intl.sienovo.cn/blog/130075249 - Date: 2023-04-11 - Tags: #DSP+FPGA **2.1** **Functional Requirements and Performance Indicators** **2.1.1** **Functional Requirements** (1) Capable of two-axis movement (azimuth and elevation); (2) The azimuth axis can perform preset, continuous scan, and sector scan functions; (3) The elevation axis can perform a preset function. **2.1.2** **Performance Indicators** (1) Motion Range: Azimuth rotation range is , elevation rotation range is ; (2) Angular Velocity: Maximum azimuth angular velocity is 100º/s, maximum elevation angular velocity is 40º/s; (3) Angular Acceleration: Maximum azimuth angular acceleration is 90º/s²; (4) Static Positioning Error: 0.1º (maximum); (5) Angular Resolution: 0.01º; (6) System Power Supply: Voltage is 27V, starting current is 6A, operating current is 2.5A; (7) Electrical Interface: Uses RS-422 transmission protocol, host computer downlink frequency is 100Hz, controller uplink frequency is 200Hz, baud rate is 115200bps; (8) Environmental Adaptability: Temperature range is --- ## FPGA+DSP-based Shockwave Overpressure Test System Design and Implementation - System Testing (Part 2) - URL: https://intl.sienovo.cn/blog/130074644 - Date: 2023-04-11 - Tags: #FPGADev 5 System Function Testing and Simulation After completing the design of the system hardware circuit board and the development of software programs, this chapter separately tested the read/write waveforms of the A/D acquisition module and the DDR3 SDRAM storage module. Packet capture and speed testing were also performed on the Gigabit Ethernet transmission module using Wireshark software. After successful debugging and verification, the modules were assembled for overall system testing to check if the system functions meet the requirements. The assembly diagram of the data acquisition system is shown in Figure 5-1. From top to bottom, they are the AD9238 analog-to-digital conversion module, FPGA module, Gigabit Ethernet module, and DSP module. Module expansion can be performed later according to experimental requirements. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130074644/01_bf4e7c95531f66867cd9c76e108b709f.png) After verifying the DC performance of the A/D modu --- ## RK3399 + Kylin Industrial Tablet Solution - URL: https://intl.sienovo.cn/blog/130063985 - Date: 2023-04-10 - Tags: #RK3399 A few key properties are worth understanding: - **`compatible = "gs_mxc6655xa"`** — this string must match the `.compatible` entry in the kernel driver's `of_match_table`. If this string is wrong or the driver module is not loaded, the device will not bind. - **`reg = <0x15>`** — the I²C slave address. Confirm with `i2cdetect -y 5` at runtime; you should see a device acknowledged at address `0x15`. - **`irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>`** — the interrupt line is GPIO3_C1, configured as active-low. This matches the MXC6655xa's INT pin behavior when a motion threshold is exceeded. - **`irq_enable = <1>`** — enables interrupt-driven reporting rather than pure polling. - **`poll_delay_ms = <30>`** — when polling is active (or as a fallback), the driver samples the sensor every 30 ms (~33 Hz), which is a reasonable rate for UI rotation and industrial tilt sensing. - **`type = `** — maps the device into the Rockchip sensor subsystem as an accelerometer type, --- ## Design and Implementation of an Air Data Measurement Device Based on Domestic FPGA, DSP, and 1553B Bus - URL: https://intl.sienovo.cn/blog/130052274 - Date: 2023-04-10 - Tags: #DomesticDSPFPGA Air data is used by aircraft control and management systems to provide flight guidance, making real-time and accurate acquisition of air data crucial during flight. This paper designs and implements an air data measurement device based on FPGA and DSP. The measurement device includes five pressure sensors and two temperature sensors, capable of real-time acquisition of pressure and temperature signals from the aircraft surface. After acquisition, conditioning, conversion, and computation, the sensor signals output five pressure values and two temperature values. The obtained pressure and temperature values can be used to compute air data parameters such as Mach number, static pressure, angle of attack, sideslip angle, and total temperature. The aircraft control system uses these parameters to monitor the aircraft's flight status in real-time and make corresponding adjustments and control actions. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/130052274/01_1911024f5658a4 --- ## 2-6 Axis Dispensing Control System Solution Design - URL: https://intl.sienovo.cn/blog/129995512 - Date: 2023-04-06 - Tags: #DispensingControl The 2-6 axis dispensing control system consists of a TV5600 handheld terminal and an offline motion control card (OMC8849/OMC1600) based on the OMCV13 system. The two components are connected via Modbus serial communication. The TV5600 handles the human-machine interface (HMI) tasks, while the offline motion control card performs motion control and I/O operations, forming a split-type, full 3D, high-precision dedicated motion control system. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129995512/01_63310c030dee2eb86d020bea15b301c2.png) **Hardware Features:** * Controllable Axes: 2-6 axes * Maximum Pulse Frequency: 2MHz * Pulse Output: 5V differential output, Output mode: Pulse+Direction or Pulse+Pulse * Handheld Terminal Screen Resolution: 480x272 pixels, Color * 128MB storage for handheld terminal, 128MB for offline card * Digital Input: All opto-isolated, Input voltage: 12-24V * Digital Output: All opto-isolated, NPN open collector 5-24VDC, rated cur --- ## Integrated Design Solution for Vision Controller and Smart Vision Software - URL: https://intl.sienovo.cn/blog/129994046 - Date: 2023-04-06 - Tags: #AI ## I. Vision Controller The entire system primarily consists of two parts: hardware and software. Hardware components: Vision Controller + Camera + Lens + Light Source + Light Source Controller Software components: ADTvision module ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129994046/01_3a8af4f925c1d5b0a9cd6e8340aaf475.png) **Features** 1. Supports cameras with various interfaces such as Gigabit Ethernet and USB. 2. Supports area scan CCD cameras. 3. Provides 1 opto-isolated input, 1 opto-isolated output, and 2 GPIOs. 4. Supports online or offline inspection. 5. Supports various common communication interfaces such as RS232 and Ethernet. 6. Complies with OPC standard. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129994046/02_3d4f11266d4f1f458e4d0679fba1e725.png) ## II. AVS4.0 Smart Vision Software The AVS Smart Vision Recognition System is a new generation, easy-to-learn, easy-to-use, feature-rich, and powerful general-purpose vision sof --- ## X86 Vision Controller + Light Source Controller Solution Design - URL: https://intl.sienovo.cn/blog/129993799 - Date: 2023-04-06 - Tags: #VisionController Industrial machine vision systems depend on tight integration between imaging hardware, lighting control, and software—yet getting all three to work together reliably is often the hardest part of a deployment. This post describes the X86-based AVS Intelligent Vision Recognition System that Sienovo (Xinmai) has developed for high-precision industrial positioning, walking through its hardware architecture, communication interfaces, and the role of the ADTvision software platform. ## System Architecture Overview The AVS system is split cleanly into hardware and software layers, which makes it straightforward to plan an installation and to isolate problems when they arise. **Hardware layer:** Vision Controller + Camera + Lens + Light Source + Light Source Controller **Software layer:** ADTvision PC software ![System overview](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129993799/01_5a21732bf502ec8c3dac1f409e77e96a.png) The vision controller is an x86-class embedded PC, w --- ## ZYNQ ARM+FPGA Binocular Stereo Vision Controller Design and Implementation (Part 1) - URL: https://intl.sienovo.cn/blog/129958175 - Date: 2023-04-06 - Tags: #ZYNQ, #Vision Implementing a binocular stereo vision system with an FPGA+ARM architecture using a ZYNQ board. This design utilizes the Zynq-7020 board independently developed by our lab and proposes a hardware and software system design solution for binocular stereo vision based on the FPGA+ARM architecture. Based on the functional division between the system's hardware and software, the PL (FPGA) side primarily handles binocular camera image acquisition, storage, and HDMI display. The PS (ARM) side primarily implements software control, as well as binocular stereo vision stereo matching and stereo rectification algorithms. This design uses an OV5640 binocular camera, with an image resolution of 640*480 and an image transmission frame rate of 30fps. High-speed data transfer is achieved via AXI-DMA, and ping-pong operations are implemented using SGI software interrupts and DMA interrupts, ultimately displaying a stable 640*480 disparity map on HDMI. **4.1** **Introduction to the Binocular System H --- ## AM64X/AM62X + FPGA Inter-Core Communication Solution - URL: https://intl.sienovo.cn/blog/129954356 - Date: 2023-04-04 - Tags: #Server, #Networking, #linux IPC for AM64x The AM64x processor has two dual-core Cortex-R5F subsystems (R5FSS) and one Cortex-M4F subsystem. In addition, there is a dual-core Cortex-A53 subsystem. The R5FSS supports dual-core mode (Split mode) and single-CPU mode. **理解IPC（inter-processor communication）**refer link IPC SW Architecture ![在这里插入图片描述](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129954356/01_494b83c1fcb61eeb396b399043079609.png) APIs for exchanging messages between CPUs: IPC Notify and IPC RP Message IPC RP Message: Features: RP Message + VRING protocol implementation Uses IPC Notify for interrupts at the lower layer, and shared memory (VRING) as the message buffer. Supports message passing between NORTOS, FreeRTOS, and Linux CPUs. Logical communication channels can be created using unique "endpoints." This allows multiple tasks on one CPU to communicate with multiple tasks on another CPU using the same underlying HW mailbox and shared memory. IPC Notify: The underlying implementation w --- ## AM62X +FPGA+AD/DA TSN Industrial Gateway Solution - URL: https://intl.sienovo.cn/blog/129954032 - Date: 2023-04-04 - Tags: #AM62X, #FPGA, #AD Texas Instruments' Sitara AM62x processor family represents a significant leap forward for edge-AI-enabled human-machine interfaces (HMI) in industrial settings. This article unpacks the AM62x's five key differentiators, walks through its eight headline upgrades over the widely deployed AM335x, and explains how the companion FPGA + AD/DA + TSN stack turns it into a capable industrial gateway SoC. ## Why HMI Is Evolving from "Interface" to "Interaction" The concept of HMI is undergoing a fundamental shift — from static physical panels, buttons, switches, and indicator lights toward richer interaction modalities: facial recognition, gesture control, voice commands, high-definition graphics, and predictive maintenance dashboards. This shift demands that the underlying MPU deliver AI inference, functional-safety support, advanced display pipelines, and broad connectivity, all within tight power and cost envelopes. TI's Sitara General-Purpose MPU product line manager outlined four pressu --- ## Design and Implementation of a 1553B Bus Controller Test System Based on ZYNQ 7000 - URL: https://intl.sienovo.cn/blog/129936044 - Date: 2023-04-03 - Tags: #FPGADev, #ZYNQ, #MILSTD1553B To facilitate the testing of 1553B devices, this paper introduces a design and implementation method for a 1553B bus controller test system based on the ZYNQ 7000 platform. The system first configures data on a PC through a human-machine interface, supporting flexible data fault injection. Then, it sends the data to the ZYNQ's PS (Processor System) side via a serial port. The ZYNQ's PL (Programmable Logic) side reads the data, and finally, the ZYNQ's PL side drives the data out. After the design was completed, simulation verification was performed, and the results showed that it met the design requirements. Introduction: Avionics systems are distributed communication systems built upon 1553B bus communication networks. Various electronic devices within avionics systems are developed by numerous R&D units according to system requirements and are ultimately integrated into a system via 1553B bus networking. Each R&D unit primarily develops 1553B communication products based on 1553B st --- ## My Views on Empowering Humanoid Robots with ChatGPT Large Models - URL: https://intl.sienovo.cn/blog/129932576 - Date: 2023-04-03 - Tags: #AI ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129932576/01_be2bcb3582283b3b0c81e34260d9671a.png) My personal views (without involving any project-related details or trade secrets, these are merely my general observations): 1. From a macro trend perspective, the flexibility and versatility of [humanoid robots](https://www.zhihu.com/search?q=%E4%BA%BA%E5%BD%A2%E6%9C%BA%E5%99%A8%E4%BA%BA&search_source=Entity&hybrid_search_source=Entity&hybrid_search_extra=%7B%22sourceType%22%3A%22answer%22%2C%22sourceId%22%3A2963630653%7D "humanoid robots") are indeed very high, and they hold great promise. Moreover, wheeled-legged locomotion is not unique to this approach; ETH Zurich's ANYMAL quadruped/wheeled robot is an excellent example, demonstrating excellent mobility and flexibility. It can be widely applied in various industrial and commercial scenarios. 【**In short, if it can be successfully developed, it will be highly valuable in terms of both versatility and practicality.】** --- ## ChatGPT + Robot Controller Integration (Part 1) - URL: https://intl.sienovo.cn/blog/129842664 - Date: 2023-03-29 - Tags: #chatgpt, #Robotics **Challenges Facing Modern Robotics, and How ChatGPT Can Help** Currently, the robot operation workflow starts with engineers or technical users, who need to translate task requirements into system code. Engineers are in the loop of the workflow, constantly writing new code and specifications to correct robot behavior. Overall, this process is slow (users need to write low-level code), expensive (requiring highly skilled users with deep knowledge of robotics), and inefficient (requiring multiple interactions to function correctly). However, ChatGPT has opened up a new robotics paradigm, allowing potentially non-technical users to participate in the loop, providing high-level feedback to large language models (LLMs) while monitoring robot performance. By following the design principles of the research, ChatGPT can generate code for robotic scenarios. Without any fine-tuning, the research leverages the LLM's knowledge to control different robot morphologies to accomplish various tasks. --- ## ChatGPT + Secure Robot Controller + Integrated Chassis Solution: A Design Concept - URL: https://intl.sienovo.cn/blog/129842548 - Date: 2023-03-29 - Tags: #chatgpt, #Robotics ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129842548/01_94a7979c9e7ed190f68ba929fd5d67c0.png) "Have you ever thought that you just need to tell your home assistant robot: 'Please heat my lunch,' and it will find the microwave by itself? Isn't that amazing?" Recently, Microsoft published a paper titled "ChatGPT for Robotics: Design Principles and Model Abilities" on its official website, announcing their research findings on applying ChatGPT to robotics. The paper states that the goal of this research is to observe whether ChatGPT can think beyond text and reason about the physical world to help complete robotic tasks. Humans currently still heavily rely on handwritten code to control robots. The team has been exploring how to change this reality and use OpenAI's new AI language model, ChatGPT, to achieve natural human-robot interaction. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129842548/04_ad0367cfb98da822c79fd2c40f42b12a.png) Researchers hop --- ## Large Model Multimodal ChatGPT + Autonomous Driving Controller Design Solution - URL: https://intl.sienovo.cn/blog/129842443 - Date: 2023-03-29 - Tags: #AI, #AutonomousDriving, #chatgpt, #LLM ## Decision-Making Challenges in Autonomous Driving In the autonomous driving industry, decision-making and planning serve as the brain of the entire system — a core algorithmic module that is central to both functional realization and safety assurance. The majority of companies implementing assisted or autonomous driving today rely on rule-based approaches. Rule-based systems offer a key advantage: the decision logic is traceable. When something goes wrong, engineers can follow the rule chain back to the source of the failure. Reinforcement learning (RL), by contrast, carries a well-known structural weakness: when the model produces a bad output, root-cause analysis is extremely difficult. The only viable response is continued iteration — collecting more edge-case data, retraining, and hoping the next model version handles the scenario correctly. Worse, RL requires large-scale training and a robust evaluation framework. Without a reliable way to score model outputs, there is no sign --- ## ChatGPT + Industrial Robots/Autonomous Driving Controllers: Some Experiments - URL: https://intl.sienovo.cn/blog/129842333 - Date: 2023-03-29 - Tags: #chatgpt, #Robotics ChatGPT is a language model trained on a vast corpus of text and human interactions, enabling it to generate coherent, grammatically correct responses across a wide range of prompts. But can it go beyond text and reason about the physical world well enough to help robots complete real tasks? That is exactly what a Microsoft Research team set out to answer in a 2023 paper exploring how ChatGPT can serve as a natural-language interface for robotic platforms—including robotic arms, drones, and home assistant robots—without requiring users to write a single line of code. Paper link: https://www.microsoft.com/en-us/research/uploads/prod/2023/02/ChatGPT___Robotics.pdf ## The Problem with Today's Robot Programming Workflow The conventional robot programming pipeline starts with an engineer or highly skilled technical user who translates a task requirement into system code. That engineer stays in the loop throughout, continuously writing new code and specifications to correct the robot's be --- ## ZYNQ+AD8285 High-Speed Millimeter-Wave Radar Data Acquisition System Design - URL: https://intl.sienovo.cn/blog/129821843 - Date: 2023-03-28 - Tags: #ZYNQ, #AD, #mmWaveRadar Traditional millimeter-wave radars employ DSP+FPGA processing modules, where FPGAs enhance data acquisition throughput and DSP devices execute data processing algorithms. To meet the current demands for low power consumption and miniaturization in millimeter-wave radars, while also ensuring data interface stability and speed, this design proposes a ZYNQ-based acquisition system from Xilinx, featuring high integration and high reliability. The PL-side logic resources control high-speed AD data acquisition. The PS-side transmits the acquired data to a host computer, where dynamic parameter analysis of the acquisition system is performed using the Matlab platform. Experiments demonstrate that all dynamic parameters of the AD meet the design requirements, thus validating the rationality of this high-speed acquisition system design. 1 System Overall Design In millimeter-wave radar applications, the data acquisition system primarily consists of the following components: ADI's 12-bit AD828 --- ## Design of an Integrated Board Featuring AM62x TSN Switch, FPGA, and High-Speed AD Acquisition - URL: https://intl.sienovo.cn/blog/129809274 - Date: 2023-03-28 - Tags: #FPGADev, #TSN, #HighSpeedADC Recently, Texas Instruments launched its new Sitara AM62 processor, featuring Edge AI, dual-screen display, and other functionalities, significantly boosting industrial HMI upgrades. In TI's new product introduction video for AM62x, Liu Jingwei, Sitara General Purpose MPU Marketing Manager, detailed the various features of the AM62x. Liu Jingwei stated that the connotation of HMI is shifting from Human Machine Interface to Human Machine Interaction. Its product form has evolved from early physical control panels, buttons, switches, and indicator lights to supporting richer functionalities such as facial recognition, voice recognition, high-definition displays, and graphical interfaces. To this end, MPUs need continuous innovation to meet the new demands of HMI. Firstly, MPUs need to have AI support, privacy and IP protection, higher processing performance, and more complex peripherals. Furthermore, as performance and functionality increase, power consumption will also rise accordin --- ## Key Technology Research and Development of a ZYNQ+Linux+Xenomai-based Multi-axis Motion Control Platform - Test System Setup (Part 4) - URL: https://intl.sienovo.cn/blog/129784535 - Date: 2023-03-26 - Tags: #ZYNQ, #MotionController This chapter describes the setup of the experimental test platform to test the hardware functions and system task communication functions of the multi-axis motion control platform. Through the test results, the correctness of the platform's hardware design is verified, and the functionality and performance of the system's real-time processing and synchronous control are validated. **5.1 Test Platform Setup** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129784535/01_583a93a9edc43d7231630c410e1a9eba.png) The test platform setup for the multi-axis motion control system is shown in Figure 5.1. The test platform consists of a safety power supply, a multi-axis motion platform prototype (including the main control board MC), a host PC, a handheld pendant, and four 80ST-M0 1330LMB Huada AC servo motors (with built-in 17-bit absolute encoders). The prototype is connected to the four servo motors via motor power interfaces and encoder interfaces. Hardware testing of the moti --- ## Research and Development of Key Technologies for ZYNQ-based Multi-axis Motion Control Platform - Linux + Xenomai Open-source Real-time System Design (Part 3) - URL: https://intl.sienovo.cn/blog/129784030 - Date: 2023-03-26 - Tags: #ZYNQ, #linux+xenomai, #RealTime **4.3 Non-periodic Task Communication Technology** In multi-axis motion control, inter-core non-periodic task communication in a dual-core system is primarily used for the Linux system to read information from the servo system, such as servo parameters. **4.3.1 Data Link Design** In non-periodic task communication, the communication data in a dual-core system is diverse, and message lengths are not fixed. Therefore, variable-length mailboxes are used to implement the data link for non-periodic communication, and inter-core semaphores are used to manage the switching of system communication states. The data link for non-periodic task communication is shown in Figure 4.13, with data frame definitions completed on the OCM. Concurrently, both the Linux system and the servo system define corresponding data frames in their applications, used to store destination data frames and response data frames. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129784030/01_3974bdfb306c36 --- ## 基于ZYNQ 的多轴运动控制平台关键技术研发-Linux+xenomai开源实时系统设计(二） - URL: https://intl.sienovo.cn/blog/129783845 - Date: 2023-03-26 - Tags: #linux+xenomai, #RTOS, #ZYNQ **4. SoC Dual-Core System and Inter-Core Multi-Task Communication Design** This chapter details the design of the SoC core system under AMP architecture and the implementation methods for inter-core task communication. First, the dual-core system is set up, and device drivers are ported. Then, a communication module based on shared memory is designed. Finally, a multi-task communication solution is proposed to meet the requirements of different communication tasks within the system. **4.1 Dual-Core System Design and Implementation** **4.1.1 Linux Real-time System Setup** **(1) Xenomai Real-time Patch Installation** Robot control systems require strong real-time capabilities, ensuring real-time processing and response for motion control-related task scheduling and data communication during operation. Due to mechanisms such as kernel preemption, interrupt masking, and priority preemption scheduling, the Linux system cannot provide strict hard real-time performance. There are two met --- ## Key Technology Development for Multi-Axis Motion Control Platform Based on ZYNQ – Overall Architecture Design (Part 1) - URL: https://intl.sienovo.cn/blog/129783489 - Date: 2023-03-26 - Tags: #ZYNQ, #MultiAxisMotionController To meet the real-time communication and synchronized control requirements of a multi-axis motion control platform, the Xilinx Zynq 7020 SoC is adopted as the core processor to design the overall architecture of a dual-core SoC-based multi-axis motion control platform. Based on the functional and interface characteristics of multi-axis motion control systems, the hardware design of the SoC motion control platform is completed, primarily including the SoC minimum system and mainstream communication interface designs such as Ethernet, USB, and UART. To ensure functional completeness of motion control, a dual-core SoC system is designed comprising a Linux+Xenomai real-time operating system and a servo bare-metal system. Under the Linux system, driver porting for the platform's communication devices is implemented. This chapter analyzes the application requirements of a robotic multi-axis motion control platform, proposes a dual-core SoC-based multi-axis motion control platform design, an --- ## ZYNQ-based Mobile Robot Controller Design (Part 1) - URL: https://intl.sienovo.cn/blog/129718026 - Date: 2023-03-22 - Tags: #zynq, #MobileRobot, #Controller The design of a mobile robot is a multidisciplinary task integrating software, hardware, and mechanical knowledge. Therefore, a complete solution must demonstrate its key technologies in mechanical structure, hardware architecture, and software layers. 2.1 Application Scenario Description and Requirements Analysis This section first describes the application scenario for the mobile robot controller solution proposed in this paper. Then, starting from this application scenario, it deduces and summarizes the functional and performance requirements for mobile robots in this context. 2.1.1. Application Scenario Description As mentioned earlier, current mobile robot solutions are typically developed for specific problems, with complex structures and lengthy, slow development processes. They often fail to meet the demands of agile development, making it difficult to quickly deliver products with general-purpose functionalities. Cost control is also challenging. Furthermore, the reusabilit --- ## Zynq+AD+DA-based Shaking Table Controller Testing and Verification (Part 4) - URL: https://intl.sienovo.cn/blog/129717709 - Date: 2023-03-22 - Tags: #ZYNQ, #VibrationController **Shaking Table System Testing and Verification** **5.1 Test Platform** Figure 5.1 shows the single-degree-of-freedom electro-hydraulic servo shaking table used in this paper, with its main parameters listed in Table 5.1. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129717709/01_9a1f50ce857217ea5f010643f63346f1.png)  ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129717709/02_537df918580a5ffc06d2b5d8efc706bc.png) **5.2 Data Preprocessing** The controller architecture designed in this paper is relatively general-purpose. The motion waveform can be a sine wave, a random wave, or an earthquake wave. In experiments where the reference waveform is an earthquake wave, data preprocessing is required. Two scenarios here require preprocessing: one is when earthquake wave data only contains acceleration waveforms, without displacement and velocity waveforms. In this case, velocity and displacement need to be synthesized from acceleration, and baseline correct --- ## FPGA Algorithm Implementation of a Shaker Controller Based on Zynq+AD+DA (Part 3) - URL: https://intl.sienovo.cn/blog/129717569 - Date: 2023-03-22 - Tags: #FPGADev, #ZYNQ **4 FPGA Implementation of Shaker Control Algorithms** **4.1 PID Control Algorithm** **4.1.1 Incremental PID Control Algorithm** PID control is a widely used control method in control engineering [33]. Its basic principle block diagram is shown in Figure 4.1, where 𝑢𝑢(𝑡𝑡) is the control signal, 𝑟𝑟(𝑡𝑡) is the system input signal, and 𝑦𝑦(𝑡𝑡) is the system output signal. The control system is mainly composed of three components: Proportional, Integral, and Differential. The system error is processed by the three units of the controller through operations and linear combination to obtain the control quantity, where the system error 𝑒𝑒(𝑡𝑡) can be expressed as ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129717569/01_00800af048b5128c3d91b9d3a6b4fdf3.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129717569/02_85e845c95ba6a782a9d989a44af499b8.png) As can be seen from the above equation, the incremental PID is only related to the errors --- ## Zynq+AD+DA-based Vibration Table Controller Architecture Design and Algorithm Implementation - Overall Architecture Design (Part 2) - URL: https://intl.sienovo.cn/blog/129674005 - Date: 2023-03-22 - Tags: #FPGADev **3 Vibration Table Controller Architecture Design and Implementation** As previously mentioned, the Zynq-7000 already possesses unique architectural advantages by combining an ARM Cortex-A9 processor subsystem (PS) with a programmable logic fabric (PL) on a single chip. This tight coupling allows the vibration table controller to partition its workload along a clear boundary: tasks demanding deterministic timing — sampling, filtering, PID computation, and analog output — run entirely in the PL at hardware speed, while tasks that require flexibility but not strict cycle-accuracy, such as host communication and parameter management, run in the PS. This is a critical design distinction. "High-speed" and "real-time" are not synonymous: a USB or Ethernet link may transfer data at hundreds of megabits per second yet tolerate milliseconds of jitter, whereas the control loop must complete within a fixed 1 ms window with no exceptions. Based on this partitioning principle, the overall progra --- ## Vibration Table Controller Architecture Design and Algorithm Implementation Based on Zynq + AD + DA - Overall Architecture Design (Part 1) - URL: https://intl.sienovo.cn/blog/129669481 - Date: 2023-03-22 - Tags: #FPGADev Electro-hydraulic vibration tables can simulate vibrations in real-world environments and are widely used in fields such as seismic simulation for buildings, material structure testing, automotive testing, and marine gangways. High-performance vibration controllers required for controlling electro-hydraulic vibration tables primarily rely on imports. In recent years, FPGA-based vibration controllers have begun to highlight their advantages, making them more suitable for multi-channel, high-frequency, and other testing scenarios. This paper designs a set of vibration table control programs based on the CPU+FPGA architecture of the Zynq-7000 chip, which is clearly structured, highly versatile, and easily extensible. It implements functions such as data acquisition, control, and Ethernet communication. System tests were conducted to verify the rationality and effectiveness of the controller architecture. Sine wave tests and seismic wave tests were performed. In the sine wave tests, the --- ## Design of a CAN Bus Motion Controller for Soft Robots Based on STM32 ARM+ FPGA - URL: https://intl.sienovo.cn/blog/129646892 - Date: 2023-03-20 - Tags: #FPGADev, #Robotics, #MCU To address the challenges of multi-motor coordinated control in soft robot applications, such as high difficulty, poor versatility, and poor coordination, a Controller Area Network (CAN) bus motion controller for soft robots based on ARM and FPGA was designed. This CAN bus motion controller for soft robots was implemented using an STM32F407 development board, featuring an ARM Cortex-M4 core, and an AX7102 FPGA development board. The design primarily covers the system architecture, hardware design, and software design. The controller leverages the STM32 as the control core and the high-speed processing capabilities of the FPGA to execute control algorithms, while CAN bus technology is employed for communication with the host computer. Experimental operation has demonstrated that this controller meets the predefined requirements. Soft robots differ from traditional rigid robots, offering numerous advantages, including bio-flexibility. They can perform flexible obstacle avoidance or comp --- ## Fudan Micro ZYNQ7020 Domestic Replacement Solution Design - URL: https://intl.sienovo.cn/blog/129649793 - Date: 2023-03-19 - Tags: #FPGADev, #FMSHZYNQ7020, #DomesticZYNQ The pace of domestic substitution is accelerating. Imported chips were only used for functional verification and will soon be replaced by domestic alternatives. Currently, Fudan Micro is the only domestic company that has developed Zynq-like chips. Shanghai Anlu and Chengdu Huawei are also in the process of R&D (it's not ruled out that Shenzhen Guowei is also working on it, given the significant market potential). Where are the use cases? First, let's be clear: heterogeneous SoC chips like Zynq (ARM+FPGA) are absolutely not suitable for low-cost solutions. Why? Using these chips almost always requires accompanying DDR3. The price of a single DDR3 chip is about 100 RMB, and this is for imported ones; domestic ones are even more expensive. As long as DDR is used, at least an eight-layer PCB is required. How much does one PCB fabrication cost? Over 2,000 RMB. If Fudan Micro's FMQL is used, their Nor Flash will be bundled, as other brands are incompatible. Moreover, this Nor Flash is mi --- ## Autonomous Mobile Robot (AMR) Controller Design and Experimentation (Part 1) - URL: https://intl.sienovo.cn/blog/129614477 - Date: 2023-03-17 - Tags: #ui In recent years, with the advancement of society and technology, autonomous navigation has become a crucial capability required by robots in various fields such as warehousing and logistics\[1], autonomous driving\[2], and express delivery\[3]. However, this also poses significant challenges to their long-term robustness. During long-term robot operation, especially in outdoor environments, environmental changes pose challenges to robot operation, making the improvement of robot mobility robustness a popular research topic. Regarding sensor selection, while sensors like 3D LiDAR can directly provide robust spatial geometric information, effectively enhancing the robustness of localization and perception algorithms, they are expensive. Comparatively, lower-cost visual sensors are more favored. However, visual sensors are sensitive to environmental changes and have lower robustness. Therefore, improving the robustness of visual sensors in long-term operation becomes a crucial aspect for --- ## ARM+FPGA-Based Mobile Robot Controller Design - URL: https://intl.sienovo.cn/blog/129611560 - Date: 2023-03-17 - Tags: #FPGADev The XM-AMR-5728 series controller is a general-purpose controller designed for mobile robots (AMRs, intelligent forklifts, etc.), providing core functionalities such as map building, localization and navigation, and model editing for mobile robots. This product integrates the core components of mobile robots into a single unit. Coupled with the powerful client software Roboshop Pro, it helps users quickly set up robots. In addition, SRC has gradually evolved into a controller for smart factory infrastructure, capable of controlling automatic charging stations, automatic doors, elevators, traffic lights, and more. Under a unified scheduling interface framework, it drives the intelligent transformation and automation expansion of the entire factory. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129611560/01_14b1cdc564d77bbb3e0d728693f619a9.png) **SRC-3000FS** **Safety-Rated AMR Controller** The SRC-3000FS safety-rated controller is an integrated navigation and functio --- ## Motion Controller Design Based on ZYNQ7020 ARM+FPGA - URL: https://intl.sienovo.cn/blog/129578779 - Date: 2023-03-16 - Tags: #FPGADev, #ZYNQ, #MotionController ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129578779/01_d063b79db17a80a26e6241f59c62dc7d.jpeg) The ZYNQ7020 series motion controller supports 6-axis pulse control and 16/32-axis bus control, with 36 local inputs, 24 outputs, and communication via RS232/485 and TCP. ZYNQ7020 Series Specifications: 1. Local pulse axes: 6 axes with encoder feedback; maximum encoder input frequency: 4MHz 2. Maximum pulse frequency: 4MHz, differential output; supports both pulse+direction and dual-pulse modes 3. Digital inputs: 36 channels, optically isolated (with indicator LEDs); input voltage: 12–24V; high level >4.5V; low level <1.0V 4. Digital outputs: 24 channels, optically isolated NPN open-collector output; output voltage range: 5–24VDC; maximum current per channel: 500mA 5. Power supply: DC 24V, maximum power consumption: 15W 6. Analog outputs: 2 channels of analog voltage output; output range: 0–10V 7. Operating temperature: -10°C to 50°C; storage temperature: -20°C to --- ## Glass Polishing Bus Control Solution Design - URL: https://intl.sienovo.cn/blog/129578486 - Date: 2023-03-16 - Tags: #FPGADev 2.5D glass is widely used in products such as mobile phone covers, in-car displays, and smart watch displays. During its processing, a CNC polishing machine is typically used to polish its surrounding vertical surfaces to improve transparency and texture. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129578486/01_aa2e9d78e65c570f65a25afb20841d92.gif) Xinmai closely monitors various technical challenges in glass processing. The bus control solution for mobile phone glass polishing machines, launched for the polishing equipment industry, has won the favor of numerous customers due to its economical and efficient features. For multi-axis applications in polishing machines, bus-based motion control coupled with the QXE bus servo system not only improves the positioning accuracy and stability of the entire machine but also fully leverages advantages in efficiency and flexibility. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129578486/02_53df9215e0850450b0 --- ## Design and Implementation of an Autonomous Driving Domain Controller for Intelligent Vehicles Based on NVIDIA Xavier - Baidu Apollo Architecture (Part 2) - URL: https://intl.sienovo.cn/blog/129429786 - Date: 2023-03-09 - Tags: #AutonomousDriving, #AI, #MachineLearning, #Controller Intelligent Vehicle Operating System An intelligent vehicle operating system is a crucial component of an intelligent vehicle system. Modern automotive software components are typically first developed by different suppliers and then integrated by manufacturers under limited resources \[42\]. The intelligent vehicle operating system needs to adopt modular and layered design principles to be compatible with modules such as sensors, distributed communication, and general autonomous driving frameworks, thereby enabling autonomous driving functions like environmental perception, motion planning, task decision-making, and vehicle control. The intelligent vehicle operating system primarily includes multi-kernel design and optimization for heterogeneous distributed systems, Hypervisor virtualization technology, POSIX API, distributed communication mechanisms, management plane, and data plane, as shown in Figure 2.2. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129429786/01 --- ## Design and Implementation of an Autonomous Driving Domain Controller for Intelligent Vehicles Based on NVIDIA Xavier (Part 1) - URL: https://intl.sienovo.cn/blog/129416469 - Date: 2023-03-09 - Tags: #AutonomousDriving, #AI, #MachineLearning Intelligent vehicles play a crucial role in reducing traffic accidents, saving energy and reducing emissions, and alleviating traffic congestion. Autonomous driving systems are the core of intelligent vehicles. In recent years, with the increasing widespread application scenarios of intelligent vehicles, artificial intelligence algorithms have been widely used in autonomous driving systems, and the functions of autonomous driving systems have continuously enhanced. This has led to a situation where the computing power of hardware platforms with a single-chip architecture can no longer meet the needs of autonomous driving systems. The perception system of intelligent vehicles is composed of various types of sensors, which increases the complexity of system integration and communication interfaces. Traditional distributed control system architectures cannot meet reliability requirements. Therefore, designing an intelligent vehicle domain controller with rich interfaces, diverse function --- ## RK3588 AI High-Performance 5-Port Industrial Switch - URL: https://intl.sienovo.cn/blog/129415949 - Date: 2023-03-09 - Tags: #AI, #IndustrialSwitch, #RK3588, #MultiEthernet The RK3588 is Rockchip's most powerful SoC to date — an octa-core, 8K-capable chip that brings datacenter-grade AI compute to the edge. This post walks through the full hardware specification of a 5-port industrial switch built on the RK3588, explaining why each subsystem matters for demanding edge-AI and industrial networking deployments. ![RK3588 AI Industrial Switch](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129415949/01_95924bb0d473b9bd800f334586043383.png) ## Why RK3588 for an Industrial Switch? Traditional managed switches run lightweight MIPS or ARM Cortex-A cores that handle packet forwarding but leave no headroom for on-device intelligence. The RK3588 breaks that trade-off: its highly integrated SoC design packs a powerful CPU cluster, a dedicated NPU, a full-featured GPU, and a wide array of high-speed peripherals into a single die, reducing BOM cost while enabling AI workloads — traffic classification, anomaly detection, or video analytics — to run directly --- ## Software Design for Intel SoC+FPGA-based Smart Cockpit and Advanced Driver-Assistance Systems (Part 3) - URL: https://intl.sienovo.cn/blog/129369292 - Date: 2023-03-06 - Tags: #FPGADev, #intel, #SoftwareDesign, #SmartCockpit **Introduction to Virtualized Operating Systems** In-vehicle platforms are showing a trend towards convergence. With the rapid growth in computing performance and applications of in-vehicle SoCs, there's a challenge of integrating multiple applications across various display subsystems, which necessitates the platform to run multiple operating systems. Virtualization technology is developing rapidly. System virtualization is a type of virtualization technology, and with the significant advancements in current CPU technology and performance, the time for virtualization technology to be truly commercialized has arrived. System virtualization refers to virtualizing a single physical computer system into one or more virtual computer systems. Each virtual computer system (referred to as a virtual machine or VM) possesses its own virtual hardware (e.g., CPU, memory, and devices) to provide an independent VM operating environment. By emulating the virtualization layer, the operating system --- ## Hardware Design of Intel x86 + FPGA-based Smart Cockpit and Advanced Driver Assistance Systems (Part 2) - URL: https://intl.sienovo.cn/blog/129369185 - Date: 2023-03-06 - Tags: #FPGADev, #intel, #SmartDriving **System Functional Architecture and Module Overview** The smart cockpit and advanced driver assistance system is an embedded platform for in-vehicle intelligent terminals, integrating both hardware and software capable of running virtualized operating systems. The vehicle-mounted host described in this article includes a hardware main control processor, power management ICs, storage devices, input/output controllers, digital instrument systems, rear-seat entertainment systems, multi-channel camera systems, as well as software components such as virtualized operating systems, real-time operating systems for sub-domains, and automotive manufacturer applications. All components must meet the quality requirements specified by automotive-grade certifications AEC-Q100/AEC-Q101/AEC-Q200. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129369185/01_34f1747cc193386342c6503f0722b4be.png) Key performance indicators of the SoC A3900 are as follows: - Based on Goldmont architectur --- ## Vehicle Smart Cockpit and ADAS Design Based on x86 SoC (Part 1) - URL: https://intl.sienovo.cn/blog/129369056 - Date: 2023-03-06 - Tags: #5G, #AI, #SmartCockpit, #ADAS As cars become the center of software-defined automation, Intel is committed to providing scalable and secure solutions from car to cloud to accelerate technological support for autonomous driving, from Advanced Driver-Assistance Systems (ADAS) to fully autonomous vehicles. In March 2016, Intel acquired Mobileye, an Israeli advanced driver-assistance system company, for $15.3 billion. In July 2016, BMW Group, together with Intel, the world's largest chip manufacturer, and Mobileye, a global leader in advanced driver-assistance systems, held a joint press conference to announce that the three parties would collaborate to develop autonomous vehicles based on the BMW i Vision Future Interaction concept car, with the production version officially launching in 2021 \[2]. As the world's largest chip manufacturer, Intel has a unique inherent advantage in data computing and analytical processing. Human driving is susceptible to external emergencies and distractions due to inattention, leadi --- ## Autonomous Driving Planning and Control Hardware-Software Integrated Controller Solution (Part 1) - URL: https://intl.sienovo.cn/blog/129354883 - Date: 2023-03-06 - Tags: #AutonomousDriving, #PlanningControl, #Controller With the advancement of society, the automotive industry and electronic technology are developing rapidly. The number of in-vehicle electronic devices is increasing, and the integration level of automotive electronics platforms is getting higher and higher. The convergence of the two is revolutionizing people's driving and riding experience. This paper designs a system based on x86 SoC to achieve efficient automotive smart cockpit technology and advanced driver-assistance systems (ADAS), reducing the total cost for users. The main work of this paper is as follows: 1. Investigated the domestic and international industry status and development trends of in-vehicle systems, analyzed solutions from mainstream in-vehicle control manufacturers and major Tier 1 suppliers, pointed out the advantages and disadvantages of current smart cockpit in-vehicle systems, elaborated on key technologies in the design, and proposed the overall architecture and solution for this system design. 2. Rese --- ## VPX Ethernet Switch Board Design Based on Loongson + Domestic FPGA (Part 3) - URL: https://intl.sienovo.cn/blog/129354708 - Date: 2023-03-06 - Tags: #DomesticFPGA, #VPX, #NetworkSwitch Debugging and testing are critical phases in the development of any complex embedded system. This article, part three of a series, delves into the practical aspects of bringing up and validating a VPX Ethernet switch board, designed with a Loongson processor and domestic FPGA. We'll explore the detailed debugging environment, step-by-step procedures for single-board and joint hardware-software debugging, and comprehensive system-level testing. Crucially, we'll analyze two challenging issues encountered during testing—an intermittent Ethernet interface anomaly and line-rate forwarding packet loss—providing in-depth root cause analysis and the solutions implemented, offering valuable insights into the complexities of integrating domestic chips in high-performance industrial computing solutions. ## 6.1 Circuit Board Static Inspection Following the complete manufacturing process, which includes schematic design, PCB layout, fabrication, and assembly, the final circuit board is ready for --- ## VPX Ethernet Switch Board Design Based on Loongson + Domestic FPGA (II) - URL: https://intl.sienovo.cn/blog/129294235 - Date: 2023-03-02 - Tags: #DomesticFPGA, #VPX, #NetworkSwitch **3.1 Board Technical Requirements** **3.1.1** **Main Performance Indicators** Adhering to the principle of backward compatibility, the design of the Ethernet switch board aims to retain the basic functions and interfaces of traditional information processing platforms, with a focus on improving equipment performance and scalability. The main performance indicators for the Ethernet switch board in this project are as follows: (1) Features high-capacity, non-blocking switching; switching capacity no less than 16Gbps; (2) Supports Gigabit optical Ethernet interfaces and electrical Ethernet interfaces; (3) No packet loss for single-node real-time services, average forwarding delay ≤1ms. **3.1.2** **Main Physical Interfaces** In accordance with VPX standard requirements and actual application needs, the main physical interfaces of the Ethernet switch board are as follows: (1) Provides 20 SerDes interfaces, connected to the backplane connector, providing data exchange for the dat --- ## Design of a VPX Ethernet Switch Board Based on Loongson + Domestic FPGA (Part 1) - URL: https://intl.sienovo.cn/blog/129294125 - Date: 2023-03-02 - Tags: #DomesticFPGA, #VPX, #NetworkSwitch The exposure of "PRISM Gate" revealed significant security risks in China's information security. As network equipment serving as carriers for information transmission, there is an urgent need for their localization. Domestic processors, domestic programmable logic devices, and Ethernet switch chips, among others, have promising application prospects. On the other hand, the demands of broadband data services and multimedia services impose higher performance requirements on network equipment. The VPX standard, based on high-speed serial bus technology, is widely used in modern communications due to its high performance, high reliability, scalability, and excellent architecture. This paper conducts a systematic study of domestic chips and the VPX standard. Taking a certain information processing equipment as the background platform, a VPX-based Ethernet switch board was designed. Its core processor, programmable logic devices, and switch chips all utilize domestic chips. **2.1 VPX Bus O --- ## RK3399+FPGA+MIPI Solution Details: subLVDS to MIPI Processing - URL: https://intl.sienovo.cn/blog/129233232 - Date: 2023-02-26 - Tags: #FPGADev #CROSSLINK Series #CROSSLINK vs XO3L ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129233232/01_a4909fa97b6a0b28ca5ccf7e633936be.png) Overall, XO3L offers greater flexibility and is more akin to a general-purpose CPLD; CROSSLINK is more specialized. For the requirement of converting subLVDS to MIPI, CROSSLINK has an advantage due to its higher integration, leading to greater stability. #Key Points #CrossLink does not support JTAG download, requiring a separate download cable. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129233232/02_0799b7371c87d8a0a255f79646d42b41.png) #IO Power-up Voltage IOs are low before program loading, or at least interpreted as low by the control logic. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129233232/03_83f7a7e242371a49e175cebc12c687bd.png) #NVCM One-Time Programming (OTP) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129233232/04_0686d383a32a3cea5eda2b1056b9ba67.png) If this one opp --- ## Software Design for a Multi-parameter Data Logger Test Platform on an RK3399+Linux QT Ground Test Bench (Part 2) - URL: https://intl.sienovo.cn/blog/129165369 - Date: 2023-02-22 - Tags: #linux, #qt, #RK3399 The RK3399 is a high-performance, low-power "Chinese chip" developed by local chip manufacturer Rockchip. In April 2016, the RK3399 made its debut at an electronics exhibition held in Hong Kong. The chip uses a hexa-core big.LITTLE processor, including a quad-core Cortex-A53 and a dual-core Cortex-A72, with a main frequency up to 2.0GHz. The chip is compatible with 3G and 4G network communication, boasts rich interface resources, and excellent overall performance, supporting device interfaces such as USB3.0 and MIPI dual cameras. There are also many options for operating systems; users can choose Android/Linux/Debian, etc., as the OS, or lightweight office development environments like Phoenix OS and Flint OS, with compatibility for common software. In terms of hardware interfaces, the RK3399 provides abundant resources. The appearance and specific interface definitions of the Xinmai RK3399 development board are shown in Figure 2.5. The RK3399 has the following unique advantages: 1. --- ## Software Design of a Multi-Parameter Data Recorder Test Platform Based on RK3399 + Linux QT - URL: https://intl.sienovo.cn/blog/129160239 - Date: 2023-02-22 - Tags: #RK3399 With the increasingly critical role of high-tech in modern warfare, the development of flight equipment has evolved from single-system to multi-system architectures. During the design of aviation systems, extensive testing is required—especially the real-time recording of operational status parameters across various subsystems during development and flight testing—for subsequent analysis and design improvements. Data recorders have thus emerged to meet this need. A data recorder is a storage and measurement device that conditions, acquires, processes, and records various onboard signals before, during, and after missile launch. After the missile completes its mission, data stored in the recorder's memory can be recovered via specialized methods. Emphasizing testing technologies effectively reduces development risks, saves R&D costs, and shortens development cycles. Therefore, testing technology is an essential component in the development of flight systems. The ground test station se --- ## Embedded Linux System Porting and Driver Design Based on Loongson 2K1000 (II) - URL: https://intl.sienovo.cn/blog/129145068 - Date: 2023-02-22 - Tags: #linux, #SystemPorting This guide details the process of porting an embedded Linux system onto the Loongson 2K1000 processor, covering the critical stages of bootloader configuration, kernel compilation, and root filesystem creation. Readers will learn the specific steps and considerations for setting up a robust embedded Linux environment, including PMON bootloader analysis, Linux kernel customization, and Buildroot-based root filesystem generation. ## 3. Embedded Software System Porting For an embedded system to function correctly, a complete and operational embedded software system is paramount. This system forms the foundational platform for all subsequent software development. Key components include the PMON bootloader, which initiates kernel booting; a fully functional embedded Linux kernel; and a root filesystem responsible for critical initialization tasks during the boot process. ## 3.1 PMON Boot Process and Compilation PMON (Processor Monitor) serves as the bootloader for the Loongson 2K1000, r --- ## Embedded Linux System Porting and Driver Design Based on Loongson 2K1000 (Part 1) - URL: https://intl.sienovo.cn/blog/129140347 - Date: 2023-02-21 - Tags: #linux, #DriverDev, #DevOps 2.1 Requirements Analysis This project uses the Loongson 2K1000 processor as the embedded system's processor. It requires the implementation of a complete embedded software system that can boot normally and run embedded Linux stably. A network device driver needs to be designed to enable network connectivity and file transfer between the board and other network devices. A PCIe device driver needs to be designed to configure and access external PCIe devices connected to the processor. The three components of the software system – the bootloader, Linux kernel, and root file system – can each perform their functions, and when combined, enable the system to operate correctly. The system's bootloader can perform basic operations on devices, such as setting network device IP addresses, and can complete the booting of the Linux kernel. The bootloader's compilation method should be correct to ensure that source code changes take effect. The embedded Linux kernel should boot normally and impl --- ## Development of a High-Definition Image Tracking System Based on DSP+FPGA - URL: https://intl.sienovo.cn/blog/129131621 - Date: 2023-02-20 - Tags: #FPGADev, #DSP+ARM, #ImageTracking Target recognition and tracking technology is currently a key research direction in image processing, possessing broad application value in both military and civilian fields. Examples include precision-guided weapons, missile and aircraft early warning in military applications, and traffic management, criminal investigation in civilian applications. Among these, how to extract, identify, and track specific targets in complex backgrounds is an urgent problem to be solved. This paper introduces the current research status and development trends of image tracking systems at home and abroad, the basic composition and working principles, detailed functions, and performance requirements of image tracking systems. It designs an image tracking system based on DSP+FPGA and conducts experimental verification. The main work includes: 1) The image tracking system designed in this paper is mainly composed of an image tracking circuit, a communication control circuit, and a video interface circuit --- ## Hardware Design and Development of an Airborne Radar Servo Control System Based on DSP+FPGA - URL: https://intl.sienovo.cn/blog/129131345 - Date: 2023-02-20 - Tags: #FPGADev, #DSP+FPGA, #Radar Airborne radar is a general term for various radar antennas carried by aircraft, primarily used for aerial reconnaissance, surveillance, and ensuring accurate and safe navigation [1]. With the rapid development of aerospace technology and the widespread application of new technologies such as microelectronics, computers, and high-speed integrated circuits in the military field [2], many countries have developed numerous new types of fighter jets and missiles. The targets tracked and measured by airborne radar have also gradually shifted from surface vessels to faster aircraft and missiles. This requires airborne radar equipment to be able to quickly and precisely acquire targets [3]. The airborne radar servo control system is a critical component of airborne radar. Its function is to control the rotation of the radar antenna to achieve precise target tracking and rapid positioning. Its servo accuracy directly affects the radar's performance [4][5]. Airborne radar operates for extended --- ## Design of a Medical Video Terminal Based on RK3399+5G - URL: https://intl.sienovo.cn/blog/129118263 - Date: 2023-02-20 - Tags: #5G, #RK3399 Driven by various advanced information and communication technologies, the healthcare industry is currently showing a trend towards informatization, mobility, and intelligence. In particular, the practical application of 5G communication technology has propelled the vigorous development of the smart healthcare industry, leading to a surge of 5G-based medical and health applications and services. This further integrates advanced information technologies such as 5G, IoT, and big data, making the transformation and upgrade of traditional medical services towards digitalization, informatization, and intelligence a hot topic in industry research and application. Among these, mobile telemedicine scenarios, as a crucial application area within the smart healthcare system, effectively leverage the technical advantages of 5G mobile communication networks to achieve mobile collection and high-speed real-time transmission of large volumes of heterogeneous medical data, such as images and physiol --- ## Software Design of a Gas Well Controller Based on Loongson CPU (Part 3) - URL: https://intl.sienovo.cn/blog/129078316 - Date: 2023-02-17 - Tags: #linux, #DevOps, #Server ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129078316/01_fe90d421253711d39367a9c157063e5b.png) **4.1 Overall Design of System Software** The design of a gas well controller based on a Loongson CPU requires the development of test software for hardware modules. This primarily involves designing drivers and applications for the RTC module, memory module, 4G communication, Ethernet communication, UART serial port, and AI module. Each module is designed as a separate task, and the software design flowchart for the Loongson RTU is shown in Figure 4-1. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129078316/02_93a3f667619835e9a07ab641a0b40545.png) **4.2 Embedded Linux Development Environment** **4.2.1 Building the Embedded Linux System** With the rapid development of microprocessors, various low-cost, compact CPUs and peripheral connections have formed stable and reliable hardware architectures. Since the late 1980s, embedded operating systems such as Vx --- ## Research and Design of a Gas Well Industrial Gateway Based on Domestic Loongson CPU (II) - URL: https://intl.sienovo.cn/blog/129078124 - Date: 2023-02-17 - Tags: #HardwareArchitecture, #IndustrialGateway, #RTU, #OilWell **3.1 Overall Hardware Design of the System** From a hardware architecture perspective, this RTU primarily includes the design of three major parts: (1) Peripheral Circuit Design: Power supply circuit design, RTC circuit design, and EEPROM circuit design. (2) RTU Main Body I/O Port Design: Analog Input (A/I) port design and TTS voice port design. (3) RTU Communication Port Design: RS232 port design, RS485 port design, 4G communication port design, and Ethernet communication port design. Additionally, considering that RTUs typically operate in remote and harsh environments, to ensure the normal operation of the RTU in industrial settings, the baseboard incorporates multiple power supplies, and each module features digital signal isolation and power isolation designs. The overall hardware design scheme is shown in Figure 3-1. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/129078124/01_bf856d0992d9aaa0c301012194a00f67.png) **3.2 Hardware Development Environment and --- ## Research and Design of Gas Well Industrial Gateway Based on Domestic Loongson CPU (Part 1) - URL: https://intl.sienovo.cn/blog/129077999 - Date: 2023-02-17 - Tags: #IndustrialGateway, #RTU, #Oilfield Currently, the level of automation in China's gas fields has not yet been fully popularized, and there remains a certain gap compared to the widespread automation levels seen in gas well stations in other countries. In nations with relatively abundant natural gas resources, substantial investment and long development cycles have led to successive generations of automated extraction systems. As a result, their automation levels are higher, and digital monitoring systems are more mature. For example, global energy giants such as Shell have established highly comprehensive automation control systems. These systems not only increase energy output but also enhance returns and profitability. Therefore, the research and promotion of gas well automation systems have become particularly important. Applying the domestically developed Loongson CPU to gas well controllers not only expands the application scope of Loongson chips but also provides a new research and development approach for gas we --- ## Research and Development of a VPX Bus-Based Wafer Stage Motion Control System - DSP+FPGA Hardware Architecture (Part 1) - URL: https://intl.sienovo.cn/blog/129054299 - Date: 2023-02-16 - Tags: #HardwareArchitecture, #PrecisionMotionController, #DSP+FPGA As one of the core units of a lithography machine, the ultra-precision wafer stage is responsible for fast scanning, wafer loading and unloading, precise positioning, leveling, and focusing. Achieving sub-nanometer repeatability across 44 motor axes — while closing servo loops in 100 µs — demands a control architecture that pushes the limits of both bus bandwidth and processor throughput. This post documents the hardware architecture of a new VPX-bus-based wafer stage motion control system designed to replace a legacy VME-based solution, covering the system requirements analysis, board-level hardware selection, and the RapidIO interconnect topology that ties everything together. ## Why the VME Architecture Hit Its Limit Mature lithography wafer stage controllers have long relied on a VME parallel bus backbone. In the system under study, the motion control side consisted of multiple Motion Control cards (MC cards), a single-board computer, and a Master Bus Controller (MBC) with fiber --- ## Research and Development of a VPX Bus-based Wafer Stage Motion Control System - Taking a Lithography Stage as an Example (Part 1) - URL: https://intl.sienovo.cn/blog/129054162 - Date: 2023-02-16 - Tags: #VPX, #PrecisionMotionControl, #FPGA The Chinese source has one brand mention at the very end: "信迈提供DSP+FPGA精密运动控制器在半导体设备行业的软硬件方案。" — a closing tagline that is entirely absent from the English. I'll append only that sentence. The wafer stage system is one of the key subsystems of a lithography machine. The wafer stage motion control system plays a crucial role in achieving the performance targets of the lithography machine, thus the research and development of such a system holds extremely significant engineering application value. Based on the technical requirements for parallelism, synchronization, and real-time performance that the wafer stage control system must possess, this paper establishes a hardware architecture for a VPX bus-based wafer stage motion control system. Furthermore, it investigates a data parallel interaction mechanism based on C6678 shared memory and a precise synchronous measurement and control strategy for the system. To address issues such as real-time data transfer between multiple processors, --- ## Design of a Quadrotor Tracking and Control System Based on RK3399+STM32+PID - URL: https://intl.sienovo.cn/blog/129029630 - Date: 2023-02-14 - Tags: #stm32, #EmbeddedHardware, #MCU Overall Hardware Design Scheme of the System To design a quadrotor tracking system with tracking capabilities and stable flight, the primary step is to ensure the functional stability of the system's hardware platform. Each module of the system has different functions, so chip selection and hardware circuit design must be carried out based on the function and performance of each module. This optimizes the system in terms of engineering metrics such as cost-effectiveness, manufacturing process, and functional requirements, thereby improving the system's stability and reliability to a certain extent. This paper divides the hardware platform of the quadrotor tracking system into three units for design, based on different functions and design requirements. This ensures that each unit can operate independently while cooperating to complete tasks. The first part is the quadrotor control unit. This hardware primarily performs stable control of the quadrotor body, receives remote control sig --- ## AI Image System Design for Object Detection Based on RK3399 + YOLO - URL: https://intl.sienovo.cn/blog/129020736 - Date: 2023-02-14 - Tags: #ObjectDetection, #AI, #ComputerVision, #RK3399, #YOLO With the widespread popularization of 5G communication technology, traditional object detection systems can no longer meet the demands of various industries transitioning to intelligence. Consumers have higher demands for traditional object detection systems that previously relied on machine learning, and related manufacturing enterprises are also beginning to transition towards intelligence and low power consumption. Among these, how to combine image enhancement technology, object detection technology, and neural networks, and port them to portable embedded platforms has become a hot research topic for developers today. This project designs an object detection system based on a heterogeneous processor, which can efficiently and accurately identify target objects in specific environments with dense object populations. This paper first presents the overall design of the object detection system. For hardware design, the multi-core heterogeneous ARM processor RK3399 was selected as the --- ## Design of a Traffic Monitoring System Based on RK3399, 5G Communication, and Image Enhancement Algorithms - URL: https://intl.sienovo.cn/blog/125625899 - Date: 2023-02-14 - Tags: #RK3399, #5g Modern transportation is developing rapidly, bringing with it numerous challenges such as improving traffic efficiency, ensuring traffic safety, and strengthening traffic management. Therefore, finding effective methods for efficient and accurate monitoring of traffic roads is of great significance. By adopting more advanced communication and image processing technologies, it is possible to achieve reasonable control over traffic flow and prevent traffic accidents [1]. Currently, most road monitoring systems in China use wired transmission for information. Although wired transmission offers high bandwidth, its wiring and subsequent maintenance costs are high. Wang Ke et al. [2] used wireless communication to transmit video information. However, due to bandwidth limitations, it could not meet the requirements for real-time transmission, which would reduce the accuracy of road condition assessment. With the application of 5G technology, the speed and stability of wireless communication --- ## Design of a Multi-axis Motion Controller Based on STM32+FPGA - URL: https://intl.sienovo.cn/blog/129003308 - Date: 2023-02-13 - Tags: #FPGADev, #STM32+FPGA, #MotionController Motion controllers are the core of control systems for automated equipment such as CNC machine tools and high-end robots. To ensure the practicality, real-time performance, and stability of the controller, a multi-axis motion controller design scheme is proposed, using STM32 as the main controller and FPGA as the auxiliary controller. The hardware circuit design of the motion controller is presented, and an S-curve acceleration/deceleration algorithm is integrated into the motion controller, improving control precision and effectively preventing phenomena such as overshoot and oscillation. The performance of the motion controller was tested on a 3D dispensing machine platform, and the results show that each axis of the dispensing machine can move according to the set trajectory, operating smoothly with high real-time performance, demonstrating good application prospects. The performance of motion controllers directly determines the overall performance of automated systems [1-2]. Compa --- ## Design of a High-Speed Motion Controller Based on DSP+FPGA - URL: https://intl.sienovo.cn/blog/128946784 - Date: 2023-02-09 - Tags: #FPGADev, #MotionController Open robot motion control systems based on a "PC + motion controller" architecture can fully leverage the advantages of PCs such as high openness, good versatility, and strong processing capabilities, as well as the benefits of motion controllers like fast computation speed, excellent real-time performance, and strong control capabilities. Consequently, they have developed rapidly and become a current research hotspot. However, in current open robot motion control systems employing this architecture, whether the motion controllers are provided by controller vendors or independently designed by researchers, there are issues concerning versatility and hardware/software reconfigurability, which affect the openness of robot motion control systems. Therefore, this paper, by studying the structural characteristics of open robot motion controllers, formulated an overall design scheme for an open robot motion controller based on DSP+FPGA. Based on the formulated design scheme, an open robot m --- ## Design and Implementation of a Handheld Stabilized Gimbal Based on RK3399 and PID - URL: https://intl.sienovo.cn/blog/128929251 - Date: 2023-02-08 - Tags: #matlab, #RK3399 The two Chinese brand mentions ("信迈RK3399开发板" and "信迈提供RK3399定制化解决方案") both appear in sections of the article that the English excerpt does not reach — the English text cuts off mid-sentence well before those paragraphs. There is no corresponding location in the provided English to insert "Sienovo." The primary function of a handheld stabilized gimbal is to isolate camera attitude changes caused by external environmental factors, such as body vibrations due to operator movement or wind resistance torque. This ensures that the camera's optical axis consistently maintains the desired attitude during operation. For a gimbal camera to capture high-quality images, it is crucial to ensure the camera's optical axis remains stable relative to the target. Therefore, during camera shooting, the equipment must maintain a horizontal, constant velocity motion while also ensuring its attitude stability. This paper utilizes the Rockchip RK3399 as the control chip for the handheld stabilized gimbal c --- ## A Design Solution for a High-speed Industrial Camera based on RK3399+MIPI+FPGA (Part 1) - URL: https://intl.sienovo.cn/blog/128924318 - Date: 2023-02-08 - Tags: #FPGADev, #RK3399+FPGA, #IndustrialCamera Currently, embedded cameras are gradually replacing traditional cameras and entering the public eye, finding applications in many fields such as public security criminal investigation, biomedical science, and cultural heritage protection. However, with the increasing demand for higher quality visual imaging, image sensors are evolving towards high resolution, high sensitivity, and high pixel bit depth. Ordinary embedded cameras can no longer meet the processing requirements for large data volumes and low latency. To address this, this paper researches and designs an FPGA-based MIPI interface embedded platform camera, conducting in-depth research on image acquisition, image processing, and image transmission to ultimately develop the complete machine. For the front-end image acquisition of the system, it supports multiple image sensors from Gpixel, such as GSENSE400BSI, GSENSE2020S, GMAX0806, etc., driving the image sensor to output LVDS data signals through a pre-configurable mode. Thr --- ## Application of RK3399+PCIe+FPGA in High-Speed AD Wireless Communication - URL: https://intl.sienovo.cn/blog/128924819 - Date: 2023-02-07 - Tags: #FPGADev, #RK3399+FPGA, #HighSpeedADC I. Requirements The requirement is to implement high-speed AD/DA data acquisition and send it to a high-performance ARM core for data processing. Solution: RK3399+PCIe+FPGA+AD/DA. II. Device Introduction I. RK3399 The RK3399 is a low-power, high-performance processor for computing, personal mobile internet devices, and other smart device applications. Based on the Big.Little architecture, it integrates dual-core Cortex-A72 and quad-core Cortex-A53 with a separate NEON coprocessor. Many powerful embedded hardware engines provide optimized performance for high-end applications. RK3399 supports multi-format video decoders, including H.264/H.265/VP9, up to 4Kx2K@60fps. In particular, the H.264/H.265 decoder supports 10-bit encoding, and it also supports H.264/MVC/VP8 encoders at 1080p@30fps, high-quality JPEG encoders/decoders, and special image pre-processors and post-processors. The embedded 3D GPU makes RK3399 fully compatible with OpenGL ES1.1/2.0/3.0/3.1/3.2, OpenCL 1.2, and Dire --- ## A Design Solution for a High-speed Industrial Camera with RK3399+MIPI+FPGA (Part 3) - URL: https://intl.sienovo.cn/blog/128924710 - Date: 2023-02-07 - Tags: #fpga, #IndustrialCamera 4 Design of the Software System for the MIPI Interface Embedded Platform Camera 4.1 Introduction to the FPGA Development Environment 4.1.1 Introduction to Development Languages Common FPGA development languages include Verilog HDL and VHDL. The suffix HDL stands for Hardware Description Language. Unlike C/C++ familiar from traditional software development, the biggest feature of hardware description languages is parallel execution, meaning all descriptive statements are executed concurrently at the same time. This is significantly different from the sequential execution of C/C++. This also leads to the high execution efficiency of FPGAs. In certain high-speed, low-latency fields, Verilog HDL and VHDL play a significant role. Verilog HDL is more commonly used in the domestic market. At the same time, Verilog HDL is divided into three description levels from high to low: behavioral level, RTL level, and structural level. In short, Verilog HDL statements describing functional states are --- ## A Design Solution for a High-Speed Industrial Camera Based on RK3399+MIPI+FPGA (Part 2) - URL: https://intl.sienovo.cn/blog/128924540 - Date: 2023-02-07 - Tags: #FPGADev, #RK3399+FPGA Image Acquisition Module Circuit Design ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128924540/01_cf9e5db589e77cd794e8e810b514d5ab.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128924540/02_5cae5ce54748971b88179bcb4689dedb.png) 3.4 Image Processing Module Circuit Design The Spartan-6 chip is manufactured using a 45nm process and contains a total of 43,661 Logic Cells resources. It also features abundant DSP48A1 slices computational units and Block RAM storage units. Additionally, it supports dedicated resources such as CMT (Clock Management Tile) and MCB (Memory Controller Block). ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128924540/03_74a0142ddcc64f05f0efb615c429bc51.png) 3.5 Interface Bridging and Conversion Module 3.5.1 Bridge Chip Circuit Design As shown in Figure 3-18, the CrossLink device integrates two MIPI D-PHY hard cores and offers numerous programmable I/O resources, supporting multiple protocols or interface --- ## A Design Solution for a Power Trusted IoT AI Gateway Based on RK3568+STM32+AD8684 - URL: https://intl.sienovo.cn/blog/128923950 - Date: 2023-02-07 - Tags: #IoT, #RK3568, #STM32, #Gateway Addressing the domestic application requirements for integrated business scenarios in the power IoT, a trusted multi-functional IoT gateway device has been designed. The solution uses RK3568J as the core main controller, equipped with a trusted security module to build trusted authenticated boot. It features common interfaces such as serial ports, Ethernet, digital inputs/outputs (DI/DO), telemetry, low-power wireless, carrier communication, and 4G/5G, supporting wireless communication link extensions like WiFi, ZigBee, and NB-IoT. This device has rich business interface resources, capable of achieving multi-link transmission channels and security protection, and its highly integrated features enhance market competitiveness. 0 Introduction In the current construction process of the power IoT, intelligent devices with edge computing capabilities play an important role. They interact with the master station upstream, connect to sensing equipment downstream, dynamically perceive on-sit --- ## Research on Automated Optical Inspection of PCB Pads and Gold Fingers - URL: https://intl.sienovo.cn/blog/128893995 - Date: 2023-02-05 - Tags: #AI Introduction A Printed Circuit Board (PCB) refers to a designed device that uses insulating material as a substrate, covered with conductive material traces, and without electronic components installed. The function of a PCB is to provide a physical carrier and electrical connections for various electronic components. Modern PCBs are primarily composed of an insulating part made of fiberglass, fabric materials, and resin, along with epoxy resin and copper foil \[1-3\]. This chapter mainly introduces the current status of PCB defect detection and then summarizes the main research content of this paper. 1.1 Introduction to PCB Inspection Stability and reliability are important indicators in electronic equipment manufacturing, and the quality of Printed Circuit Boards (PCBs), as core components of electronic products, is extremely crucial. Due to the interaction of various equipment operations and environmental factors during the production process, coupled with the complexity of elec --- ## Design of an Online Visual Inspection System for Defects in Large-Format Flexible Printed Circuit Boards - URL: https://intl.sienovo.cn/blog/128891952 - Date: 2023-02-05 - Tags: #PCB, #ImageInspection, #AOI A Flexible Printed Circuit Board (FPCB) is a type of printed circuit board primarily made from polymer films such as polyimide [1]. Compared to traditional PCBs, FPCBs offer advantages such as flexibility, bendability, ease of transmission, and lower overall cost. The subject of this study is a conductive film for a laptop keyboard, which is a flexible circuit board made from PET film (polyethylene terephthalate) as the base material. It boasts numerous advantages including high flexibility, light weight, good conductivity, cost-effectiveness, and environmental friendliness. FPCBs are widely used in control automation, smart electronic devices, modern medical equipment, consumer electronics, and telecommunications [2], as shown in Figure 1.1. Particularly in terms of cost, FPCBs are only half the price of ordinary rigid PCBs, which can significantly reduce product costs. As electronic components trend towards miniaturization and circuit board designs become more complex, flexible circ --- ## Research on Flexible Printed Circuit Board Defect Detection Methods - URL: https://intl.sienovo.cn/blog/128891794 - Date: 2023-02-05 - Tags: #AI, #ComputerVision, #PCBImageInspection ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128891794/01_1195309b745f4f0a3e7965ac1f7af9e8.png) Research on FPC Defect Detection Methods Based on Template Matching Template matching, as the most intuitive and fundamental pattern recognition method, is widely applied in fields such as object recognition and artificial intelligence. It is an effective approach for circuit board defect detection, essentially measuring the similarity between a registered FPC image and an inspection FPC image. This chapter investigates the FPC board defect detection process from the perspective of template matching. Template matching methods can be classified in various ways. Based on the scope of template matching, they can be categorized into two types: global matching and local matching \[8\]. Global template matching treats the deviation of the inspection template relative to the registered template as a spatial image shift, and the entire image is corrected based on this shift. In c --- ## Design of Multi-Model Smartphone Exterior Cleaning and Inspection Equipment - URL: https://intl.sienovo.cn/blog/128888171 - Date: 2023-02-05 - Tags: #ComputerVision, #AI, #PhoneAppearanceInspection Automated smartphone exterior inspection sits at the intersection of precision mechanics, machine vision, and adaptive lighting — and building a single machine that handles *multiple phone models* compounds every challenge. This post walks through the design rationale, sensor selection, and hard-won calibration lessons behind a commercial multi-model smartphone cleaning and inspection line, including two alternative strategies for acquiring phone dimensions without relying on a customer-supplied model database. ## Industry Context The wave of "Made in China 2025" smart-manufacturing initiatives has accelerated demand for in-line optical inspection across the consumer electronics supply chain. Smartphone production in particular spans the full product lifecycle: front-end processes (screen cutting, cleaning, first-pass inspection) through final-assembly stages (exterior cleaning, cosmetic inspection, packaging). Each of these steps is a candidate for automation, and visual inspection --- ## Fully Domestically Produced Loongson 2K0500 Multi-functional SoC Processor and its Solutions - URL: https://intl.sienovo.cn/blog/128470196 - Date: 2022-12-28 - Tags: #2K0500, #FullyDomestic The Loongson 2K0500 integrates on-chip a single 64-bit LoongArch LA264 processor core, 32KB L1 instruction cache, 32KB L1 data cache, 512KB L2 cache, a 32-bit DDR2/3-1066 controller, a 2D GPU graphics core, a DVO display interface, two PCIe 2.0 channels, two SATA 2.0 channels, four USB 2.0 channels, one USB 3.0 channel, two GMACs, a PCI bus, a color and monochrome printing interface, HDA, and other common interfaces, operating at 500-800MHz. It also supports low-power technologies such as ACPI/DVFS/DPM dynamic power management, multiple power levels, and wake-up methods. Based on specific application scenarios, it can dynamically control the clock and power switching for some chip functions and high-speed interfaces, meeting the low-power application requirements in fields such as industrial control and network security. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128470196/01_6461eca8136e8e3b3c0b4e00d6dfe924.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2 --- ## 100% Domestic Loongson 2K1000 Design Solution - URL: https://intl.sienovo.cn/blog/128466427 - Date: 2022-12-28 - Tags: #FullyDomestic Domestic industrial processor, Loongson 2K1000 motherboard, 100% domestically produced solution A fully domestic component solution featuring a homegrown processor. The Xinmai 2K1000 development board adopts the Loongson 2K1000 processor, integrating two GS264 processor cores, operating at a main frequency of 1GHz, equipped with a 64-bit DDR3 controller, and various system I/O interfaces. Verified through extensive project applications, it is widely used in intelligent transportation, automated financial equipment, energy systems, industrial control, CNC machines, charging stations, and other industries. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128466427/01_e3e5e7a18ff8685b2719dcb3d6d8c1a0.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128466427/02_dcd35bf73550c70bc92194abe289f8f6.png) **Loongson 2K1000 Processor Main Features** - Integrated dual-issue superscalar GS264 dual 64-bit processor cores, 1GHz main frequency - On-chip shared 1MB --- ## FPGA-based State Machine Design and Implementation of an EtherCAT Slave - URL: https://intl.sienovo.cn/blog/128461175 - Date: 2022-12-27 - Tags: #FPGADev 0 Introduction EtherCAT, proposed by BECKHOFF, is one of the fieldbuses widely used in industrial control. This bus features full-duplex operation, enabling data transfer based on a Master-Slave connection model, characterized by low latency and high security. The EtherCAT Slave Controller (ESC) is key for slave modules to implement the EtherCAT communication protocol. Currently, communication functions based on the EtherCAT protocol in China are mostly implemented using slave chips like ET1100/ET1200 \[1-4\]. However, besides basic communication functions, these chips also possess numerous other features, and these additional communication mechanisms are not disclosed to Chinese technical personnel. This prevents complete independent control over such communication chips, making it impossible to even discuss adopting effective security mechanisms to enhance system security. With information security issues becoming increasingly prominent in the industrial control sector, the applicat --- ## FeiTeng FT-2000/4 Processor + Fudan Micro FPGA + Domestic Operating System Solution (Part 2) - URL: https://intl.sienovo.cn/blog/128459951 - Date: 2022-12-27 - Tags: #Phytium, #FPGA, #DomesticOS XM-1104 FeiTeng Core Processing Mainboard ▶ Small size, low power consumption, high performance. ▶ Diverse functional interfaces, uses high-density connectors for excellent shock resistance. ▶ Low cost, strong expandability, customizable baseboards according to user needs. ▶ Flexible product, easy to maintain, long lifecycle. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128459951/01_3a309f9ac2ce0ba3966b48fa84fd6be9.jpeg) **Specifications** **Parameters** **Product** FT-2000/4, COM Express® Compact Type 6 **Processor** FT-2000/4 integrates 4 FTC663 processor cores, main frequency 2.2, 2.6, 3.0GHz, L2 cache 4MB, L3 cache 4MB **BIOS** Uboot/UEFI/Custom firmware **Memory** Onboard 16GB domestic DDR4 memory **Ethernet Interface** 1 Gigabit Ethernet port, 10/100/1000M adaptive network signal (FeiTeng CPU embedded network controller) **Serial Ports** 2 TTL serial ports, derived from FeiTeng FT2000/4, where COM0 is the debug serial port and COM1 is the funct --- ## Phytium FT-2000/4 Processor + Fudan Micro FPGA + Domestic Operating System Solution - URL: https://intl.sienovo.cn/blog/128459913 - Date: 2022-12-27 - Tags: #Phytium, #FPGA, #SylixOS XM-1203- FPGA Phytium Custom Motherboard Autonomous and controllable, featuring a domestic CPU, BIOS, and domestic Linux operating system. The FT-2000/4 processor offers stable performance, diverse functional interfaces, strong expandability, high integration, rich interfaces, and excellent electromagnetic compatibility. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128459913/01_3516310ed28b83ceb9c8292b710d0c23.jpeg) The XM-1203-FPGA is a non-standard custom processor board based on the Phytium 4-core CPU FT-2000/4, featuring clock speeds of 2.2 and 2.6GHz. This quad-core processor product offers low power consumption, strong overall performance, high stability, rich interfaces, and strong expandability, making it particularly suitable for the standard embedded industrial control industry. **Specifications** Parameters **Product** FT-2000/4, Non-standard custom motherboard **Processor** FT-2000/4, integrates 4 FTC663 processor cores, clock speed 2.2, 2.6GHz, 4M --- ## Domestically Produced Fudan Micro FMQL45T900 ZYNQ7045 ARM+FPGA Development Platform - URL: https://intl.sienovo.cn/blog/128419265 - Date: 2022-12-23 - Tags: #FPGADev, #FMSHZYNQ FM4550 Domestically Produced Development Board Functional Interfaces - ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128419265/01_843998df872d001a4949df2a76947889.png) \- System Block Diagram - ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128419265/02_83a8a06ee12e919259c8b4bfea7b2a1f.png) 01 \- Product Parameters - 1. Key Parameters System 1: FPGA Model: FMQL45T900 PS Core: Quad-core ARM Cortex-A7, main frequency 800MHz PS-side Memory: 1GB DDR3, data rate 1066Mbps, 32bit PL-side Memory: 1GB DDR3, data rate 1600Mbps, 32bit GTX Transceivers: 16X Speed Grade: Comparable to imported -2                        Chip Grade: Industrial Grade Operating Temperature: -40℃-100℃                       Logic Cells: 350k Look-Up Tables: 218600                             Multipliers: 900 Flip-Flops: 437200                             Block RAM: 19.1Mb EMMC FLASH:  8GB                         QSPI FLASH: 128Mbit\*2 System 2: FPGA Model: JFMK50TFGG484 --- ## XMC4800 EtherCAT Slave-Based Factory Automation Solution - URL: https://intl.sienovo.cn/blog/128410412 - Date: 2022-12-22 - Tags: #Automation, #XMC4800, #EtherCATSlave **Background** With the introduction of the concepts of "Industry 4.0" and "Industrial Internet," the idea of "Internet + Manufacturing" has become widely known to the public, often referred to as the Fourth Industrial Revolution. Against this backdrop, new industrial automation has emerged. Smart factories, Industry 4.0 solution providers offering smart factory design and implementation, and technology suppliers have successively appeared. ARROW deeply collaborates with solution providers and technology suppliers to offer channels for realizing smart factories. Servo systems, as one of the most crucial control and execution mechanisms in industrial automation, are widely applied in fields such as machine tools, textile machinery, printing machinery, and packaging machinery. Simultaneously, with the rapid expansion of industries like industrial robots and electronic manufacturing equipment in recent years, the application scale of servo systems in emerging industries has grown rapidl --- ## EtherCAT I/O Motor Control Robot Slave Controller Design - URL: https://intl.sienovo.cn/blog/128409126 - Date: 2022-12-22 - Tags: #ETHERCAT, #Slave The AX58100 is a cost-effective EtherCAT slave controller that is **certified by Beckhoff Automation** and **integrates two Fast Ethernet physical interfaces** that **support 100Mbps full-duplex and HP Auto-MDIX**. The AX58100 supports all EtherCAT systems, including standard EtherCAT devices (e.g., CoE, FoE, VoE, etc.). The AX58100 provides a highly cost-effective EtherCAT solution for applications such as drive/motor/data I/O control, digital-to-analog conversion, analog-to-digital conversion, variable frequency controllers, and image data acquisition! The AX58100 offers **a three-channel PWM controller or a stepper controller**, along with an additional (ABZ)/Hall encoder interface for closed-loop management of control applications such as drives/motors; it provides an SPI **master** to manage DAC/ADC converter control applications and image data acquisition applications; and it also includes an I/O watchdog and an **emergency stop input** for industrial automation safety applicat --- ## Overview of SI/PI Simulation: Active High-Speed Signals, Impedance, and Filtering Solution Analysis - URL: https://intl.sienovo.cn/blog/128405320 - Date: 2022-12-22 - Tags: #SIPISimulation **Overview of SI/PI Simulation** Signal Integrity (SI) and Power Integrity (PI) are two critical factors that must be ensured in today's high-speed electronic product systems and PCB designs. SI/PI directly determine the quality of system signals and power, thereby affecting correct data transmission and system bit error rate. To evaluate and simulate SI/PI during the design phase, professional EDA tools are required for simulation analysis. The accuracy of SI/PI simulation analysis and its correlation with actual test results depend on the accuracy of the simulation models themselves on one hand, and on the correctness of the simulation methods and the experience of the simulation designer on the other hand. Xinmai possesses a team of experienced SI/PI simulation engineers, a simulation model library validated by actual tests, mature design experience, and successful case studies. This enables us to help clients quickly resolve SI/PI issues during the design and testing phases. * --- ## Evaluating EtherCAT Slave Node Solutions - URL: https://intl.sienovo.cn/blog/128404576 - Date: 2022-12-22 - Tags: #TI C2000, #EtherCATSlave, #F28338 Part 1 of this blog series introduced the market opportunity for EtherCAT slave stack solutions for C2000™ microcontrollers and a three-stage quick-start guide for slave stack development. Part 2 detailed the features and benefits of the TI C2000 MCU EtherCAT implementation. Part 3 described the three stages of developing a slave node application using an EtherCAT slave and a C2000 Delfino MCU controlCARD kit, and how the EtherCAT package in TI C2000 controlSUITE™ software supports each stage. This blog post, as Part 4 of the series, will introduce how to develop an EtherCAT slave controller using the latest C2000 TMS320F28388D real-time controller. The C2000 F28388D MCU incorporates Beckhoff's EtherCAT peripheral module, integrating it onto the chip. Ownership of the EtherCAT peripheral module can be assigned to either CPU1 or CM. To support this functionality, a set of software solutions has been added to C2000Ware (C2000 microcontroller software package). These F28388D EtherCAT so --- ## EtherCAT Slave Design and FOC Servo Motor Current Loop Control - URL: https://intl.sienovo.cn/blog/128404322 - Date: 2022-12-22 - Tags: #FPGA, #EtherCATSlave, #FOC, #CurrentLoop Introduction to EtherCAT Slave Development Solutions - Including ET9300 Comparison General EtherCAT Design Requirements (for uC+ESC solutions): Hardware: Main controller uC + ESC (EtherCAT Slave Controller, selectable from various vendors) Operating System: No special requirements, determined by product performance, an OS may not even be necessary. Software: The main controller uC needs to handle EtherCAT message communication. ESCs typically come with development kits for easy porting. Challenge: How to achieve data interaction between the uC and ESC. Requirements for Vendors: Provide high-quality source code (high code efficiency, optimized EtherCAT performance) Provide at least one hardware platform demo Provide complete EtherCAT network diagnostic and configuration tools: for testing, etc. A typical slave includes the following three core components: Physical Layer: Requires an Ethernet port Data Link Layer: Includes an EtherCAT Slave Controller (ESC) (this is the comm --- ## Design of a Controller for a Semiconductor Motion Stage for Wafer Inspection (Part 2) - URL: https://intl.sienovo.cn/blog/128399985 - Date: 2022-12-21 - Tags: #AI Although the overall research and development of precision wafer inspection motion stages in China is currently relatively nascent, it is worth noting that considerable experience has been accumulated in the research of X-Y two-degree-of-freedom motion stages, and even multi-degree-of-freedom motion stages, advanced drive methods, and control strategies. Incorporating this experience into the development of this motion stage will be beneficial for selecting the correct mechanical structure, utilizing advanced drive methods, implementing appropriate control strategies, accelerating project progress, and ensuring project completion. A comparison between standardized precision motion stages from abroad and domestic precision stages is provided below. Japan has accumulated many years of experience in the manufacturing of precision equipment and holds a leading position internationally. Japanese precision equipment manufacturer THK offers precision XY stages that share many similarities w --- ## High-Speed High-Precision Semiconductor Motion Stage Design (Part 2) - URL: https://intl.sienovo.cn/blog/128393121 - Date: 2022-12-21 - Tags: #SemiconductorStage, #Controller The performance of high-speed, high-precision motion platforms is not only related to the motion controller and servo drives but also closely linked to the performance of the motor itself. The motion platform shown in Figure 5-2 utilizes Yaskawa linear motors, which directly drive the load, offering high rigidity and fast response. Concurrently, a high-performance multi-axis motion control card and GTHD series high-performance servo drives were selected as the platform's servo control system. X-Y Motion Platform Position Detection Device The accuracy requirements for high-speed, high-precision motion platforms are at the _μm_ level, which necessitates the selection of high-resolution detection devices. Commonly used position detection devices for linear motors include lasers, magnetic scales, inductive synchronizers, and optical encoders. Laser devices, as detection devices, offer high accuracy and stability but come at a high cost. Both magnetic scales and inductive synchronizers a --- ## Mechatrolink III to EtherCAT Gateway Module Solution - URL: https://intl.sienovo.cn/blog/128356770 - Date: 2022-12-21 - Tags: #EtherCATConverter **Overview** Industrial Ethernet is becoming increasingly popular in the industrial control field, with many types of protocols such as Mechatrolink III, EtherCAT, Powerlink, Profinet, EtherNet/IP, etc. In the CNC machining field, the mainstream protocols are Mechatrolink III and EtherCAT. However, communication and interoperability between various protocols are challenging. Yaskawa Electric's Mechatrolink III is an advanced Industrial Ethernet technology widely used in the CNC machining field. Servo devices mostly adopt Mechatrolink III, but lack supporting I/O or sensing devices. Domestic I/O or sensing devices mostly use EtherCAT, with relatively abundant resources. The MIE SoC module for Mechatrolink III to EtherCAT Master effectively solves the problem of the Mechatrolink III protocol lacking supporting devices, enabling quick access, reducing system burden, and simultaneously supporting access for multiple I/O devices. **Mechatrolink III to EtherCAT Solution** Existing solut --- ## FPGA EtherCAT Master PCIe Acceleration Card Based on Linux + Xenomai Real-time System - URL: https://intl.sienovo.cn/blog/128355421 - Date: 2022-12-21 - Tags: #ethercat, #pcie, #linux+xenomai Overview Both commercial and open-source EtherCAT masters implement master functionality using software, with their performance largely depending on the PC's performance and the operating system's real-time capabilities. Xinmai, however, implements the EtherCAT protocol layer using pre-programmed FPGA logic, allowing customers to use it as a dedicated chip. ![](https://pub-048dcb96257f476697b113fc5939cb9.r2.dev/blog/128355421/01_df86c3fc1519274059ac03a3c2a08f60.png) The EtherCAT max10 chip implements the standard EtherCAT master protocol, utilizing a standard general-purpose parallel bus interface that can connect to and control any CPU. It supports ARM or x86 processor platforms. It provides reference software code, API functions, XML file system initialization, and other software. It can be used for controlling any standard EtherCAT motors and I/O devices. ![](https://pub-048dcb96257f476697b113fc5939cb9.r2.dev/blog/128355421/02_617b029a78363fab034a7ef12f9c0be5.png) Features ⦁ --- ## High-Speed High-Precision Semiconductor Motion Stage Design (Part 1) - URL: https://intl.sienovo.cn/blog/128324807 - Date: 2022-12-21 - Tags: #Manufacturing, #SemiconductorStage Whether it's wafer manufacturing equipment like lithography machines and etching machines, or semiconductor back-end packaging equipment such as die bonders and wire bonders, the XY motion stage is a core component of these devices. The performance of the motion stage dictates the overall performance of the equipment. The main characteristics of high-speed high-precision motion stages are high speed, high acceleration, and high precision. High speed and high acceleration can improve equipment production efficiency, while high precision significantly impacts product quality. In different application fields, precision can be categorized into high positioning accuracy and high contouring accuracy. For instance, in high-end CNC machining, where contour error requirements are stringent, the focus is on high contouring accuracy. In semiconductor packaging equipment, which involves point-to-point motion, the emphasis is on high positioning accuracy. Currently, the technical level of high-sp --- ## Custom Design Solution for Host Computer Industrial Software in Semiconductor and New Energy Intelligent Equipment - URL: https://intl.sienovo.cn/blog/127877583 - Date: 2022-12-21 - Tags: #EquipmentIndustrialSoftware, #SemiconductorSoftware, #NewEnergySoftware, #IndustrialSoftwareCustom 一、Overview If PLCs are the 'cerebellum' of industrial control, then host computer software acts as its 'brain'. Conceptually, the controller and service provider is the host computer, while the controlled and serviced entity is the lower-level device. The host computer typically handles digital signal processing and command issuance, while the lower-level device usually handles analog signal processing and command execution. The hardware for host computers is generally industrial PCs or industrial control computers. The operating systems running on host computers can typically be Windows, Linux, HarmonyOS, etc., with different OSes chosen based on varying performance requirements. The software running on host computers is usually custom-developed specialized software. Some large manufacturing companies or enterprises often have their own R&D teams, while others choose to outsource the host computer software development. **二、Main Application Industries for Host Computer Software** --- ## Domestic Real-time Operating System + Intel x86/Loongson Platform Hyper-Edge Computer Solution - URL: https://intl.sienovo.cn/blog/128357056 - Date: 2022-12-17 - Tags: #5G, #AI Introduction In recent years, technologies such as IoT, cloud computing, machine learning, and cybersecurity have continuously driven the development of Industry 4.0. The "cloud-edge-device" architecture is gradually replacing the "cloud-pipe-device" architecture, and edge computing has become a key element for transformation in many fields in the new era. Taking smart manufacturing as an example, unlike CDN edge computing technology serving the internet, industrial sites also require more powerful and intelligent hyper-edge computers to directly serve data sources. It can operate in a closed local area network environment, directly providing intelligent computing services for OT (Operational Technology) devices. Through configurations of various specifications and multiple expandable hardware interfaces, it fully meets the demands for computing power and data storage in various industrial computing scenarios. Through local high-speed Ethernet or 5G private networks, it meets the net --- ## RF Solution Based on AD936X and Intel FPGA - URL: https://intl.sienovo.cn/blog/128356884 - Date: 2022-12-17 - Tags: #FPGADev, #AD9361 An RF solution based on ADI AD936X and Intel Cyclone V FPGA is suitable for applications such as wireless communication infrastructure, defense electronics systems, RF test equipment and instrumentation, and general-purpose software-defined radio (SDR) platforms. About the ADI AD936X Series RF Transceiver The AD936X series operates over a frequency range from 70 MHz to 6 GHz. It is a complete radio design, a single-chip integrated solution. It integrates multiple functions, including an RF front-end, mixed-signal baseband section, frequency synthesizer, analog-to-digital converter (ADC), and direct conversion receiver. The AD936X supports channel bandwidths from below 200 kHz to 56 MHz, offers high programmability, boasts an unparalleled dynamic range in today's market, and provides leading noise figure and linearity performance, as well as an economical and low-power radio solution. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128356884/01_4bcdd60b2753d22d2b5a6809e --- ## Cyclone V-based USB3.0/GIGE Industrial Camera Module Design Solution - URL: https://intl.sienovo.cn/blog/128356797 - Date: 2022-12-17 - Tags: #AI, #ComputerVision Designing a compact industrial camera module requires careful selection of every component in the signal chain — from the image sensor front-end through ISP processing, memory subsystem, and host interface. This post walks through a Cyclone V FPGA-based camera module design that supports up to 2-megapixel image sensors and offers either USB 3.0 or GigE Vision connectivity, making it a flexible platform for machine-vision and edge-AI inspection applications. ## Design Goals Industrial camera modules differ from consumer webcams in several key ways: they demand deterministic low-latency image delivery, robust noise immunity in electrically harsh factory environments, and long product-lifecycle component availability. The design described here targets: - Up to **2 MP** sensor support with a scalable ISP pipeline - Dual host interface support: **USB 3.0** (SuperSpeed, up to 5 Gbps) and **GigE Vision** (1 Gbps with standardized GenICam control) - Compact form factor suitable for integrat --- ## FPGA-Based Solution for Low-Latency Professional-Grade 4K AV Signal Transmission over 1Gb Ethernet - URL: https://intl.sienovo.cn/blog/128356520 - Date: 2022-12-17 - Tags: #fpga, #4K The ME10 SoC is a full-stack AV over IP System-on-Chip (SoC) capable of transmitting HDMI 2.0 4K 4:4:4 video, audio, and control data over a 1Gb network. The ME10 SoC comes in a small 23 x 23 mm BGA package. Its key features are interoperability and superior performance. IPMX is a collection of open standards and specifications for AV over IP, specifically developed for the professional AV market. The ME10 is ready for AIMS IPMX. Interoperability standards include device discovery and registration, USB and serial extension, resilient network performance, sub-frame latency, and JPEG-XS compression. IPMX is an industry-awaited standard. Built on this interoperability platform, the ME10 provides a complete AV over IP solution for all your product lines. The included web stack features a RESTful configuration API, providing full access to ME10 functionalities. The customizable web interface is clean and intuitive. JPEG-XS compression delivers a truly immersive and transparent desktop ex --- ## Control and Implementation of a DSP+FPGA-Based High-Speed Macro-Micro Semiconductor Motion Platform - URL: https://intl.sienovo.cn/blog/128332680 - Date: 2022-12-15 - Tags: #SemiconductorStage In semiconductor chip manufacturing equipment, to achieve high quality and high efficiency in semiconductor chip manufacturing, its moving parts typically require high motion performance. For example, in high-end wire bonders, the motion platform is usually required to achieve a positioning accuracy of 1-2 μm at an acceleration of 15-20g and a motion frequency of 15-20Hz [3]. For typical chip lithography machines, the motion platform needs to achieve tens of nanometers of positioning accuracy over a long stroke of 100-150mm [4]. Furthermore, as semiconductor chips continue to evolve towards higher efficiency and greater precision, to further meet the high-end demands of the microelectronics manufacturing industry, high-acceleration precision motion platforms in semiconductor chip manufacturing equipment must simultaneously satisfy comprehensive requirements for large stroke, high dynamic response, and high-precision positioning. Macro-micro motion platforms combine the characteristics --- ## Design of a Controller for Semiconductor Wafer Inspection Motion Stages - URL: https://intl.sienovo.cn/blog/128325493 - Date: 2022-12-15 - Tags: #SemiconductorStage, #Controller Multi-degree-of-freedom precision motion stages are a crucial issue in wafer manufacturing and inspection processes within the semiconductor industry. Compared to traditional motion stages driven by ball screws and rotary motors, precision motion stages employing advanced drive methods such as linear motors and voice coil motors offer numerous advantages, including high precision, fast response, long lifespan, maintenance-free operation, and simple structure. Their advantages are highly significant, and thus they are increasingly valued by the production and research fields of high-precision motion stages. To adapt to the rapidly advancing IC technology's demand for front-end wafer manufacturing technology, developed countries attach great importance to developing advanced silicon wafer manufacturing technologies and equipment. Currently, 200mm wafer processing technology is widespread abroad, and 300mm diameter wafers are becoming widespread. According to historical patterns, the up --- ## 3U Rail Transit Vehicle-mounted Industrial-grade M12 PoE Switch, IP66 Protection Rating - URL: https://intl.sienovo.cn/blog/128296457 - Date: 2022-12-13 - Tags: #RailTransit, #NetworkSwitch Rail transit industrial switch supporting software and hardware customization services Supports dual power redundancy Supports Bypass Ethernet data communication equipment specifically designed and manufactured for rail transit applications Train-level backbone Ethernet core equipment implemented according to IEC61375-2-5 and IEC61375-2-3 protocols Supports China Railway product certification ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128296457/01_61c2fa9ae4294e9e5c7a73e04d0b6bf5.png) The XM-5145 industrial switch is a Layer 2 managed switch specifically designed and developed for harsh environments such as rail transit, marine, and vehicle-mounted applications. The product design complies with rail transit industry certifications. It uses M12 connectors to ensure stable network communication in vibrating environments. The entire unit adopts a fanless passive cooling design, ensuring long-term stable operation in a -40°C to 75°C operating environment. The uniq --- ## Intel-based In-vehicle M12 Managed Switch Solution with 13 Ethernet Ports and Bypass Function Support - URL: https://intl.sienovo.cn/blog/128291009 - Date: 2022-12-12 - Tags: #Networking ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128291009/01_6d8ad5590ee82f854b21a1632951dd95.png) Overview: The XM-5130 is a Layer 2 managed Ethernet switch. Its front panel provides 13 100M auto-sensing Ethernet ports and 4 inter-vehicle Ethernet ports with Link Aggregation and bypass functionality. The interfaces are provided via M12 connectors. This product is suitable for harsh operating environments with significant vibration, temperature and humidity fluctuations, large power supply variations, and complex electromagnetic interference. Strict EMC principles were followed during the design process, enabling it to meet the demanding operating conditions of railway industrial on-board train applications, and it can be extended to other critical mission systems in harsh environments. **XM-5130 Specifications** | Product Type | In-vehicle Managed Industrial Switch | | :----------- | :--------------------------------- | | IP Rating | IP67 --- ## Edge AI Gateway Rapidly Boosts Air Compressor Applications - URL: https://intl.sienovo.cn/blog/128290652 - Date: 2022-12-12 - Tags: #FPGADev, #Energy ### Application Requirements In the era of IoT, the number of devices connected to the internet is increasing daily. A recent report from Strategy Analytics predicts that by 2025, 38.6 billion devices will be connected to the IoT. The rapid proliferation of the IoT wave leads to the generation of massive amounts of data, and edge computing gateways are rapidly becoming key components for device management, data collection, and transmission. Customer Pain Points A well-known air compressor manufacturer hopes to deploy a solution that can acquire real-time equipment operational data (temperature, pressure, vibration, and runtime) and perform compressor analysis, lifespan evaluation, and predictive maintenance. Since air compressors are often installed in harsh environments lacking Ethernet infrastructure, **a suitable edge computing gateway must meet the following requirements: wide voltage input for unstable power supplies; a broad operating temperature range to withstand harsh envi --- ## Intel Low-Power Platform-Based Edge Computing Solution Boosts Semiconductor Equipment Upgrade - URL: https://intl.sienovo.cn/blog/128288162 - Date: 2022-12-12 - Tags: #SemiconductorEquipment, #Controller Semiconductor chips are the brains of modern electronics. In fact, in communication, computing, retail, healthcare, and transportation applications, semiconductor chips provide the foundation for various advanced technologies. Global semiconductor sales grew by 6.5% in 2020, and the production demand for related manufacturing equipment increased accordingly. A Japanese semiconductor equipment manufacturer in the industry is developing a new type of semiconductor lithography machine for 300mm and 200mm wafer advanced packaging processes. The semiconductor lithography system is designed to handle Fan-Out Panel Level Packaging (FOPLP) in semiconductor packaging processes. This new semiconductor lithography system requires multiple reliable, high-end edge computers as support to upgrade equipment performance and achieve high-speed, high-precision imaging. At the same time, this series of edge computers requires a fanless design, high computing power, cost advantages, and interfaces neces --- ## Implementing Device AI and Smart Data Transformation on Intel+FPGA Platforms - URL: https://intl.sienovo.cn/blog/128282028 - Date: 2022-12-12 - Tags: #AI ### Digitalizing Smart Devices Through AI and Data Transformation Data collection, visualization, automatic control, and AI analysis effectively facilitate device intelligence (M2I) and Industrial AI, serving as the foundational elements and two gears driving the advancement of smart manufacturing. By empowering smart device functions through "Device Intelligence" and "Industrial AI," smart operations and management can be achieved. Enable Smarter Device Operation ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128282028/01_34a122e4e8fa4c88b0ef7e9d6cc2d002.png) #### Providing Comprehensive Services for the Semiconductor and Automated Test Equipment Industries Semiconductor manufacturing is a complex process composed of many individual steps. From wafer fabrication/sorting to assembly/testing/shipping, many process steps have very strict tolerances. Each step affects subsequent steps, and each parameter is the result of many different inputs. #### Realizing the Futur --- ## Intel® Core™ i5-Based Robot Controller - URL: https://intl.sienovo.cn/blog/128270065 - Date: 2022-12-10 - Tags: #Robotics, #5G The XM-6815 is a compact, wall-mountable embedded industrial PC from Sienovo, built on Intel's 11th Generation Core i-series platform. Designed for demanding industrial environments, it targets applications such as robotic arm controllers, machine vision processing nodes, and AGV (Automated Guided Vehicle) control units — use cases that require a combination of real-time serial communication, multi-network isolation, and reliable 24/7 operation inside control cabinets or on mounting rails. ## Platform and Processing At the heart of the XM-6815 are two CPU options from Intel's Tiger Lake-H embedded product line: - **Intel® Core™ i3-1115G4E** — a dual-core, four-thread processor with a base clock of 2.2 GHz (burst to 4.1 GHz), designed for sustained industrial workloads with extended availability guarantees. - **Intel® Core™ i5-1145G7E** — a quad-core, eight-thread variant clocking up to 4.1 GHz, adding Intel® Iris® Xe Graphics for light machine vision inference or multi-display scena --- ## Applications of Intel® Celeron/i3/i5 Wall-mounted Fanless Industrial PCs in Machine Vision - URL: https://intl.sienovo.cn/blog/128252398 - Date: 2022-12-10 - Tags: #linux, #DevOps, #Server ## XM-5131 Wall-mounted Fanless Industrial PC The XM-5131 is a wall-mounted fanless industrial PC based on Intel 6th/7th generation Core i-series platform CPUs, featuring expandable memory slots, 1× mSATA, 3× Gigabit Ethernet ports, 6× COM ports, 4× USB 3.0, and 4× USB 2.0. This product is suitable for wall-mounted applications such as industrial robot controllers and machine vision controllers. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128252398/01_f2b3728a5d10022c5dafc5a0606db86c.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128252398/02_8ec68df10abe0c2ffb0c725bd6ff4474.png) **XM-5131 Specifications** Product Type Wall-mounted Fanless Industrial PC Protection Rating IP4X Chipset SOC CPU Intel® Celeron™ 3855U, 1.6GHz Intel® Core™i3-6100U, 2.3GHz Intel® Core™i5-6200U, 2.3GHz Intel® Core™ i7-7600U, 2.8GHz Memory Expandable DDR3L Memory BIOS AMI UEFI Ethernet Intel i211 Gigabit Ethernet \*3 RJ45 Independent Intel Controllers --- ## Wafer-Level Flip Chip Bonder and Control System - URL: https://intl.sienovo.cn/blog/128230956 - Date: 2022-12-08 - Tags: #FPGADev ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128230956/01_b1873022b64ee0318f3963c1cd72028b.png) The wafer-level flip chip bonder is mainly composed of the wafer tray feeding module, wafer tray workbench module, flip chip module, bonding head module, substrate workbench module, dispensing module, vision module, and substrate loading/unloading module, as shown in Figure 2-2. Wafer-Level Flip Chip Bonder Control System Architecture The motion control system of the wafer-level flip chip bonder is mainly composed of an industrial PC (IPC), motion control card, drivers, feedback devices, and a linear motor motion platform. The IPC serves as the host computer for the entire motion control system. The motion control card is directly plugged into the IPC's PCIe interface slot and allows for custom design of servo control algorithms. It controls the drivers by outputting analog DAC commands. The drivers are set to current loop control mode, amplifying and processing the input --- ## Excellent Computing Performance for Semiconductor and Integrated Circuit Test Equipment Based on Intel Lake-UP3 Platform - URL: https://intl.sienovo.cn/blog/128208897 - Date: 2022-12-06 - Tags: #FPGADev **Why do Semiconductor and IC Test Equipment Need Upgrades?** With the increasing demand for numerous new high-performance applications, Xinmai aims to provide better solutions for customers in the semiconductor and integrated circuit test equipment field. Semiconductor and integrated circuit (IC) test equipment is designed to simultaneously batch test hundreds of integrated circuit boards and chipsets on different lines within a single test machine, such as CPUs, SoCs, SSDs, and memory products. To batch test integrated circuit products at a lower cost and more efficiently, IC test equipment tends to have an equal number of functional boards corresponding to each device under test (DUT), with these functional boards testing the integrated circuits via pre-loaded test programs. As test programs become increasingly complex, to shorten the average test cycle, core requirements for larger memory capacity and faster data transfer speeds must be met. Since a single integrated circuit test --- ## Ultrasound Equipment Solution Design Based on Intel Lake-UP3 Platform, Offering Excellent Graphics and AI Performance - URL: https://intl.sienovo.cn/blog/128208669 - Date: 2022-12-06 - Tags: #AI, #Intel+fpga, #UltrasoundEquipment **Ultrasound System Requirements** Effective ultrasound systems accelerate diagnosis and help doctors make faster, more effective treatment decisions. To achieve this, ultrasound machines demand extremely high processing performance and graphics rendering capabilities to improve diagnostic accuracy and acquire precise images instantly. Similarly, they also need to be highly portable to adapt to evolving medical scenarios and trends, especially when treating patients with mobility issues or travel/activity restrictions due to COVID-19. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128208669/01_2b2a7cddbc34ce2b04fb936dccccca47.jpeg) **Challenges** High-end ultrasound systems typically leverage FPGAs, graphics cards, or AI accelerator modules to achieve high computational and graphics performance, leading to complex system designs and higher costs when integrating additional GPU or VPU engines. Furthermore, in pursuit of extreme performance, these systems inevitably en --- ## X86-based Compute Board Accelerating Edge AI Applications - URL: https://intl.sienovo.cn/blog/128177791 - Date: 2022-12-04 - Tags: #5G, #intel The XM-SOM-6801 is a standard COM Express Type 6 module based on the Haswell-M platform. It adheres to the standard COM Express Type 6 specification, with dimensions of only 125mm × 95mm. This module integrates a range of CPUs from the Haswell-M platform, covering high, mid, and low tiers, specifically the I7-4900MQ, I5-4300M, and I3-4100M CPUs. These CPUs offer powerful computing capabilities and can be widely applied in fields such as communications, industrial automation, and medical equipment, meeting diverse customer requirements. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128177791/01_c353d2db3e25011b9d23867b71cb8681.png) XM-SOM-6801 Specifications Product Type COM Express Type 6 Chipset SOC CPU Intel I3-4100M, 2.5GHz, Dual-core Processor Intel I5-4300M, 2.6GHz, Max Turbo Frequency 3.3GHz, Dual-core Processor Intel I7-4900M, 2.8GHz, Max Turbo Frequency 3.8GHz, Quad-core Processor Memory Onboard 4G/8G optional DDR3L memory; 1×memory slot, supports up t --- ## Design and Implementation of an EtherCAT Master Based on ARM + FPGA - URL: https://intl.sienovo.cn/blog/128164666 - Date: 2022-12-03 - Tags: #FPGADev To address issues such as real-time performance and stability arising from the application of the real-time industrial Ethernet protocol EtherCAT to embedded master controllers, this paper first investigated the functional requirements of the EtherCAT master controller in an EtherCAT network control system. An architecture for implementing an embedded EtherCAT master was then analyzed and proposed. Subsequently, a hardware solution for implementing an EtherCAT master based on ARM + FPGA was designed for this architecture, along with a software implementation solution based on a real-time Linux operating system with Xenomai patches. Finally, an interconnected and interoperable testing platform was established. Experimental results demonstrate that this master controller exhibits compatibility with the EtherCAT standard protocol, extremely high real-time performance, and stability. Real-time industrial Ethernet technology has evolved from conventional Ethernet technology. Because tradi --- ## RV1126/RV1109 IPC Board + RK3568 + HarmonyOS AI Video Solution - URL: https://intl.sienovo.cn/blog/128164318 - Date: 2022-12-03 - Tags: #harmonyos, #AI, #Huawei In recent years, cloud terminal products have been widely adopted in industries such as office, education, and industrial control due to their practicality, low maintenance requirements, and enhanced data security, making them highly favored in the market. However, under complex conditions—such as variable lighting, heavy pedestrian and vehicle traffic, and diverse human movements—image quality, visual performance, and detail rendering capability are key technical indicators for evaluating IPC (Internet Protocol Camera) solutions. The combined solution of RV1109 and RK3568 for network camera IPC transmission improves network transmission efficiency. RK3568 supports simultaneous decoding of multiple video streams, featuring a next-generation security-focused ISP (Image Signal Processor) with 8M@30fps processing power. It enables time-division multiplexing, dual-channel simultaneous scaling output, and advanced noise reduction, delivering fine-grained images even under low-light condit --- ## Allwinner T3 ARM+EtherCAT+Codesys Industrial Controller Design Solution - URL: https://intl.sienovo.cn/blog/128163360 - Date: 2022-12-03 - Tags: #AllwinnerT3, #codesys, #RTOS, #FullyDomestic Currently, Codesys + EtherCAT drives offer significant advantages for motion control. Nowadays, bus-based motion control mostly uses this configuration. Codesys is known as the Android of the PLC world, and domestic PLC manufacturers mostly use the Codesys kernel. Such as: Inovance, Co-Trust, Hollysys, Invt, Delta. Including international ones: Beckhoff TwinCAT 2, Schneider SoMachine, Rexroth, etc., all use Codesys. Intuitively speaking, Codesys is a software PLC with pre-written motion control and communication functionalities. In motion control, the PLCopen protocol is a programming standard for PLCs. TIA Portal's motion control also uses PLCopen Motion, and Codesys supports the PLCopen standard. Additionally, Codesys also supports high-level languages; for example, C++ functions can be called within Codesys. For another example, Codesys can also define multi-tasks, similar to parallel computing in high-level languages. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev --- ## AGV Mobile Robot and Autonomous Forklift Controller Design - URL: https://intl.sienovo.cn/blog/128126234 - Date: 2022-12-01 - Tags: #AGVController The AGV controller is a general-purpose controller designed for mobile robots (AMRs, smart forklifts, etc.), providing core functionalities such as map building, localization and navigation, and model editing for mobile robots. This solution integrates the core components of mobile robots into one unit, and with powerful client software, it helps users quickly set up robots. In addition, it has gradually evolved into a controller for smart factory infrastructure, capable of controlling automatic charging stations, automatic doors, elevators, traffic lights, and more. Under a unified scheduling interface framework, it drives the intelligent transformation and automation expansion of the entire factory. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128126234/01_ab9a5981cc2f273f93936a06fd8dfef7.png)  ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128126234/02_510c537da2b57f124afdb15f9d79e767.png) The main control methods for AGV systems include centralized --- ## 3D视觉识别案例：3D无序棒料抓取,阀体圆环上下料,电机定子上料 - URL: https://intl.sienovo.cn/blog/128102950 - Date: 2022-11-29 - Tags: #3d ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128102950/01_650d5a5eb99b2899c256d35cf55e0866.png) **3D Bin Picking of Disordered Rods** A leading automotive industry company **Project Background** A renowned automotive company in Changchun required 3D vision to automate the loading of circular rods. **Operation Process** Steel rods are sequentially cut/sawed, picked from a deep bin, first placed on a V-shaped secondary positioning platform, and then picked from the platform onto a conveyor line. The target workstation is a heating equipment with a conveyor chain. **Solution Highlights** • **Motion Trajectory Planning:** Automatic avoidance of singular points during motion trajectory planning ensures safe and smooth trajectories. No manual teaching is required; the online collision-free motion planning algorithm generates collision-free, time-optimal paths. • **Topple Function:** To achieve 100% bin clearance, a topple function was developed, allowing obscured wo --- ## 3D Vision Application Cases: Automated Loading of Flange Parts, Engine Hoods, Control Arms, and Wheel Hub Picking for Racking - URL: https://intl.sienovo.cn/blog/128102873 - Date: 2022-11-29 - Tags: #3d ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128102873/01_f701370b2f187540cb762d14a9f02cb5.png) **Flange Part Loading** A Large Automotive Parts Manufacturer **Project Background** The client is a well-known foreign-funded automotive parts enterprise. Its factory located in East China requires 3D vision to automate the loading of sandblasting machines. The workpieces are plate-shaped, porous metal parts, with a thickness of only 5mm. They are neatly stacked in deep bins and need to be loaded at high speed onto the sandblasting machine. **Operation Process** • Manual transport of material bins into position, vision system locates bin position. • Vision system captures images to guide the robot to pick up 4 pieces in a row, placing them in parallel onto the sandblasting machine. • Repeat the above actions until the bin is empty. **Solution Highlights** • Uses XM-GX-L camera, with an accuracy of ±2mm. • Vision cycle time <3s, overall cycle time <5s, maximizing --- ## 3D Vision Application Cases: Guided Part Localization and Grasping - URL: https://intl.sienovo.cn/blog/128095021 - Date: 2022-11-29 - Tags: #3d, #AI ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128095021/01_ab84d8b4a1de2248e8ae3ba8cb6433c0.png) **3D Guided Part Localization and Grasping** A Renowned Mold and Steel Group **Project Background** A renowned mold and steel group in Guangzhou required 3D-guided part localization and grasping, along with 2D identification information acquisition capabilities. The original setup, which used gantry cranes and manual handling, had an extremely low safety factor. **Workflow** • After the 3D camera visually identifies the product's position, a robot equipped with an electromagnet grasps the product. • Before placing it onto the secondary positioning fixture, a laser and sensors inspect the product specifications. A 2D camera then identifies QR code labels to differentiate product materials. **Solution Highlights** • **Vision Algorithm:** For workpieces with extremely high reflectivity, which cause specular reflections in point clouds, a unique vision algorithm reduces --- ## RK3568 OpenHarmony-based Agricultural Financial Service Terminal Design Solution - URL: https://intl.sienovo.cn/blog/128091517 - Date: 2022-11-29 - Tags: #5G **Background** The No. 1 Central Document of 2022, "Opinions of the Central Committee of the Communist Party of China and the State Council on Key Work for Comprehensively Promoting Rural Revitalization in 2022," proposed strengthening financial services for rural revitalization. "The 14th Five-Year Plan for Promoting Agricultural and Rural Modernization" emphasized improving the rural financial service system and included the "Rural Revitalization Financial Service Action" in the new round of rural reform initiatives. "The Rural Revitalization Strategic Plan" proposed, "establishing a rural financial system suitable for the characteristics of agriculture and rural areas, allocating more financial resources to key areas and weak links in rural economic and social development, and better meeting the diverse rural financial needs of rural revitalization." Major banks have also successively introduced financial service policies benefiting farmers in response to the rural revitalization --- ## OpenHarmony-based RK3568 Commercial Display Board Solution - URL: https://intl.sienovo.cn/blog/128091342 - Date: 2022-11-29 - Tags: #harmonyos, #Huawei ### Introduction RK3568 Commercial Display Board Featuring OpenHarmony OS 3.1 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128091342/01_6d88b388.png) > The XM-RK3568 chip integrates a quad-core Cortex-A55 CPU, Mali-G610 GPU, and 0.8 TOPS NPU capabilities. Due to its rich interfaces and the high cost-effectiveness of the board solution, RK3568 is widely used in commercial display products across various industries. Currently, RK3568 board solutions have been applied in commercial all-in-one machines in sectors such as medical, property/campus management, finance, and government. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128091342/02_5d3b0310cb7f8c99a458467bfbde66e3.png) > The Xinmai XM-RK3568 commercial display board solution provides more hardware interfaces for connecting peripherals from various industries. It supports display interfaces such as VBY1, HDMI, and eDP, with a maximum 4K*2K video output. It also supports SATA data storage interfac --- ## RK3568 + HarmonyOS Teaching and Experiment Platform: HarmonyOS Certified Design Solution - URL: https://intl.sienovo.cn/blog/127619112 - Date: 2022-11-29 - Tags: #harmonyos, #Huawei, #HarmonyOSTeachingPlatform RK3568/3288/3399 + HarmonyOS is widely used in Information Technology Application Innovation (Xinchuang) industries such as industrial tablets and military-grade medical equipment, supporting software and hardware customization! It not only features a domestically developed operating system and stylish design but also offers rich interfaces and powerful core functions, complemented by a 10.1-inch LCD display. Application scenarios include: smart manufacturing, smart finance, smart transportation, self-service terminals, and more. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127619112/01_d1bd5e1ccbe4f900ba9e8dc75250042d.png) The XM3568A motherboard adopts the Rockchip RK3568 quad-core 64-bit Cortex-A55 processor, with a main frequency up to 2.0GHz, offering significantly improved performance. It utilizes advanced 22nm process technology, characterized by low power consumption and high performance. It features a dual-core architecture GPU, high-performance VPU, and N --- ## Ultra-Low Latency 4K Customizable Professional Vision Computing Platform - URL: https://intl.sienovo.cn/blog/128084833 - Date: 2022-11-28 - Tags: #FPGADev, #FPGAImageProcessing Industrial machine vision systems live and die by latency. A camera pipeline that introduces even a few milliseconds of delay can invalidate real-time defect detection, throw off robotic pick-and-place timing, or degrade surgical imaging feedback loops. This post walks through Sienovo's ultra-low latency 4K professional vision computing platform — a tightly integrated hardware and software solution built around the Xilinx Zynq UltraScale+ MPSoC — and explains why its architectural choices matter for demanding industrial, medical, and IoT imaging applications. ## Platform Foundation: Zynq UltraScale+ MPSoC At the heart of the platform sits the Xilinx Zynq UltraScale+ MPSoC, a heterogeneous SoC that pairs a quad-core ARM Cortex-A53 application processor and dual-core ARM Cortex-R5 real-time processor with a substantial UltraScale+ FPGA fabric. This ARM + FPGA fusion architecture is what makes sub-millisecond ISP latency achievable: instead of routing raw sensor data through a CPU pipel --- ## FPGA+MPU+MCU-Based Fully Automatic Blood Cell Analyzer Solution - URL: https://intl.sienovo.cn/blog/128084775 - Date: 2022-11-28 - Tags: #FPGADev, #MCU, #EmbeddedHardware The fully automatic blood cell analyzer is one of the most widely used instruments in clinical laboratories at hospitals, employed for testing parameters such as red blood cells, hemoglobin, white blood cells, and platelets. As a fully automated intelligent device based on electronic and automation technologies, it offers comprehensive functionality and simple operation. With support from computer systems, it excels in data processing and analysis, enabling reliable multi-parameter analysis simultaneously. Through network connectivity and interactive touchscreens, it supports online information sharing and is extensively used in hospital clinical testing. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/128084775/01_adab4473bf17ee3484156cf7117c9d5a.png) The hardware system of a fully automatic blood cell analyzer consists of three main lines. First is the data line, centered on an FPGA processor, primarily responsible for high-speed acquisition and collection of raw d --- ## PROFINET to EtherCAT Gateway Solution Design - URL: https://intl.sienovo.cn/blog/127985044 - Date: 2022-11-22 - Tags: #profinet, #ethercat, #Gateway 1 Summary PLC controllers and remote I/O are increasingly communicating in current production environments. In some sites, controllers and remote I/O stations use a unified communication protocol, while in others, remote I/O stations may use different protocols, primarily due to product limitations from various manufacturers. 1.1 Solution In a certain site in Henan, the controller uses a Siemens S7-1500 series PLC, and the modules for the remote I/O stations are all from Inovance AM600 medium-sized series PLCs. All I/O modules are connected to an AM600-RTU-ECAT coupler. The Inovance coupler module supports the EtherCAT protocol when operating normally, functioning as an EtherCAT slave. The monitoring system, a Siemens S7-1500 series PLC, supports the PROFINET protocol. The protocol inconsistency prevents direct communication for data exchange. A third-party protocol conversion module is required to enable data exchange between different protocols. In this case, our self-developed Ethe --- ## Elevator IoT Gateway Hardware-Software Integrated Solution - URL: https://intl.sienovo.cn/blog/127984822 - Date: 2022-11-22 - Tags: #IoT The Elevator IoT Monitoring Platform, based on edge computing intelligent monitoring equipment, provides 24/7, fully automatic monitoring of elevator operations. By collecting real-time elevator operational sensor data, it establishes key data standards for operational status. Utilizing AI machine learning algorithms and big data analysis, it provides real-time alerts for elevator faults, trapped persons, and other incidents, supporting assisted rescue operations. The proprietary "Elevator Cluster Situational Awareness Algorithm (ECSA)" offers scientific support for "on-demand maintenance" and operational health management of elevators. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127984822/01_1d39ae0cb68d06bb0c8032b7625d67b8.png) IoT Gateway Design: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127984822/02_7bfadbe592e71ad391d746999ba839af.png) Features: Independent Industrial-Grade Design: Independently researched and designed in accordance with n --- ## Smart Terminal Testing Solution - URL: https://intl.sienovo.cn/blog/127976417 - Date: 2022-11-22 - Tags: #5G Overview With the rapid development of the Internet+ industry and the rise of smart terminals, mobile device manufacturers, mobile communication operators, and mobile internet content providers alike are facing a landscape of continuously emerging new technologies, new businesses, and new services, coupled with an accelerating commercialization process. Currently, mobile transmission networks based on 5G core technologies have been developed. In the future, supported devices will include not only smartphones but also smartwatches, fitness trackers, smart projectors, smart home devices, and more. The smart terminal industry chain is undergoing a period of rapid development. Communication standards are constantly being updated and revised, smartphone functionalities are continuously innovating, and various communication protocol certifications are becoming increasingly complex and cumbersome. Device manufacturers, mobile communication operators, mobile internet content providers, and --- ## Intelligent Service Robot Products and Solutions - URL: https://intl.sienovo.cn/blog/127976344 - Date: 2022-11-22 - Tags: #Robotics, #AI Product Overview With the continuous development and evolution of Artificial Intelligence (AI) technology, AI-oriented domain applications are increasingly gaining attention from more enterprises. Xinmai, as a leading innovative software and information technology service provider in China, has always been committed to the exploration and practice of AI domain technologies. Leveraging its strong technical capabilities, Xinmai has developed an AI product called "Intelligent Service Robot". This product is based on big data technology, completing the evolution and upgrade of its technical system from the "pre-AI era (search + keywords/templates)" to the "post-AI era (search + Natural Language Processing NLP + Deep Learning + Reinforcement Learning)". ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127976344/01_c7613f3ef64ab370124f14d20372542e.png) By means of a "human-machine collaborative self-learning mechanism" and "integration (search + deep learning)", service robo --- ## Hardware & OS Testing Solutions - URL: https://intl.sienovo.cn/blog/127976308 - Date: 2022-11-22 - Tags: #Server, #DevOps, #CloudComputing ### Hardware & OS Testing Solutions Solution Overview Server Hardware, OS Compatibility, and Certification Testing The core technology for all data center and cloud computing services is scalability, built upon the foundation of large-scale distributed server deployments. However, the current market features a vast array of server types and a multitude of corresponding operating systems. This places extremely high demands on the compatibility between various servers and operating systems. Ensuring good compatibility and long-term operational stability between underlying hardware products and their supporting operating systems, coupled with continuous investment in hardware compatibility testing and certification to enrich the support list for components and software, is essential to ensure that the data center or cloud computing services provided to customers gain an advantage in fierce market competition, enhancing user satisfaction and competitiveness. Server Hardware and Chip P --- ## Motion Control, Machine Vision, Intelligent Manufacturing Host System Customized Solution - URL: https://intl.sienovo.cn/blog/127859438 - Date: 2022-11-15 - Tags: #Manufacturing Industrial production lines increasingly rely on automated optical inspection (AOI) to catch defects that the human eye misses at line speed. This post examines the AIISG fanless vision inspection system — an Advantech platform designed specifically for machine-vision workloads in manufacturing environments — covering its hardware architecture, key interface specifications, and the industrial applications it is built to serve. ## What Is the AIISG Vision Inspection System? The AIISG series is a purpose-built system solution for AOI applications. Rather than adapting a general-purpose industrial PC, Advantech engineered the AIISG around the specific demands of machine vision: deterministic camera synchronization, high-bandwidth image acquisition, and reliable 24/7 operation in factory environments that range from cold storage to hot shop floors. The platform is powered by an **Intel 6th Generation (Skylake) Core™ i7 or i5 processor in BGA1440 package**, a soldered-down design that el --- ## 24G Security Radar - Radar-Vision Integrated System - Traffic Flow Radar - Speed and Distance Measurement - 77G Millimeter-Wave Radar - URL: https://intl.sienovo.cn/blog/127596046 - Date: 2022-10-30 - Tags: #24GHzSecurityRadar, #mmWaveRadar ## ******1 Overview****** The XD-100 Security Radar, developed by Shenzhen Xinmai, is a 24G band, 100-meter miniature multi-purpose radar for ranging, speed measurement, and angle monitoring. Its primary design purpose is to monitor personnel moving on the ground for ground status monitoring applications. The XD-100 Security Radar adopts an FMCW (Frequency Modulated Continuous Wave) operating principle, featuring a small size, light weight, high reliability, and no distance blind spots. The XD-100 Security Radar has no internal mechanical moving parts and can simultaneously detect the distance, speed, angle, and target echo power of moving targets, including personnel and vehicles. Operating in the 24G band, the XD-100 Security Radar can penetrate adverse weather conditions like rain and fog, enabling 24/7 all-weather operation. The radar uses low transmit power, posing no impact on personnel safety. The XD-100 Security Radar is primarily used for perimeter protection, airport secur --- ## ZYNQ RFSoC Development Board - USRP Software Defined Radio X410mini Development Board - 5G Evaluation Board - URL: https://intl.sienovo.cn/blog/127595870 - Date: 2022-10-30 - Tags: #5GEvaluationBoard, #SDR RFSoC Development Board - USRP Software Defined Radio X410mini Development Board - 5G Evaluation Board The Zynq® UltraScale+™ RFSoC ZCU208 Evaluation Kit is an ideal RF test platform for out-of-the-box evaluation and cutting-edge application development. The kit includes the UltraScale+ RFSoC ZU48DR, which integrates eight 14-bit 5GSPS ADCs, eight 14-bit 10GSPS DACs, and eight Soft-Decision Forward Error Correction (SD-FEC) cores, designed for rapid bring-up of RF-class applications. ### Product Description The Zynq® UltraScale+™ RFSoC ZCU208 Evaluation Kit is an ideal RF test platform for out-of-the-box evaluation and cutting-edge application development. The kit includes the Zynq UltraScale+ RFSoC ZU48DR, which integrates eight 14-bit 5GSPS ADCs, eight 14-bit 10GSPS\* DACs, and eight Soft-Decision Forward Error Correction (SD-FEC) cores, designed for rapid bring-up of RF-class applications. By perfectly combining Arm® Cortex®-A53 and Cortex-R5 subsystems, programmable logic, and --- ## Array Camera - Light Field Camera - AI Binocular Thermal Camera - Infrared AI Recognition Camera - URL: https://intl.sienovo.cn/blog/127583463 - Date: 2022-10-29 - Tags: #AI, #CameraArray ## Understanding Array Cameras: A New Era in Imaging Technology Array cameras, also known as light field cameras, AI binocular thermal cameras, and infrared AI recognition cameras, are a type of imaging technology that uses multiple small lenses to achieve the imaging effect of a large lens. This principle is similar to that of array telescopes and insect compound eyes. In this article, we will explore the benefits and features of array cameras, and what makes them an attractive option for various applications. ### Benefits of Array Cameras Array cameras have several advantages over traditional cameras. Firstly, they have a wider field of view, which allows them to capture more information and detail in a single image. This is particularly useful in applications such as surveillance, where a wider field of view can help to detect and track objects more effectively. Secondly, array cameras produce larger images, which can be beneficial in applications such as medical imaging, where h --- ## Helicopter FPGA Multi-channel Video Capture, OSD Character Overlay, and Fusion Board Design with VGA-HDMI-DVI-SDI Capture - URL: https://intl.sienovo.cn/blog/127583358 - Date: 2022-10-29 - Tags: #FPGADev, #VideoFusion Video fusion technology is a branch of virtual reality technology, and can also be considered a development stage of virtual reality. Video fusion technology refers to fusing one or more image sequence videos of a certain scene or model, captured by video capture devices, with a related virtual scene, to generate a new virtual scene or model of this scene. Shenzhen Xinmai has launched an FPGA-based hardware real-time video overlay and fusion development board, which provides multi-channel video capture, overlay, and fusion capabilities. Video sources include VGA, PAL LVDS, HDMI, SDI, 4K, and other high-definition videos. It offers powerful video capture and fusion capabilities. In the video surveillance systems of armed helicopters, there is a requirement not only to display the status of reconnaissance targets in real-time but also to simultaneously show information such as the helicopter's speed, position, altitude, and engine status during its current flight. This necessitates the --- ## Custom Virtex-4 CameraLink Development Board with PCI Image Acquisition Card, FPGA-HDMI Encoding, and LVDS Camera Support - URL: https://intl.sienovo.cn/blog/127583207 - Date: 2022-10-29 - Tags: #FPGADev, #cameralink, #FPGACamera This custom Virtex-4 CameraLink development board is designed for industrial machine-vision and image-acquisition applications where high-speed camera data must be captured, buffered, and forwarded to a host processor — ARM or DSP — for real-time analysis. The board bridges the CameraLink physical layer to a standard FPC ribbon cable, making it straightforward to drop into existing embedded-vision pipelines without redesigning the camera front-end. ## FPGA: Xilinx Virtex-4 The board's logic fabric is built around a Xilinx Virtex-4 device. Virtex-4 parts include dedicated RocketIO serial transceivers and large block-RAM resources that suit them well for data-path applications: deserializing the high-speed LVDS streams from a CameraLink camera, packing pixels into frames, and writing burst transfers to the onboard SRAM. The Virtex-4 family also offers dedicated DSP48 slices, which can be used for in-FPGA preprocessing (histogram, colour conversion, simple filtering) before the data lea --- ## Design and Testing of a Ground Surveillance Radar System - URL: https://intl.sienovo.cn/blog/127579719 - Date: 2022-10-28 - Tags: #GroundSurveillanceRadar This article primarily introduces the composition and design of a ground surveillance radar system. ## ******I. Functions and Performance Indicators****** The XD-5000 ground surveillance radar is a small, one-dimensional phased array radar suitable for scenarios such as border surveillance, oil pipeline protection, and portable battlefield reconnaissance for individual soldiers. This radar features the following characteristics: Wide Surveillance Range: Detection range for pedestrians ≥ 5 km, for vehicles ≥ 10 km, and azimuth coverage of 90°. Strong Environmental Adaptability: The radar features online learning capabilities, allowing it to adapt to various environmental changes. Low Minimum Detectable Speed: Capable of detecting targets moving as slow as 0.3 m/s. High Detection Accuracy: Range accuracy < 5 m, azimuth accuracy < 0.5°. High Automation Level: Utilizes advanced TBD (Track Before Detect) algorithms, performing detection and tracking simultaneously, eliminating the ne --- ## UAV Detection Radar Software and Hardware Solution - URL: https://intl.sienovo.cn/blog/127579519 - Date: 2022-10-28 - Tags: #UAV, #Radar Features - Lightweight, compact radar - Detects moving vehicles and personnel - Low Probability of Intercept (LPI) waveform design - 24/7 day/night operation Applications - Critical infrastructure security - Airport security facilities - Airport and secure area protection - Oil depot protection - Border surveillance - Perimeter surveillance - Integration with existing security video systems ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127579519/01_09b574fd1f30b8766b524f5bf6937395.png) The UAV detection radar is a fully coherent continuous wave (CW) radar system, used to detect, monitor, track, and measure low-altitude or ground-based moving targets. These moving targets can include people, vehicles, low-flying aircraft, drones, etc. The motion information of these targets is transmitted to the monitoring center in a specified format to provide real-time relevant information about moving targets within the monitored area. The data interface supports communication w --- ## Three-Coordinate Low-Altitude Target Early Warning and Detection Radar Solution - URL: https://intl.sienovo.cn/blog/127579452 - Date: 2022-10-28 - Tags: #RadarDSPFPGA, #RadarSoftware The three-coordinate low-altitude target tracking radar is an all-day, all-weather, high-resolution, high-precision, and low-cost three-coordinate surveillance radar developed to meet the detection and tracking needs of low-altitude targets such as UAVs, paragliders, and hot air balloons in complex background environments. This radar employs a composite pulse Doppler system, utilizing technologies such as solid-state transmission, integrated front-end, MTD, MTI, software display and control, Ethernet communication, and a fully sealed structure. It can achieve accurate detection, precise positioning, and timely early warning for multi-attribute targets. Its technical and functional features include advanced technology, high reliability, strong operability, low false alarm rate, diverse installation platforms, and wide deployment areas. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127579452/01_536bc831754f9f0a5ddbcc78785cc5bf.png) ****Features:**** 1. ****All-day, a --- ## C6678+K7+AD9253/AD9783 8-Channel AD High-Speed Signal Processing Board - URL: https://intl.sienovo.cn/blog/127569249 - Date: 2022-10-28 - Tags: #C6678+K7+AD ## Overview The C6678+K7+AD9253/AD9783 8-channel signal processing board is a compact, high-density embedded computing module designed for demanding analog signal acquisition and real-time digital processing tasks. Combining a Texas Instruments TMS320C6678 multi-core DSP with a Xilinx Kintex-7 FPGA and a pair of high-speed ADCs, the board targets applications such as radar front-ends, software-defined radio (SDR), sonar, electronic warfare, and industrial non-destructive testing — anywhere that requires simultaneous multi-channel analog capture paired with heavy arithmetic throughput, all within a tight SWaP (Size, Weight, and Power) envelope. At just 105 mm × 180 mm and under 150 g, the module runs entirely from a single 5 V rail and draws no more than 35 W under full load. All active components are sourced from industrial-grade import channels, making the design suitable for extended temperature ranges and long-lifecycle deployments. --- ## Analog Front-End: Dual AD9253 ADCs (8 C --- ## C6678/C6657+ZYNQ/K7/A7 FPGA+AD+Beidou Hardware and Software Design Solution - URL: https://intl.sienovo.cn/blog/127565140 - Date: 2022-10-28 - Tags: #C6678, #ZYNQ Addressing the current issue of low positioning accuracy in Beidou navigation and positioning receivers under high dynamic and complex electromagnetic environments, this paper, based on an understanding of satellite navigation principles, introduces the design of an embedded Beidou navigation receiver based on DSP+FPGA, to meet the high-precision navigation and positioning requirements for UAVs, individual soldiers, robots, and other applications in high dynamic and complex electromagnetic environments. Compared to the TMS320C6678 + Kintex-7 combination, the TMS320C6678 + ZYNQ combination offers more hardware resources, most notably the addition of two ARM Cortex-A9 cores, and features native [Ethernet](http://www.elecfans.com/tags/ethernet/ "Ethernet"), [USB](http://www.hqchip.com/app/576 "USB"), [UART](http://www.elecfans.com/tags/uart/ "UART"), [CAN](http://www.elecfans.com/tags/can/ "CAN"), S[PI](http://www.elecfans.com/tags/pi/ "PI"), [I2C](http://www.elecfans.com/tags/i2c/ "I2C --- ## Domestic ARM+FPGA+AD Low-Cost High-Performance Data Acquisition Card Solution - URL: https://intl.sienovo.cn/blog/127521138 - Date: 2022-10-25 - Tags: #FPGADev **Foreword** In recent years, with the continuous advancement of China's New Infrastructure and Made in China 2025 initiatives, single ARM processors are increasingly struggling to meet the functional requirements of industrial applications. Industries such as energy and power, industrial control, and smart healthcare often require processor platforms with an ARM+FPGA architecture to implement specific functions, such as multi-channel/high-speed AD acquisition, multiple Ethernet ports, multiple serial ports, multi-channel/high-speed parallel DI/DO, and high-speed data parallel processing. So, let's first look at the advantages of the ARM+FPGA architecture. **ARM:** Rich interface resources, low power consumption, excels in multimedia display, logic control, etc. **FPGA:** Excels in multi-channel or high-speed AD acquisition, interface expansion, high-speed signal transmission, high-speed data parallel processing, etc. Therefore, the ARM+FPGA architecture offers comprehensive comp --- ## Surgical Robot Hardware and Software Design Solution - URL: https://intl.sienovo.cn/blog/127518880 - Date: 2022-10-25 - Tags: #EmbeddedHardware, #SurgicalRobot Embedded Master Manipulator Handle Requirements Structure: 1. The following structure is a control handle used to collect human hand motion signals, transmit them to the host computer, and remotely control other equipment. 12. The master manipulator arm within the handle contains 4 motor rotary joints, with a built-in 16-bit resolution rotary encoder to record angular displacement; 23. The host computer connects to the master manipulator handle motors, slave instrument motors (actuators controlled by the handle's motion output), stand motors (for linear motion controlled by the handle), and the electrosurgical unit (for on/off control implemented by the handle). ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127518880/01_3d99d1ef03d100b80750c9bac8709164.png) Functional Modules: Forward Control (Handle as Controller): Control the master manipulator handle's output rotary encoder (5) angular displacement signal to control the slave instrument motors; Handle buttons: --- ## NXP i.MX8-based EtherCAT Real-time Motion Controller Design: Linux+Xenomai+IGH+RTnet - URL: https://intl.sienovo.cn/blog/127398232 - Date: 2022-10-18 - Tags: #Ethercat, #RealTime, #igh, #CostEffective Hardware Platform: i.MX8 Software Architecture: Linux + Xenomai + IGH + RTnet ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127398232/05_af063166dc458e4a921cff17a27c1879.png) Designed based on the NXP i.MX8 processor, featuring a quad-core ARM-A53 with a clock speed of up to 1.3GHz, onboard 2GB RAM, and 8GB ROM. It operates within an ambient temperature range of -40℃ to 85℃, meeting the requirements for industrial and general industrial applications. The i.MX8M processor features industry-leading audio, voice, and video processing capabilities, offering full 4K UltraHD resolution and HDR (Dolby Vision, HDR10, and HLG), and providing the highest level of professional audio fidelity. It is suitable for fanless operation, with low-cost thermal systems and long battery life. It boasts the latest high-speed interfaces for flexible connectivity and offers a 10-15 year long-term product supply program. **·Dual Independent Display Outputs** MIPI-DSI (1080p) and HDMI 2.0a (4K --- ## 国产EDA与FPGA芯片验证方案 - URL: https://intl.sienovo.cn/blog/127394072 - Date: 2022-10-18 - Tags: #DomesticEDA, #FPGA #### Key Technologies Restricting FPGA Development - EDA FPGAs, hailed as "universal chips," have been increasingly gaining attention in the domestic market in recent years. However, their high technical barrier is almost unparalleled in the chip industry. Among the many factors restricting FPGA development, the most critical one is EDA software tools. Indispensable! Developing FPGAs Requires a Dual Focus on Both Hardware and Software FPGA, short for Field Programmable Array, is a programmable semiconductor device composed of a matrix of configurable logic blocks (CLBs) connected by programmable interconnects. FPGAs require accompanying software to burn user designs onto the chip to achieve the desired functionality. Currently, the chip market primarily consists of four major types: CPUs, GPUs, FPGAs, and ASICs. Compared to other mainstream chips, FPGAs offer higher flexibility than application-specific integrated circuits (ASICs). Their performance and real-time processing capabi --- ## RK3588 + AI Industrial Vision Inspection Design Solution - URL: https://intl.sienovo.cn/blog/127344769 - Date: 2022-10-16 - Tags: #AI This article provides a detailed introduction to the form factor, dimensions, and technical specifications of the AI edge computing motherboard based on the Rockchip RK3588 chip, as well as detailed hardware interface design reference instructions. This enables customers to quickly apply the RK3588 edge computing motherboard to smart terminal devices in AI fields such as industrial internet, smart cities, smart security, smart transportation, and smart healthcare. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127344769/01_f05d925178993e1dbcb9c70f20cc280a.png) Product Overview Xinmai has launched an AI edge computing motherboard based on the Rockchip RK3588 architecture. The RK3588 is a new generation domestic flagship high-performance 64-bit octa-core processor, manufactured using an 8nm process, featuring high computing power, low power consumption, powerful multimedia capabilities, and rich data interfaces. It is equipped with an octa-core CPU (quad-core A76 + quad- --- ## RK3588 + AI Video Structuring Algorithm Design Solution - URL: https://intl.sienovo.cn/blog/127327103 - Date: 2022-10-14 - Tags: #AI, #MachineLearning, #DeepLearning This article provides a detailed introduction to the form factor, dimensions, and technical specifications of the AI edge computing motherboard based on the Rockchip RK3588 chip, as well as detailed hardware interface design reference instructions. This enables customers to quickly apply the RK3588 edge computing motherboard in intelligent terminal devices across AI fields such as industrial internet, smart cities, smart security, smart transportation, and smart healthcare. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127327103/01_f05d925178993e1dbcb9c70f20cc280a.png) Product Overview Xinmai introduces an AI edge computing motherboard based on the Rockchip RK3588 architecture. The RK3588 is a new generation domestic flagship high-performance 64-bit octa-core processor, manufactured with an 8nm process, featuring high computing power, low power consumption, powerful multimedia capabilities, and rich data interfaces. It is equipped with an octa-core CPU (quad-core A76 --- ## AI Security Detection Solution Based on RK1126 with Support for Custom AI Algorithm Development - URL: https://intl.sienovo.cn/blog/127326942 - Date: 2022-10-14 - Tags: #RK1126, #AI, #SmartSecurity The AI BOX is a high-performance, low-power edge computing device based on the RK1126 platform, delivering 2 TOPS of computing power. The RK1126 supports 4K H.264/H.265 decoding and 1080p@60fps H.264/H.265 encoding, with HDMI video output supporting up to 4K@30fps. With a lightweight and flexible design, it is widely applicable in fields such as new retail, intelligent security, smart classrooms, and gaming consoles. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127326942/01_c06a3d32855ff05e341043e82d648c99.png) Algorithms can be customized and ported according to customer requirements: Supported functions include fall detection, climbing recognition, fight detection, absence from post detection, sleeping on duty detection, flame detection, smoke detection, fire lane obstruction detection, virtual fence (electronic perimeter), garbage overflow detection, and people counting. Main Specifications: The RV1126 HCoreV1.1 core board features Rockchip's RV1126 main chip, --- ## RK3588 AI Edge Computing Smart Transportation Intelligent Security Industrial Motherboard Design Solution - URL: https://intl.sienovo.cn/blog/127289327 - Date: 2022-10-14 - Tags: #AI, #IoT, #RK3588 This article provides a detailed introduction to the form factor, dimensions, technical specifications, and detailed hardware interface design reference for the AI edge computing motherboard based on the Rockchip RK3588 chip. This enables customers to quickly apply the RK3588 edge computing motherboard to intelligent terminal devices in AI fields such as industrial internet, smart cities, smart security, smart transportation, and smart healthcare. 1. ******Product Overview****** Xinmai has launched an AI edge computing motherboard based on the Rockchip RK3588 architecture. The RK3588 is a new generation domestic flagship high-performance 64-bit octa-core processor, built on an 8nm process. It features high computing power, low power consumption, powerful multimedia capabilities, and rich data interfaces. It is equipped with an octa-core CPU (quad-core A76 + quad-core A55) and an ARM G610MP4 GPU, with a built-in NPU offering 6 TOPs of computing power. It supports 8K@60fps video deco --- ## SI+PI Co-Simulation Analysis of DDR3/DDR4 for Domestic DSP+ARM+FPGA Chips - URL: https://intl.sienovo.cn/blog/127269099 - Date: 2022-10-11 - Tags: #Simulation ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127269099/01_1d7ff7c48a8fc3f3770c906bafd0feaa.gif) #### Simulation for Domestic DSP + ARM + FPGA Chips #### Simulation Targets: DDR2/3/4/5, LPDDR2/3/4/5, etc. ● SI/PI co-simulation, batch simulation ● Participation in industry standards development for DDR3/4/5 design ● Simulation vs. test correlation to improve simulation accuracy ● Extensive DDR3/4/5 product debug experience ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127269099/02_2b3e1ac6b7e8098f43a7fb067c3507d0.gif) #### Signal Quality Simulation \- Comparison of results before and after simulation optimization #### Timing Simulation Analysis \- Timing relationship across signal groups \- Timing window calculation (setup/hold time margin) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127269099/03_7c9f77e6d884987c5afbe7d29a3c9846.gif) #### Simulation Challenges High routing density, large number of components, high operat --- ## Cost-Effective Algorithm Acceleration Platform for Lattice FPGA + PCIe + x86 Servers - URL: https://intl.sienovo.cn/blog/127268965 - Date: 2022-10-11 - Tags: #lattice, #pcie, #AlgorithmAcceleration Edge-AI workloads and industrial computing tasks increasingly demand hardware acceleration that balances cost, flexibility, and deployment simplicity. This post introduces a platform built around the Lattice ECP5 FPGA paired with a PCIe Gen 3.0 interface, designed to drop into standard x86 server infrastructure and accelerate custom algorithms under Ubuntu or Windows — without the licensing overhead and power draw of larger, higher-cost FPGAs. ## Why Lattice ECP5 for Algorithm Acceleration? Lattice Semiconductor's ECP5 family occupies a practical middle ground in the FPGA market. Unlike high-end devices from Intel (Altera) or AMD (Xilinx), the ECP5 is optimized for low-power, cost-sensitive applications while still offering a meaningful complement of logic cells, DSP slices, and high-speed SERDES transceivers. For algorithm acceleration tasks — image preprocessing, protocol offload, signal processing pipelines, or inference on lightweight models — the ECP5 provides enough fabric to b --- ## Loongson + Fudan Micro FPGA Fully Domestic VPX High-Speed Data Acquisition Card Solution - URL: https://intl.sienovo.cn/blog/127126276 - Date: 2022-10-10 - Tags: none ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/127126276/01_96063ff9f09ba5f67be3a851a865f018.png) Domestic production is a major trend nowadays. **Solution Features** ① Utilizes high-performance Loongson 3A4000 processor, operating at 1.8GHz-2.0GHz, compatible with Loongson 3A5000 processor, operating at 2.3GHz-2.5GHz ② Equipped with Loongson's self-developed 7A1000 bridge chip, offering rich interfaces to meet I/O application requirements in desktop and server fields ③ Integrated FPGA-V7 coprocessor, supporting high-speed buses like SRIO and LVDS, enabling high-speed data transmission and real-time processing ④ Onboard solid-state chip storage, with fast read/write speeds ⑤ Achieves 100% indigenous production ⑥ Can be widely applied in national defense and military, cybersecurity, railway & rail transit, nuclear power & electricity, industrial measurement and control, medical, and other fields ⑦ Board standard: VPX-6U ⑧ Highly customizable platform ![](https: --- ## Image Recognition Hardware Design and Algorithm Implementation Based on Domestic Galaxy Phytium Multi-core DSP + FPGA - URL: https://intl.sienovo.cn/blog/126966000 - Date: 2022-09-21 - Tags: #FPGADev, #DomesticDSP, #PhytiumDSP With the development of surveillance satellites, how to quickly identify targets in satellite images has become a key technology. To achieve the localization of key on-board components and provide higher performance and better real-time capabilities for the entire system, this project will use the high-performance multi-core DSP chip independently developed by the College of Computer Science, National University of Defense Technology, as the processing core, supplemented by an FPGA, to build an image acquisition and recognition hardware processing platform, and research and implement ship target recognition algorithms on this platform. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126966000/01_e7cfac685b2583a5fd3238df59c0f739.png) Main work: ① Design a processing framework based on Phytium multi-core DSP+FPGA. This framework fully utilizes the DSP's ability to process digital signals and the FPGA's ability to control interfaces. It features a flexible structure and me --- ## ARM+FPGA Medical Image Processing Solution - URL: https://intl.sienovo.cn/blog/126963671 - Date: 2022-09-20 - Tags: #arm, #FPGADev, #ImageProcessing The rapid development of image processing technology has led to increasingly widespread application of image acquisition and processing systems in enhancing the automation level of agricultural production. Current image acquisition systems are sometimes based on CCD cameras, image acquisition cards, and computers; others are based on CCD cameras, decoders, [FPGA](https://www.elecfans.com/tags/fpga/ "FPGA"), and [DSP](https://www.elecfans.com/tags/dsp/ "DSP"); and some are based on CMOS [image sensor](https://www.elecfans.com/tags/%E5%9B%BE%E5%83%8F%E4%BC%A0%E6%84%9F%E5%99%A8/ "图像传感器") chips, FPGA, and DSP. Each of these approaches has its own advantages and disadvantages in terms of real-time performance, flexibility, and maintainability. In agricultural production, systems based on CCD cameras, image acquisition cards, and [computers](https://www.hqchip.com/app/873 "计算机") are more common. This paper, considering the needs for front-end image processing and image data transmission in --- ## Design of an Intelligent Human-Machine Interaction System Based on Domestic ARM + FPGA + Codesys Motion Control Platform - URL: https://intl.sienovo.cn/blog/126958976 - Date: 2022-09-20 - Tags: #FPGADev Abstract: To meet the requirements of display systems for intelligent protection devices in the field of relay protection, a design scheme for an intelligent human-machine interaction system based on domestic ARM processors and FPGAs is proposed. This scheme focuses on elaborating the functional architecture and hardware design of the intelligent human-machine interaction system, and introduces the software design process for data exchange and human-machine interaction. Experimental results show that the scheme has a simple hardware structure, its system materials are independently controllable, and the system is safe and stable, capable of meeting the functional requirements of intelligent protection devices in power systems. **0 Introduction** With the large-scale promotion and application of third-generation intelligent substations, intelligent protection devices, characterized by information digitalization and platform networking, are gradually playing an increasingly important --- ## RK3399pro + K7/A7 FPGA + AI Domestic Artificial Intelligence Image Processing Platform - URL: https://intl.sienovo.cn/blog/126958767 - Date: 2022-09-20 - Tags: #AI, #RK3399PRO, #K7 The RK3399Pro is a Rockchip SoC that shipped with an integrated Neural Processing Unit (NPU) at a time when on-device AI inference for embedded Linux was still a niche capability. This post covers a hands-on benchmark of the RK3399Pro NPU using Rockchip's own toolkit, compares it to the Jetson Nano, and notes the real-world caveats you'll run into when porting existing detection networks to the platform. ## What Is the RK3399Pro? The RK3399Pro is built on the same dual Cortex-A72 + quad Cortex-A53 big.LITTLE cluster as the standard RK3399, but adds a dedicated NPU die. Rockchip initially quoted the NPU at **2.4 TOPS** in pre-release materials. Post-launch measurements by the community put the actual sustained throughput closer to **3.0 TOPS** — a meaningful over-delivery that made the chip significantly more competitive than early datasheets suggested. For context, the NVIDIA Jetson Nano delivers **0.47 TFLOPS** of FP16 compute via its 128-core Maxwell GPU. The two figures use diffe --- ## Metal Hardmask Physical Vapor Deposition System - URL: https://intl.sienovo.cn/blog/126946495 - Date: 2022-09-20 - Tags: #DSP+FPGA, #ETHERCAT, #SemiconductorEquipment, #Controller Hardmask technology involves using selected images, patterns, or objects to mask all or part of the image being processed, thereby controlling the area or process of image treatment. It is widely used in both Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) processes in IC manufacturing. As the IC industry advanced to process nodes below 32nm, the use of Ultra Low-k (ULK) dielectric materials (k<2.5) became necessary to address parasitic capacitance effects caused by increasingly close metal interconnects. To overcome the weaknesses of Ultra Low-K dielectric materials, such as low mechanical strength and poor corrosion resistance, Metal Hardmask process technology emerged. The exiTin H630 TiN Metal Hardmask Physical Vapor Deposition (PVD) system, independently designed and manufactured by Naura Microelectronics, is specifically developed for 55-28nm process nodes and 12-inch metal hardmask applications. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126946495/01_fec --- ## Physical Vapor Deposition Semiconductor Equipment PVD DSP/ARM+FPGA Controller Design - URL: https://intl.sienovo.cn/blog/126946420 - Date: 2022-09-20 - Tags: #arm, #FPGADev, #EmbeddedHardware Magnetron sputtering technology is a type of PVD (Physical Vapor Deposition) technology and one of the important methods for preparing thin film materials. It utilizes the characteristic that charged particles gain kinetic energy after being accelerated in an electric field, directing ions towards a target electrode (cathode) made of the material to be sputtered. This process sputters target atoms, causing them to move in a specific direction towards a substrate and deposit as a film on the substrate. Magnetron sputtering equipment allows for controllable film thickness and uniformity, producing films with good density, strong adhesion, and high purity. This technology has become an important means for preparing various functional thin films. Naura Akrion has made breakthroughs in several key technologies, including sputtering source design, plasma generation and control, particle control, chamber design and simulation, and software control. This has established core technological adv --- ## Solar Controllers in IoT and AI Systems - Integrated Storage and Control Unit (2) - URL: https://intl.sienovo.cn/blog/126862405 - Date: 2022-09-14 - Tags: #Solar, #IntegratedEnergyStorage, #IoT Featuring WEB-based RTMP live streaming and WeChat sharing for applications in agriculture, routing, IoT, and more. Various extensions based on MODBUS DTU functionality, including superimposed functions for sensors such as soil temperature and humidity, air temperature and humidity, carbon dioxide, and illuminance. With integrated 4G, GPS, and router functionalities, it serves multiple purposes, significantly reducing costs. We can establish independent operating systems for clients and offer in-depth collaboration for various project customizations. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126862405/01_3626ddd5eaa81133a3e5fa0e21e4abbf.png)Solar Lithium Battery Storage and Control System Highly integrated, lightweight, and flexibly configurable, it adapts to harsh environments and climates, enabling fast, efficient, and convenient deployment for smart IoT. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126862405/02_2f3fb020196daf78c7ffd8b04020cbea. --- ## 8-inch Aluminum Metal Etching Semiconductor Equipment DSP/ARM+FPGA Motion Controller - URL: https://intl.sienovo.cn/blog/126850252 - Date: 2022-09-14 - Tags: #FPGADev, #arm, #EmbeddedHardware The 8-inch aluminum metal etching semiconductor equipment DSP/ARM+FPGA motion controller supports customization. The NMC508M 8-inch aluminum metal etcher is an inductively coupled high-density plasma dry etching system, primarily used for aluminum and tungsten metal etching processes on 200mm wafers. The NMC508M is a multi-chamber cluster tool—an automated etching system capable of serial or parallel process handling. The system mainly consists of a transfer module, metal etch process module, strip module, cooling station, remote AC power rack, and control rack. The metal etch process module performs the metal etching process, while the strip module removes residual photoresist and corrosive gases after metal etching. The cooling station lowers wafer temperature, the transfer module safely and precisely transports wafers to designated stations, the power rack supplies electrical power to the system, and the control rack coordinates and manages the operation of all modules. Through a --- ## Fully Automatic Deep Cavity Wire Bonder DSP+FPGA Controller Solution - URL: https://intl.sienovo.cn/blog/126846070 - Date: 2022-09-14 - Tags: #SemiconductorEquipment, #DSP+FPGA, #Controller Equipment Specifications ■ Applications: Discrete devices, microwave components, lasers, optical communication devices, sensors, MEMS, SAW devices, RF modules, power devices, etc. ■ Wire Type: Gold wire (18μm-75μm) ■ Wire Loop Length, Loop Height: Fully programmable ■ Bonding Accuracy: ±3μm@3sigma ■ Ultrasonic Range: 0~0.4W control accuracy, stepped flexible application capability, adjustable in 1mW increments ■ Cavity Depth Compatibility: ≥9mm (with 19mm capillary); ≥6mm (with 16mm capillary) ■ Pressure: 0-220g, adjustable in 1g increments ■ Compatible Capillary Lengths: 16mm, 19mm ■ Bonding Area: Large area: 304.8mmX457.2mm, 0~180° rotation range ■ Bonding Speed: ≥4wire/s ■ Operating System: Windows ■ Equipment Net Weight: 1350kg ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126846070/01_33a66a7f0a940dcb2fa0d887ddb9000e.jpeg) Key Features Real-time deformation monitoring; Real-time ultrasonic energy monitoring; Fixed-length, fixed-height loop control --- ## Beckhoff XTS | Magnetic-driven Flexible Transport System with Circular Track, EtherCAT DSP+FPGA Controller - URL: https://intl.sienovo.cn/blog/126845832 - Date: 2022-09-14 - Tags: #RingLine, #DSP+FPGA, #ETHERCAT ## XTS | Magnetic-driven Flexible Transport System Customization services available. [Product Overview Table](https://www.beckhoff.com.cn/zh-cn/products/motion/xts-linear-product-transport/tabular-product-overview/ "产品概览表")[Product Finder](https://www.beckhoff.com.cn/zh-cn/products/motion/product-finder-motion/ "产品搜索器") ### Products ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126845832/01_c974211aee8be71274bbe5242b2db3bd.png) #### AT2xxx, ATH2xxx | XTS Motor Modules All active components in the XTS motor modules are integrated into a compact installation space. [More information](https://www.beckhoff.com.cn/zh-cn/products/motion/xts-linear-product-transport/at2xxx-ath2xxx-xts-motor-modules/ "更多信息") ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126845832/02_b52059f0a0c58cb49489428242faeb77.png) #### AT8x00, AT9xxx, ATH9xxx | XTS Guide Rails and Movers Guide rails and movers are passive components in the XTS system that enable linear motion alon --- ## Soft PLC Solution on RK3568 + CODESYS ARM+LINUX Hardware Platform - URL: https://intl.sienovo.cn/blog/126839996 - Date: 2022-09-13 - Tags: #codesys, #RK3568, #ARM+LINUX #### **CODESYS Control Linux ARM SL** A Soft PLC compliant with the IEC 61131-3 standard and suitable for ARM & Linux hardware platforms. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126839996/01_95a703d7e8ab6c947dd31a6efe93eead.jpeg) **Product Description** CODESYS Control Linux ARM SL is a CODESYS Runtime for ARM & Linux hardware platforms. The Runtime's functionality can be extended through the system's hardware properties. After installing the accompanying CODESYS Deployment Tool plugin in CODESYS IDE, users can install this product on the target controller's Linux operating system via CODESYS IDE. CODESYS Runtime will automatically start after each reboot. CODESYS Runtime supports running for two hours without functional limitations and without a license. **Product Features** CODESYS Runtime supports a rich set of I/O interfaces, such as local I/O or bus-based I/O, and an integrated IEC 61131-3 protocol stack. Fieldbuses can be configured directly in CODESYS --- ## HarmonyOS + Rockchip Live Streaming All-in-One Machine Solution: 8K 8-Core CPU Hardware and Software - URL: https://intl.sienovo.cn/blog/126839751 - Date: 2022-09-13 - Tags: #LiveStreamingPC, #HarmonyOS, #RK3588, #RK3568 Why are more and more people choosing live streaming all-in-one machines? What live streaming equipment is available? Live Streaming Machine Price - KaiboYa Smart Live Streaming Machine. Professional video live streaming software that is efficient and convenient, meeting your diverse needs. Professionally provided, with convenient and efficient operation, making professional high-performance video live streaming simpler and more accessible for you. With a live streaming machine, you can also become an internet celebrity and directly use a green screen for live broadcasts. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126839751/01_c17d70c0b67e71ed7c18476fc65434ab.png) Platforms like Douyin and Kuaishou have significantly boosted the live streaming industry, simultaneously introducing new demands for live stream image quality, focus and tracking, and background switching. We leverage an integrated AI solution to achieve real-time processing of virtual backgrounds for l --- ## TMS320C6678 + XC7K160T DSP+FPGA+ AD 24bit High-Precision, High-Performance Domestic Mainboard Design Solution - URL: https://intl.sienovo.cn/blog/125736186 - Date: 2022-09-13 - Tags: #DomesticADC, #C6678+AD Recently, while developing a product, we used a domestic high-precision [ADC](http://www.elecfans.com/tags/adc/ "ADC"), the AS1412 from Yuanzi [Semiconductor](https://www.hqchip.com/gongsi.html "半导体"). We learned about its advantages: not only high precision and good linearity, but also low power consumption. It can meet the requirements for many force sensing [measurements](http://www.hqchip.com/app/851 "测量"), such as various weighing scale applications, industrial equipment, instrumentation, etc. The main components and features of the AS1412 can be seen in the figure below. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/125736186/01_d00658c793d55da193ac024e387d8dbd.png) This device primarily integrates internally: 1) A MUX (multiplexer) switch for setting sampling of external signals or the internal [temperature sensor](http://www.hqchip.com/app/951 "温度传感器"); 2) A PGA (Programmable Gain Amplifier) with settable gains of ×1, ×2, ×64, ×128; 3) An [ADC](https://dfm.el --- ## Autonomous Driving Nvidia Jetson + FPGA Design Solution - URL: https://intl.sienovo.cn/blog/126738265 - Date: 2022-09-07 - Tags: #AutonomousDriving, #AI, #MachineLearning This blog post delves into the integration of Nvidia Jetson NX and Xilinx ZYNQ platforms, leveraging FPGAs for high-speed MIPI video data acquisition. We'll explore how this powerful combination forms the backbone of advanced systems, including electronic countermeasures and multi-object recognition solutions, before expanding into a comprehensive overview of the hardware and software architectures essential for autonomous driving applications. ## System Overview: Jetson NX, ZYNQ, and FPGA Integration Modern edge AI applications, particularly in demanding fields like autonomous driving and electronic countermeasures, require a blend of high-performance processing and flexible, real-time data handling. This is precisely where the synergy between Nvidia's Jetson NX platform and Xilinx ZYNQ FPGAs shines. The Nvidia Jetson NX, a compact and powerful System-on-Module (SOM), offers significant AI computing capabilities with its NVIDIA Volta GPU and ARM CPUs, making it ideal for complex AI --- ## ARM/DSP+FPGA运动控制机器视觉控制器方案定制 - URL: https://intl.sienovo.cn/blog/126698258 - Date: 2022-09-05 - Tags: #FPGADev, #arm, #ComputerVision ARM/DSP+FPGA Motion Control Machine Vision Controller Solution Customization ARM/DSP+FPGA Motion Control Machine Vision Controller Solution Customization. Xinmai possesses mature solutions in this area. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126698258/01_7290a6c536db03328b1525e34bf7a929.jpeg) Machine vision is a branch of computer vision. Visual control or visual applications in the field of industrial automation primarily refer to extracting relevant information from digitized images captured by front-end optical cameras. After analysis and processing, this information is used for controlling production line processes or quality, thereby replacing repetitive manual operations. Currently, practical applications of machine vision in factory production include: integrity quality inspection of workpieces, identification, classification, part position and orientation, dimensional measurement, code reading and traceability, surface/color difference detection, autom --- ## Domestically Developed FPGA-based EtherCAT Slave Real-time Low-Cost Motion Control System Solution - URL: https://intl.sienovo.cn/blog/126587946 - Date: 2022-08-29 - Tags: #FPGAEtherCATSlave What is an EtherCAT slave? What are its characteristics and advantages compared to others? How to implement an EtherCAT slave using an FPGA, and how to design and implement the basic communication link of an EtherCAT slave based on FPGA state machine design and verify it. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126587946/01_443d6f5d1d5562504b3c339f628577ef.jpeg) Abstract: EtherCAT is one of the widely used fieldbuses in industrial control. The EtherCAT Slave Controller (ESC) is crucial for slave modules to achieve EtherCAT protocol data communication. Achieving independent and controllable slave control chips is an important foundation for the domestic research and development of industrial control systems. Based on the EtherCAT communication protocol and basic communication functional logic, FPGA state machines for key communication nodes such as EBUS encoding/decoding, Auto-forwarder, and Loop-back funcTIon were designed. By analyzing data state changes at eac --- ## DSP/ARM+FPGA-based PLC-like High-Performance High Real-time EtherCAT Motion Control System Solution - URL: https://intl.sienovo.cn/blog/123171075 - Date: 2022-08-29 - Tags: #FPGADev, #arm, #ethercat FPGAs, with their hardware programmability, are attracting increasing attention from developers in the motion control field. When FPGAs are used to implement motion control systems, realizing the main motion control functions within the FPGA can reduce the number of components required and shrink the system's volume. FPGAs offer good expandability, are easy to maintain, and allow for straightforward system upgrades. Their speed advantage enables them to meet the demands of control applications requiring high system performance and precision. Users can program the hardware according to their needs, allowing for optimized utilization of system hardware resources. Furthermore, it supports reconfigurable design, enabling users to update and upgrade their hardware in a timely manner when system requirements change. However, for implementing complex control algorithms, the required number of logic gates increases with complexity, raising system costs. The FPGA solution represents a trade-of --- ## Domestic RK3588+DSP+FPGA+AI Industrial Vision Motherboard Solution - URL: https://intl.sienovo.cn/blog/126575372 - Date: 2022-08-28 - Tags: #RK3588, #DomesticDSP, #DomesticFPGA, #AI Industry 4.0 is driving a new wave of industrial revolution, with interconnectivity as its core feature, and further informatization and intelligence as typical characteristics. To meet the demands of Industry 4.0, Rockchip has specifically provided solutions for HMI (Human-Machine Interface), data acquisition and control, and AI vision, which are widely applied across various industrial fields. Leveraging years of expertise in FPGA technology, Sienovo introduces a domestic RK3588 + DSP + FPGA + AI industrial vision motherboard solution. ## ******1. Functional Requirements****** 1. Equipped with video/image decoding unit, video/image encoding unit, serial communication unit, and video buffering unit; 2. Capable of image acquisition, frame buffering, preprocessing, and serial communication control; 3. Capable of image enhancement, object detection, and object tracking. ## ******2. Performance Requirements****** 1. Real-time processing of video stream data at 1920×1080 resolution (25 --- ## Domestic DSP/ARM + Fudan Micro ZYNQ/A7/K7 FPGA Series Solutions - URL: https://intl.sienovo.cn/blog/126260024 - Date: 2022-08-24 - Tags: #FMSHFPGA, #DomesticFPGA, #DSP+ARM+FPGA ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126260024/01_97d676e7910859be5f29416af03418a2.jpeg) Customized DSP+ARM+FPGA Fudan Micro series solutions. RK3399/TI AM5728/C6657/C6678 + Fudan Micro ZYNQ/A7/K7 series. The pace of domestic substitution is urgent. Imported chips have only undergone functional verification and will soon be replaced by domestic ones. Currently, Fudan Micro is the only domestic company that has developed Zynq-like products. Shanghai Anlu and Chengdu Huawei are already developing them (it's not ruled out that Shenzhen Guowei is also working on it, as this market has huge potential). Table of Contents Application Scenarios Differences in Chip Architecture Procise Development Environment IAR Development Environment Market Potential Where are the application scenarios? First, let's be clear: Zynq-like ARM+FPGA heterogeneous SOC chips are absolutely not suitable for low-cost solutions. Why? Using these types of chips almost always requires --- ## Application of DSP+FPGA Main Control Board Design Solution Based on C6657 + Domestic FPGA in Nuclear Power Robots - URL: https://intl.sienovo.cn/blog/126429566 - Date: 2022-08-19 - Tags: #FPGADev, #Robotics 1 Evaluation Board Introduction Based on TI KeyStone C66x multi-core fixed-point/floating-point DSP TMS320C665x + domestic FPGA A7/K7 processor; The TMS320C665x has a main frequency of 1.0G/1.25GHz, with single-core computing capability up to 40G MACS and 20G FLOPS. The FPGA XC7A100T features 101K logic cells and 240 DSP Slices; Ø The TMS320C665x and FPGA are connected via communication interfaces such as uPP, EMIF, I2C, PCIe, and SRIO, with PCIe and SRIO achieving a maximum transmission speed of 5 GBaud per lane; Ø The FPGA acquisition card supports dual-channel 250MSPS*12Bit high-speed high-precision ADC and one-channel 175MSPS*12Bit high-speed high-precision DAC, meeting various data acquisition requirements; Supports Gigabit Ethernet, connectable to industrial network cameras, and also supports common interfaces such as I2C, SPI, UART, and McBSP; Ø Supports expansion modules such as CameraLink input/output and VGA output; Supports bare metal and SYS/BIOS operating sy --- ## RK3588+AI+FPGA Image Processing Hardware Algorithm Acceleration Solution - URL: https://intl.sienovo.cn/blog/126418195 - Date: 2022-08-19 - Tags: #AI, #FPGADev The RK3588 is Rockchip's new generation flagship high-end processor, featuring high computing power, low power consumption, powerful multimedia capabilities, and rich data interfaces. It is equipped with an octa-core CPU (quad-core A76 + quad-core A55) and an ARM G610MP4 GPU, with a built-in NPU providing 6.0 TOPs of computing power. **Five Major Technical Advantages** 1. Built-in multiple powerful embedded hardware engines, supporting 8K@60fps H.265 and VP9 decoders, 8K@30fps H.264 decoder, and 4K@60fps AV1 decoder; supports 8K@30fps H.264 and H.265 encoders, high-quality JPEG encoder/decoder, and dedicated image pre-processor and post-processor. 2. Built-in 3D GPU, compatible with OpenGL ES1.1/2.0/3.2, OpenCL 2.2, and Vulkan 1.2. A special 2D hardware engine with MMU will maximize display performance and provide a smooth operating experience. 3. Built-in Rockchip's self-developed 48MP ISP (Image Signal Processor), supporting numerous algorithm accelerators such as HDR, 3A, LSC, --- ## RK3399+XILINX K7 FPGA Applied in Radar, Communication, Telemetry, Imaging, and Other Fields - URL: https://intl.sienovo.cn/blog/126235520 - Date: 2022-08-15 - Tags: #RK3399+K7, #RK3399+FPGA xdma driver compilation on ARM, cross-compiler configuration, and kernel compilation. Here's an image first. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126235520/01_0b3cb910e96e57f729d3d06da5545613.jpeg) The following refers to [XILINX FPGA+RK3399 PCIE X4\_FPGA零下的博客-CSDN博客](https://blog.csdn.net/wcdlove/article/details/112839141 "XILINX FPGA+RK3399 PCIE X4_FPGA零下的博客-CSDN博客") xdma Compilation Instructions 1. Install cross-compiler (official version 6.3 is used) // An highlighted block    1、 mkdir -p /opt/FriendlyARM/toolchain/  # Create a new directory    2 、cp gcc \-linaro-7.4.1-2019.02-x86\_64\_aarch64-linux-gnu.tar  /opt/FriendlyARM/toolchain/    3、tar xvf gcc-linaro-7.4.1-2019.02-x86\_64\_aarch64-linux-gnu.tar # Extract the compiler to the current directory    4、 mv  gcc-linaro-7.4.1-2019.02-x86\_64\_aarch64-linux-gnu  gcc-linaro-7.4.1    # Shorten the name    5 、source setEnv.sh  # Set temporary environment variables, only valid in the current terminal, sour --- ## AM5728 + XILINX Artix7/Kintex7 Triple-Core High-Speed Image and Data Signal Acquisition Processing Platform - URL: https://intl.sienovo.cn/blog/121502921 - Date: 2022-08-10 - Tags: #MotionControl, #omapl138, #arm+fpga The Sienovo XM5728-IDK-V3 development board communicates with Artix7/Kintex7 development boards via the PCIe interface, enabling a DSP + ARM + FPGA triple-core communication architecture. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/121502921/01_e6cf909ea8cf87c1b4c86522682d93eb.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/121502921/02_5b11af6ee6ada3cdfef726dfc5be79d0.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/121502921/03_59677389b5f6a8d77447c45e8c3a831e.jpeg) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/121502921/04_64e6c90c8c8689c8c6e9ae31eccbd5e1.jpeg) XM5728-IDK-V3 Machine Vision & Motion Control Mainboard ■ Adopting a core board + baseboard design for configurable, application-driven customization ■ ARM core handles HMI interface + DSP core performs complex data computation + FPGA enables high-speed motion control ■ Supports various motor drivers: pulse motors, frequency-controlled motors, Y --- ## Overall Software System Solution Design for Semiconductor and New Energy Intelligent Equipment - URL: https://intl.sienovo.cn/blog/126235218 - Date: 2022-08-08 - Tags: #SmartEquipment, #SystemSoftware, #SoftwareCustomization, #NewEnergyEquipment, #SemiconductorEquipment Sienovo's software system solution portfolio for semiconductor and new energy intelligent equipment spans the full manufacturing lifecycle — from product development and quality assurance through logistics, deployment, and service. This post walks through two core pillars of that portfolio: the Smart Terminal Testing solution and the Hardware & OS Compatibility Testing solution, covering how each is structured, what testing methods are applied, and what measurable outcomes manufacturers can expect. ## Solution Architecture Sienovo's Smart Equipment Business Unit starts from a single design principle: move manufacturing enterprises along the maturity curve from automation → informatization → intelligence. The architecture shown below ties together proprietary information technology, enterprise digitalization tooling, and domain-specific manufacturing knowledge into a single integrated platform that runs across marketing, R&D, manufacturing, and after-sales service. ![](https://pub-04 --- ## Driver Development — Steadfast and Diligent Learning - URL: https://intl.sienovo.cn/blog/6707578 - Date: 2022-08-07 - Tags: #Tencent, #ZTE, #Server, #Huawei, #Samsung, #Smartphone ## Driver Development — Steadfast and Diligent Learning In this article, we will explore the multifaceted aspects of driver development, application development, and the invaluable lessons learned from influential mentors in the tech industry. The insights shared here are essential for anyone looking to deepen their understanding of these fields and enhance their career prospects. ## I. Influence of A — Driver Development ### Dive Deep into Driver Development Driver development is a critical area within software engineering that involves creating software components that allow the operating system to communicate with hardware devices. This field is relatively challenging due to the complexity of hardware interactions and the need for a thorough understanding of both the hardware and software layers. ### Understanding System Operations Before diving into driver development, it is beneficial to work on entire systems. This approach provides a comprehensive understanding of how vari --- ## Introduction to DSP+ARM+FPGA High-Speed PCIe/Gigabit Ethernet Signal Simulation - URL: https://intl.sienovo.cn/blog/126211285 - Date: 2022-08-07 - Tags: #java, #ProgrammingLanguage First, a self-introduction. I am a Signal Integrity (SI) engineer, with 17 years of work experience to date. Of course, I haven't been exclusively working on signal integrity for all 17 years, but all my work has been related to it. I've done PCB layout, SIPI (Signal Integrity, Power Integrity) simulation, hardware design, testing, and other tasks, but the vast majority of my experience and effort has been focused on SIPI. Naturally, when I first graduated, I wasn't doing SI. Thanks to a certain company's open technical platform, I, as a PCB layout engineer, was able to get exposed to SI. I believe many PCB layout engineers today, like me back then, are dissatisfied with the status quo and want to expand their skills, improve their compensation, and learn SI. However, they struggle with where to start, even though there are many signal integrity books available, making it overwhelming to choose from. In a series of upcoming shares, I will introduce how I self-learned SI and became a --- ## Embedded XM-RK3568 Industrial Interconnection Solution Featuring OpenHarmony OS - URL: https://intl.sienovo.cn/blog/126185554 - Date: 2022-08-05 - Tags: #harmonyos, #HarmonyOSRK3568, #HarmonyOSIndustrial The RK3568 chip is a mid-to-high-end general-purpose SoC, manufactured with a 22nm process technology, integrating a quad-core A55 processor and a Mali G52 GPU. It has a built-in independent NPU with 0.8 TOPS computing power. The chip features rich peripheral interfaces, supporting display peripherals such as HDMI, eDP, MIPI, and LVDS. Through interfaces like GPIO, RS485, RS232, and ADC, it can connect to PLC programmable controllers, photoelectric conversion module sensors, and more. In industrial applications, the RK3568 is primarily used as the processor for products such as IoT gateways, NVR storage, industrial panel PCs, industrial inspection devices, and industrial control boxes. It is widely applied in scenarios like industrial inspection, process control, data acquisition, control computers, and centralized IPC management. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126185554/01_95a703d7e8ab6c947dd31a6efe93eead.jpeg) ![](https://pub-048dcb96257f476697b113fcb --- ## RK3568 + HarmonyOS Industrial Tablet and Digital Signage Solution Design - URL: https://intl.sienovo.cn/blog/126114592 - Date: 2022-08-03 - Tags: #harmonyos, #IndustrialTablet, #RK3568HarmonyOS RK3568 + HarmonyOS Industrial Tablet and Digital Signage Solution Design. Equipped with RK3568 quad-core 64-bit processor 8GB RAM to meet demanding requirements Supports Android, Linux, OpenHarmony RS232/485, USB2.0, USB3.0, 2*GPIO Dual Gigabit Ethernet ports RK3568/3288/3399 + HarmonyOS is widely applied in industrial tablets, military, medical, and other domestic IT innovation industries, supporting software and hardware customization! Not only does it feature a domestic operating system and a sleek design, but it also offers rich interfaces, powerful core functions, and comes with a 10.1-inch LCD display. Application scenarios include: Smart Manufacturing, Smart Finance, Smart Transportation, Self-service Terminals, etc.  ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/126114592/01_d1bd5e1ccbe4f900ba9e8dc75250042d.png) The XM3568A motherboard adopts the Rockchip RK3568 quad-core 64-bit Cortex-A55 processor, with a main frequency of up to 2.0GHz, offering sign --- ## RK3588+FPGA High-Speed Image Processing and Communication Processor Solution - URL: https://intl.sienovo.cn/blog/126114676 - Date: 2022-08-02 - Tags: #FPGADev RK3588+FPGA high-speed image processing and communication processor solution. (1) Based on the RK3588 + Xilinx Artix-7 FPGA processor; (2) The RK3588 EVB features the RK3588 chip, built on an 8nm process technology, with a CPU configuration of quad-core ARM Cortex-A76 + quad-core ARM Cortex-A55, integrated 6 TOPS independent NPU, powered by the RK806-2 dual PMIC power solution, supports LPDDR4X/eMMC storage, and offers over 10 peripheral interfaces including HDMI, MIPI, VGA, and SATA. It features high integration, strong performance, and excellent expandability, meeting the requirements of various industry AIoT terminal devices; (3) The RK3588 and FPGA are connected via communication interfaces such as uPP, EMIF, I2C, PCIe, and SRIO, where PCIe and SRIO can achieve a maximum transmission rate of up to 5 GBaud per lane; (4) The FPGA acquisition card supports dual-channel 250MSPS × 12-bit high-speed, high-precision ADC and one 175MSPS × 12-bit high-speed, high-precision DAC, fulf --- ## Nvidia AGX Xavier GMSL Autonomous Driving Controller Design Solution - URL: https://intl.sienovo.cn/blog/125776868 - Date: 2022-07-14 - Tags: #AutonomousDriving, #Controller, #jetson Designing an autonomous driving perception controller around NVIDIA Jetson AGX Xavier and GMSL camera serialization involves hardware selection, carrier board layout, and a non-trivial software bring-up sequence. This article walks through Sienovo's GEAC91V platform — a dual-Xavier controller purpose-built for vehicle-grade deployments — and documents the key hardware design decisions and software debugging pitfalls engineers encounter when integrating MAX9296/MAX9295 GMSL2 camera links on Xavier. ## Why AGX Xavier for Autonomous Driving? Environmental perception is the foundation of any autonomous driving stack, and neural network inference is the computational heart of that perception. Traditional general-purpose CPUs cannot sustain the throughput required for real-time multi-camera image processing, LiDAR point cloud fusion, and object detection at automotive frame rates. This gap drove the development of dedicated inference accelerators. NVIDIA began addressing the automotive se --- ## Spiking Neural Network (SNN) Tape-out Verification for Neuromorphic Chips - URL: https://intl.sienovo.cn/blog/125736328 - Date: 2022-07-12 - Tags: #NeuromorphicChip, #FPGA ## Spiking Neural Network (SNN) Tape-out Verification for Neuromorphic Chips As the field of artificial intelligence (AI) continues to advance, the need for efficient and scalable computing solutions has become increasingly important. One area of research that has gained significant attention is neuromorphic computing, which aims to mimic the structure and function of the human brain. In this context, spiking neural networks (SNNs) have emerged as a promising approach for building efficient and adaptive AI systems. In this article, we will explore the process of tape-out verification for SNN-based neuromorphic chips, a critical step in ensuring the quality and reliability of these complex systems. ### Background on Neuromorphic Computing and SNNs Neuromorphic computing is a subfield of AI that focuses on developing computing systems inspired by the structure and function of the human brain. SNNs, in particular, are a type of neural network that uses spikes (short pulses of electrica --- ## Xinmai Offers Open-Source EtherCAT Master IgH Examples for Platforms Including ZYNQ, AM5728, AM5708, AM437x, AM335x, and STM32+FPGA - URL: https://intl.sienovo.cn/blog/125736005 - Date: 2022-07-12 - Tags: #fpga, #igh, #ethercat, #zynq, #stm32 Xinmai (Sienovo) has released open-source EtherCAT master examples based on the IgH EtherCAT Master stack, targeting a broad range of industrial SoC and hybrid FPGA platforms: ZYNQ, AM5728, AM5708, AM437x, AM335x, and STM32+FPGA. This post documents the validated development environment and hardware configuration that these examples are built against, serving as a quick-start reference for engineers bringing up real-time EtherCAT control on any of these platforms. ## Why IgH EtherCAT on Embedded Linux? EtherCAT is a deterministic fieldbus protocol widely used in motion control, robotics, and industrial automation. The IgH EtherCAT Master is the dominant open-source implementation — it runs as a Linux kernel module, intercepts raw Ethernet frames, and drives the EtherCAT state machine with microsecond-level cycle times when paired with a real-time kernel extension. For embedded platforms like TI's Sitara family (AM5728, AM5708, AM437x, AM335x) and Xilinx ZYNQ, getting IgH to compile --- ## 信迈基于FPGA ZYNQ的Ethercat高实时工业控制解决方案 - URL: https://intl.sienovo.cn/blog/118280228 - Date: 2022-07-12 - Tags: #ZYNQ, #Ethercat, #FPGA, #XENOMAI --- Title: Xinmai's FPGA ZYNQ-Based EtherCAT High-Real-Time Industrial Control Solution Content: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118280228/01_630efec2b03fc5b5ed661b77756a53eb.png) Figure 1: Hardware Architecture Diagram ### EtherCAT Master Hardware Introduction The master hardware consists of three main components (see Figure 4): the PC side, the Zedboard master development board, and the expanded FMC network card. The PC uses a serial terminal to input operating system commands. The EtherCAT network diagnostic and configuration tool, KPA EtherCAT Studio on the PC side, connects to the Zedboard master board via RPC services to configure the master and slave stations and generate network configuration files by scanning. For details on the Zedboard as an EtherCAT master board, refer to [Avnet: Quality Electronic Components & Services](http://zedboard.org/product/zedboard "Avnet: Quality Electronic Components & Services"). ![](https://pub-048d --- ## DSP+ARM+FPGA Main Control Board Design Solution Based on C6657+ZYNQ7045 - URL: https://intl.sienovo.cn/blog/125670686 - Date: 2022-07-08 - Tags: #FPGADev, #C6657, #ZYNQ7045 ## **XM-6657Z45****\-EVM**** Evaluation Board Specification** Table of Contents [XM-6657Z45-EVM Evaluation Board Specification](#_Toc14013) [1 Evaluation Board Introduction](#_Toc13706) [2 Typical Application Areas](#_Toc4165) [3 Software and Hardware Parameters](#_Toc26723) [4 Development Resources](#_Toc7685) [5 Electrical Characteristics](#_Toc7769) [6 Mechanical Dimensions](#_Toc26660) [7 Technical Services](#_Toc24353) [8 Value-Added Services](#_Toc5250) ### **1 Evaluation Board Introduction** * Based on TI KeyStone C66x multicore fixed-point/floating-point DSP TMS320C665x + Xilinx ZYNQ7045 FPGA processor; * TMS320C665x has a core frequency of 1.0G/1.25GHz, with single-core processing capability up to 40G MACS and 20G FLOPS; FPGA XC7A100T has 101K logic cells and 240 DSP Slices; Ø * TMS320C665x and FPGA are connected via communication interfaces such as uPP, EMIF, I2C, PCIe, and SRIO, with PCIe and SRIO each supporting a maximum transmission speed of 5 GBaud; Ø --- ## RK3399pro YOLOv5 AI Accelerated Inference Solution - URL: https://intl.sienovo.cn/blog/125630024 - Date: 2022-07-05 - Tags: #AI, #ubuntu, #python ### 0\. Introduction: > This article introduces the deployment and inference of the YOLOv5s algorithm on the domestic Rockchip RK3399ProD. It describes the entire process, provides a brief introduction to using the RKNN Python API based on the RK3399Pro, and records some pitfalls encountered. This article is for discussion purposes only, and any misunderstandings or errors in the text are welcome for discussion. * * * ### 1\. Deployment Process 1. **On the server or PC**, train the model. After training, convert the .pt file to ONNX format. 2. **On the PC**, use rknn-toolkit 1.6.0 to convert the ONNX model to RKNN format. 3. Perform model inference on the **RK3399Pro**. For the second step, model conversion, it can be done on an RK3399Pro with rknn-toolkit installed. Previously, when I didn't know better, I always converted on this development board. However, it is still recommended to convert on a PC running Ubuntu 18.04, as you can set a larger quantization batch size, which --- ## 16-Channel High-Speed ADC Data Acquisition System Based on Kintex-7 FPGA + Nvidia TX2 - URL: https://intl.sienovo.cn/blog/125627285 - Date: 2022-07-05 - Tags: none In previous designs involving ADC sampling, performance considerations typically revolved around resolution and sampling rate. Generally, resolution is either fixed or has a maximum configurable value, while sampling rate—when too high—can lead to inaccurate sampling and often becomes a bottleneck for overall system performance. Therefore, there has always been a desire for a system that enables high-speed ADC sampling with both remote and local data storage capabilities, where the sampling rate and storage speed are both high, and the design offers maximum flexibility. The recently released K7+TX2 platform from Sienovo XMTech perfectly fulfills this requirement as a prototype system. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/125627285/01_a54831ae052dc37b972c0ce22a79e8c7.jpeg) **XMTech High-Speed 16-Channel Data Acquisition System** The latest high-speed data acquisition system from XMTech supports 16-channel, 8-bit ADC analog-to-digital conversion with a maximum --- ## RK3568 + HarmonyOS Industrial Control Board for Industrial Gateway and Video Gateway Solutions - URL: https://intl.sienovo.cn/blog/125420453 - Date: 2022-07-05 - Tags: #RK3568, #HarmonyOS The Sienovo XM3568A motherboard features Rockchip's RK3568 quad-core 64-bit Cortex-A55 processor, with a maximum clock frequency of 2.0GHz, delivering significantly improved performance. Built on a 22nm advanced process, it offers high efficiency with low power consumption. Equipped with a dual-core GPU architecture, high-performance VPU, and NPU. Supports OpenGL ES3.2/2.0/1.1 and Vulkan 1.1; enables 4K 60fps H.265/H.264/VP9 video decoding and 1080P 100fps H.265/H.264 video encoding. Rich expansion interfaces: includes 2 USB 3.0 ports, 8 USB 2.0 ports, MiPi DSI, eDP, I2C, UART, ADC, GPIO, and more, suitable for external device control and expansion. Supports Android and Linux OS upgrades, and system booting via USB drive, eMMC, and other methods. Diverse OS support makes entertainment, office work, programming, learning, and creative development effortless. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/125420453/01_c5676684f8666600d3512417ab22afd4.png) ![](https: --- ## Rockchip RK3399/RK3568 + FPGA Hardware Acceleration Design Solution - URL: https://intl.sienovo.cn/blog/124870062 - Date: 2022-07-05 - Tags: #tensorflow, #AI, #FPGA, #PCIE, #RK3399 Rockchip RK3399/RK3568 + FPGA hardware acceleration design solution. The RK3399 interfaces with the FPGA via MIPI or PCIe. Xinmai Technology offers a mature solution. FPGAs supported include ZYNQ/A7/K7, as well as domestic options like Anlogic and Gowin. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/124870062/01_35618cc0e987bf39afc940be958701a9.jpeg) First, let's understand the common image recognition frameworks used in Android systems. I. Using proprietary libraries for recognition Megvii's image recognition and OCR text recognition libraries, and OCR text recognition libraries from other manufacturers such as Alibaba, Baidu, Huawei, and Tencent. II. Using open-source libraries for recognition 1) TensorFlow for training and recognizing custom images 1. First, train many images on Ubuntu to obtain your category model files: xxx.pb and xxx_labels.txt. 2. Place the files generated in the previous step into your Android Studio (AS) project. 3. Add TensorFlow depen --- ## Design of an AI Image Acceleration Board Based on Nvidia Jetson + FPGA (ZYNQ) - URL: https://intl.sienovo.cn/blog/124853173 - Date: 2022-06-29 - Tags: #FPGADev, #AI Building AI inference at the edge often means combining the raw compute power of an NVIDIA Jetson SoC with the deterministic signal-processing flexibility of an FPGA — specifically Xilinx ZYNQ or Ultrascale+ devices. This post covers two concrete hardware designs that use this pairing: a MIPI/CameraLink video-capture board where ZYNQ feeds frames to a Jetson NX over PCIe, and a more elaborate smart-grid real-time co-simulation platform built around Jetson AGX Xavier and Xilinx VCU118/VCU128 FPGAs. ## ZYNQ + Jetson NX: MIPI Video Acquisition Over PCIe The first design is a 6U carrier board that pairs a Xilinx ZYNQ SoC with an NVIDIA Jetson Xavier NX module. The ZYNQ handles front-end image ingestion — either MIPI CSI-2 from machine-vision sensors or CameraLink from high-frame-rate industrial cameras — and the Jetson NX runs the AI inference pipeline for multi-target detection and tracking. The interconnect between the two devices is PCIe. This is a deliberate architectural choice: PC --- ## RK3568 Multi-Gigabit Ethernet Android Video Controller: A Fully Domestic Solution - URL: https://intl.sienovo.cn/blog/125420701 - Date: 2022-06-23 - Tags: #RK3568, #MultiEthernet, #HarmonyOS The Xinmai XM-3568-01 motherboard features a Rockchip RK3568 quad-core Cortex-A55 processor with a main frequency of up to 2.0GHz, offering significantly improved performance. It supports up to 8GB of memory capacity with a frequency of up to 1600MHz, and full-link ECC for safer and more reliable data. It is equipped with dual gigabit adaptive RJ45 Ethernet ports and extends to 4 additional I211 Ethernet controllers, making it suitable for gigabit routers, soft-routers, firewalls, and other applications. Supports HarmonyOS + Android 11 + Linux. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/125420701/01_78f4472e02823222fa87b10d29612a0f.png)  ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/125420701/02_83b0f11ee45231aa4b39666c7b709654.png)   **Processor System** CPU RK3568，ARM Cortex A55，Quad-core，2 GHz GPU G52 2EE,OpenGL ES1.1/2.0/3.0/3.1/3.2, Vulkan 1.1, OpenCL 2.0 NPU RK NN, 0.8Tops **Memory** Type 32-bit，LP4/LP4x Capacity 2GB(Up to 8GB) --- ## 基于Nvidia jetson NX的边缘端人工智能解决方案 - URL: https://intl.sienovo.cn/blog/125254080 - Date: 2022-06-13 - Tags: #nvidia, #nx --- Title: Edge AI Solution Based on NVIDIA Jetson NX Content: ## ******EC07-********Industrial-Grade Edge AI BOX Based on NVIDIA Jetson Xavier NX Core Module****** **(Carmel ARMv8.2 + 8GB DDR4L + 16GB eMMC)** This is an industrial-grade, high-performance Edge AI BOX built around the NVIDIA Jetson Xavier NX core module. By combining the Xavier NX core module with a self-developed carrier board and leveraging the core module's powerful expansion bus capabilities, this compact system meets stringent size requirements while delivering exceptional inference processing performance. It is a compact edge computing solution ideal for high-performance video and image recognition tasks—such as identifying people, objects, text, and other visual features. When paired with wired or wireless network connectivity and cloud servers, it enables a complete AIoT solution combining cloud-based learning with edge-side inference. This industrial computer is well-suited for AI and IoT applications and i --- ## RK3568-based Low-Cost 6-Port Gigabit Ethernet AI Industrial Gateway Design Solution - URL: https://intl.sienovo.cn/blog/125092152 - Date: 2022-06-08 - Tags: #RK3568, #IndustrialGateway, #6PortGigabit, #CostEffective ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/125092152/01_15f4dc4de52a7122ab4dc69c5caa5aa1.png) As the Industrial Internet of Things (IIoT) becomes more widespread and powerful, RK3568-based edge computing gateways have emerged. Edge computing effectively reduces the load on cloud servers, significantly decreases bandwidth usage, and also provides convenient conditions for localized regional autonomy. Edge computing industrial gateways perfectly leverage the combined advantages of "edge" and "endpoint." Through 4G/5G communication and the internet, they integrate AI, Industrial IoT, and edge computing to achieve features such as cloud-edge collaboration, edge-endpoint linkage, compute power offloading, and regional autonomy. They can be widely applied in fields such as Industrial IoT, smart transportation, power IoT, environmental protection and fire safety, and smart agriculture. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/125092152/02_0130a0d1cf19 --- ## Ximea's Technical Approach and Application Scenarios for 3D Machine Vision - URL: https://intl.sienovo.cn/blog/125117486 - Date: 2022-06-03 - Tags: #3d, #ComputerVision, #AI **1. Typical Application Areas of 3D Cameras:** 1) Obstacle detection and "human-like" navigation for autonomous vehicles (e.g., forklifts) in industrial environments 2) Robot control for pick-and-place operations on conveyors or part handling tasks 3) Presence/absence inspection and counting of objects within containers or boxes, even when objects exhibit no contrast against the background 4) Position and presence verification of components on circuit boards 5) Volume measurement of various objects, etc. **2. Popular 3D Technologies** Commonly used techniques in 3D image processing include: 1) Stereo vision and structured light 2) Laser triangulation 3) ToF (Time-of-Flight) **3. Stereo Vision and Structured Light** Stereo vision operates on the same principle as human binocular vision. Two 2D images of an object are captured using two cameras. The same scene is recorded from two different positions, and using triangulation, a 3D image incorporating depth information is sy --- ## Zynq FPGA Low Latency H.264 Design Solution (Encoding + Decoding < 1ms) - URL: https://intl.sienovo.cn/blog/122848777 - Date: 2022-06-01 - Tags: #ZYNQ, #H264, #LowLatency, #FPGA, #WirelessVideoLink Achieving sub-millisecond H.264 encode latency in a real-time video link—while keeping the entire system on a single small PCB—has long been the holy grail of embedded video design. This post walks through how Xinmai Technologies' pure-hardware H.264 IP core, deployed on a Xilinx Zynq-7000 SoC, makes that possible: encoding latency of 0.5 ms, end-to-end glass-to-glass latency under 50 ms, and a complete encode/decode system that fits on a board small enough for an unmanned aerial vehicle (UAV) or other size-constrained platform. ## The Architecture Trade-off: ASSP vs. FPGA+Processor Designers building compact IP-based streaming video systems have historically been caught between two unsatisfying extremes. **ASSP (Application-Specific Standard Product)** chips offer dense integration and low power, but their fixed function blocks are rigid. Most ASSP video encoders provide only two camera inputs, forcing designers to multiplex multiple video streams onto a single input bus. On-screen --- ## Implementation of a ZYNQ-based Wireless Ultrasound Data Transmission and Display System - URL: https://intl.sienovo.cn/blog/124934785 - Date: 2022-05-23 - Tags: #ZYNQ, #WirelessTransmission With the rapid development of internet technology, mobile devices have become indispensable tools in human life, offering a wide array of functions through various app supports. Therefore, this project combines traditional medical ultrasound probes with everyday mobile phones, using mobile devices as terminals for wireless probe data display. It proposes replacing traditional wired ultrasound probes with wireless ones as medical devices, enabling users to monitor their conditions anytime, facilitating operation for doctors or users, and greatly simplifying doctors' work. The integration of mobile phones and medical ultrasound acquisition devices will bring substantial breakthroughs to the medical industry. This project primarily aims to implement a portable wireless ultrasound probe data transmission system and its overall software system. It involves developing Android software on mobile phones for image observation, processing ultrasound data on the phone, and using a database to s --- ## Design and Implementation of a ZYNQ+AD9361-based Software Defined Radio Platform (2) - URL: https://intl.sienovo.cn/blog/124934547 - Date: 2022-05-23 - Tags: #ZYNQ, #AD9361, #Radio ## [Design and Implementation of a ZYNQ+AD9361-based Software Defined Radio Platform (1)](https://blog.csdn.net/YEYUANGEN/article/details/122832172 "Design and Implementation of a ZYNQ+AD9361-based Software Defined Radio Platform (1)") ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/124934547/01_212b48ba2dbe438676179d00ee0e47ff.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/124934547/02_59b185b3e3f27a0832fa50264bd104be.png) ### **1 Evaluation Board Introduction** Xinmai Technology XM-ZYNQ7045-EVM is a high-end heterogeneous multi-core SoC evaluation board designed based on Xilinx Zynq-7000 series XC7Z045/XC7Z100 high-performance processors. The processor integrates a dual-core ARM Cortex-A9 on the PS (Processor System) side and 28nm Kintex-7 architecture programmable logic resources on the PL (Programmable Logic) side. The evaluation board consists of a core board and an evaluation baseboard. The core board has undergone professional PCB layout and --- ## Design and Implementation of an EOD Robot Control System Based on DSP+FPGA - URL: https://intl.sienovo.cn/blog/124933458 - Date: 2022-05-23 - Tags: #FPGADev, #DSPDev Currently, Explosive Ordnance Disposal (EOD) robots play an important role in the increasingly severe global terrorist attacks, significantly reducing casualties. Therefore, research on EOD robots holds significant social importance. However, the high price of EOD robots on the market hinders their widespread adoption. This paper, from the perspective of practical application, proposes a design scheme for an EOD robot control system based on DSP+FPGA, completes the hardware platform construction and software development for the EOD robot control system, and verifies it through experiments. The hardware platform of the EOD robot control system is centered around DSP and FPGA. The system adopts a modular design approach, with independently designed sub-modules, mainly divided into a motion control module, power module, data communication module, and video acquisition module. The motion control module is developed using an FPGA, which interacts with the DSP via the DSP's external interf --- ## Semiconductor Equipment C66x DSP+FPGA Motion Controller Design - URL: https://intl.sienovo.cn/blog/123345091 - Date: 2022-05-23 - Tags: #FPGADev, #C66X ## Semiconductor Equipment C66x DSP+FPGA Motion Controller Design In this blog post, we will explore the design and capabilities of a motion controller based on the TI KeyStone C66x DSP and Xilinx Artix-7 FPGA. This design is particularly relevant for applications requiring high-speed data acquisition and processing, such as advanced image processing and audio/video data handling. We will discuss the evaluation board's specifications, typical applications, hardware and software parameters, and the development resources available. ### 1. Evaluation Board Introduction The motion controller design integrates the TMS320C665x DSP with the Xilinx Artix-7 FPGA, creating a powerful platform for various industrial applications. Here are some key specifications: - **Processor Specifications**: - The TMS320C665x operates at clock speeds of 1.0G or 1.25GHz, offering impressive single-core processing capabilities of up to 40G MACS and 20G FLOPS. - The FPGA, specifically the XC7A100T model, --- ## ZYNQ Lidar-Visual SLAM Algorithm Porting and Design - URL: https://intl.sienovo.cn/blog/124908639 - Date: 2022-05-22 - Tags: #Robotics, #SLAM, #LaserVision This article details the development and implementation of a ZYNQ-based system for real-time 3D reconstruction, leveraging both FPGA-accelerated stereo vision and a LiDAR-based mobile platform. Readers will learn about the system's architecture, key algorithms like BM, SGBM, and ICP, hardware components including a Mecanum wheel robot and R-Fans-16 LiDAR, and its performance characteristics for environmental perception in applications like robotics and autonomous systems. ## FPGA-Accelerated Stereo Vision on ZYNQ The initial phase of this project focused on developing an FPGA-accelerated stereo vision system on a Xilinx ZYNQ platform for real-time 3D reconstruction. This involved a tight integration of the ZYNQ's Processing System (PS) and Programmable Logic (PL) for collaborative processing, enabling high-performance image processing tasks. Key achievements in this stereo vision component include: 1. **Stereo Image Acquisition and PS+PL Processing**: Successfully implemented the c --- ## Optimization and Implementation of a Zynq-based CNN Image Recognition Algorithm - URL: https://intl.sienovo.cn/blog/124856041 - Date: 2022-05-19 - Tags: #cnn, #Algorithm, #DeepLearning Convolutional Neural Network Training and Hardware Accelerator Implementation The second part of the image recognition system is the CNN accelerator, whose implementation involves two stages: training and inference. The first is convolutional neural network training, which involves extracting the corresponding weight and bias values, i.e., the training stage. The second is implementing the convolutional neural network based on the network model and performing hardware acceleration to improve the speed of convolutional neural network operations, i.e., the inference stage. Convolutional Neural Network Training 4.1.1 Convolutional Neural Network Model Construction The Flowers Recognition dataset used in this paper consists of 4242 flower images, comprising 5 categories: daisy, tulip, rose, sunflower, and dandelion. Each category contains approximately 800 images, and each image has an approximate size of 320×240. However, the images are not scaled to a uniform size and have different asp --- ## High-Performance Domestic Signal Processing Platform: Domestic DSP + FPGA + AI NPU Anlu Ziguang Solution - URL: https://intl.sienovo.cn/blog/124597073 - Date: 2022-05-13 - Tags: #FPGADev, #MCU, #EmbeddedHardware ### **I. With an NPU, do we still need a DSP?** · Both are processors designed to accelerate specific [algorithms](https://link.zhihu.com/?target=https%3A//www.icxbk.com/ask.html%3Fwords%3D%25E7%25AE%2597%25E6%25B3%2595 "算法"), however, NPUs target neural network algorithms while DSPs target signal processing algorithms, each with its own focus. NPUs adopt the Princeton architecture. DSPs adopt the Harvard architecture. Each has its own instruction set. DSPs specialize in digital signal processing. Even DSP processors are categorized into many different models and types, targeting various signal types, such as audio signals, images, and so on. NPUs specialize in neural network processing, handling different types of data. Processing AI with a general-purpose CPU versus an NPU yields different speeds, but why can't we do without a CPU? Because NPUs can only handle AI computations; they are not suitable for other tasks. · A DSP (Digital Signal Processor) is specifically designed --- ## Xilinx Zynq 7045 Implementation of Xinmai ISP IP Supporting 29 CMOS Sensors - URL: https://intl.sienovo.cn/blog/124699927 - Date: 2022-05-10 - Tags: #ZYNQ, #ISPCore **Background:** It is understood that Denali-MC IP designed by Xinmai Technology can now be implemented on multiple programmable chips, including Xilinx's Zynq 7045 FPGA device, and can be used in products featuring DSP or SoC+DSP architectures (including related products from TI and Qualcomm). The core of Denali-MC Monitor's ISP is a super-algorithm-based kernel. This algorithm core not only maximizes HDR capability for HDR-enabled imaging applications during image compensation but also delivers an end-to-end full camera ISP pipeline. These two advantages are highly significant for camera systems, as they play a crucial role in enabling cameras to capture usable video and maximize recognition points under any scene and lighting condition throughout the day. Below is a brief overview of Denali-MC. **Denali-MC:** The Denali-MC IP platform embeds a Sony IMX290LQR sensor and leverages the programmable logic within the Xilinx Zynq 7045 FPGA to support various frame configurations and --- ## ZYNQ-Based Mobile Robot Controller Design (3) – Controller Hardware Selection (Continued) - URL: https://intl.sienovo.cn/blog/124203907 - Date: 2022-04-15 - Tags: #ZYNQ, #MobileRobot, #Controller **3.1.4 ZYNQ Interface Technology** In this section, we introduce the interface technology of ZYNQ's heterogeneous system—specifically, its internal bus architecture. Before that, let's first compare traditional SoPC (System on a Programmable Chip) designs prior to Zynq. Previously, there were essentially two approaches: one was implementing a soft-core processor on an FPGA, such as Xilinx's MicroBlaze or Altera's NIOS II; the other was pairing an FPGA with a general-purpose embedded processor (such as an ARM). Both approaches had significant bottlenecks: the first mainly suffered from the soft-core's performance being far lower than that of a hard-core, while consuming substantial FPGA resources; the second often faced communication between the FPGA and the general-purpose processor becoming a difficult-to-overcome bottleneck, especially when high-bandwidth, low-latency data transfer was required. As the first product to tightly integrate a high-performance ARM Cortex-A series --- ## ZYNQ-Based Mobile Robot Controller Design (3) Controller Hardware Selection - URL: https://intl.sienovo.cn/blog/124203022 - Date: 2022-04-15 - Tags: #ZYNQ, #MobileRobot, #Controller, #RealTime This chapter introduces the selection of hardware solutions for the controller. First, it answers why the ZYNQ platform was chosen for the mobile robot controller design, analyzing the inherent compatibility between ZYNQ's architecture and our proposed controller design. Then, it dedicates significant space to explaining the key technologies that will be used, assuming ZYNQ is locked in, and the overarching design methodology that should be followed throughout the application of these key technologies. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/124203022/01_3a5573ca6dff45b80749a168d4fbfb18.png) In this paper, we select Xilinx Zynq-7000 AP (All Programmable) SoC, a rising star in the embedded processor field and defined as the paradigm for next-generation embedded processors, as our implementation platform for the following reasons: (1) Superior Performance As the embedded design field continuously pursues higher performance, lower power consumption, smaller form fa --- ## ZYNQ-based Mobile Robot Controller Design (2) Design Approach - URL: https://intl.sienovo.cn/blog/124187651 - Date: 2022-04-15 - Tags: #ZYNQ, #MotionController, #MobileRobot The mobile robot solution proposed in this paper aims to contribute to solving the aforementioned problems. This solution is suitable for the following application scenario: the robot relies on a simple, robust mechanical structure with sufficient strength to protect the control board and associated circuits, serving as a carrying platform. Movement is achieved by motor-driven wheels, operating in indoor and outdoor environments with non-adverse ground conditions, at low to medium speeds. The robot carries various common sensors, such as ultrasonic, infrared, laser, gyroscope, encoder, camera, etc., for environmental perception and self-pose estimation, and uses these sensors to achieve autonomous or human-intervened obstacle avoidance, map creation, path planning, image processing, and recognition functions. To make this application scenario more concrete and tangible, the following scenario was artificially set during the experimental process of this paper: the robot carries a rela --- ## ZYNQ-based Mobile Robot Controller Design (1) Background - URL: https://intl.sienovo.cn/blog/124187113 - Date: 2022-04-15 - Tags: #ZYNQ, #Controller, #MobileRobot This paper draws inspiration from the hierarchical paradigm of robotics, dividing the mobile robot controller into a drive-sensing layer, a real-time control layer, and an interaction layer. Based on a survey of existing mobile robot controller characteristics, a novel controller solution is proposed. This solution, tailored to the characteristics of mobile robot control, selects the Xilinx ZYNQ All Programmable SoC, which integrates multi-core ARM CPUs and an FPGA, as its hardware platform. On this platform, applying the concept of hardware-software co-design, the following tasks were completed: integrating hardware IP cores for drive sensing on the FPGA; and deploying bare-metal software for real-time control and Linux software for interaction on different CPUs. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/124187113/01_ad0fc96ce77cf44be61e2410cabb3bf0.png) This controller solution is suitable for application scenarios where mobile robots need to carry numerous sens --- ## DSP/ARM+FPGA Custom Motion Controller for Engraving Machines and CNC Machine Tools - URL: https://intl.sienovo.cn/blog/124160321 - Date: 2022-04-13 - Tags: #DSP+FPGA, #MotionController, #Customization Used for various intelligent equipment, ranging from simple point-to-point motion devices to complex trajectory motion devices such as engraving machines, CNC machine tools, and intelligent robots. Its main functional indicators include: 1. High-speed serial communication interface, enabling high-speed real-time communication between the human-machine interface (HMI) and the motion control system; * Can connect 4 axes for servo control, featuring 4-axis drive pulse and direction output functions, with a maximum pulse output frequency of 20 Mbps; 3. Utilizes 52 dedicated I/O ports to complete the transmission of dedicated control signals for 4-axis servo drives; * Features 64 I/O ports (32 inputs, 32 outputs) available for user-defined functions; 5. Provides 4 channels of quadrature encoder feedback, with a sampling frequency up to 20 MHz and a 32-bit encoder counter; 6. Offers 4 operating modes: Auto mode, Jog mode, Ref mode, and MDA mode; 7. Standard RS232 serial port and JTAG s --- ## Architecture of a High-Speed Data Processing Board Based on C66x and Domestic FPGA - URL: https://intl.sienovo.cn/blog/123787113 - Date: 2022-03-28 - Tags: #C66x, #DomesticFPGA Table of Contents Overview C66x Processor Core C66x Pipeline Structure Overview The C66x DSP is the latest generation of fixed-point and floating-point DSPs, comprising four multipliers to perform single-precision floating-point operations. The C66x DSP core can simultaneously execute up to eight floating-point multiplication operations, and coupled with a clock frequency of up to 1.4GHz, it achieves high floating-point processing performance. By integrating multiple C66x DSP cores with other cores, high-performance multi-core System-on-Chip (SoC) devices can be created. This article uses the TMS320C6678 as an example to introduce the C66x core. The TMS320C6678 features eight C66x cores, with each core operating at a maximum frequency of 1.4GHz, theoretically achieving processing performance of 179.2 (22.4x8) GFLOPs and 358.4 (44.8x8) GMACs. Each processor contains multi-level memory: L1P, L1D, and L2SRAM within the C66x core; and MSM SRAM as shared memory for multiple core --- ## Porting SOEM EtherCAT on TI DSP RTOS - URL: https://intl.sienovo.cn/blog/123536402 - Date: 2022-03-16 - Tags: #udp, #NetworkProtocol, #SOEM This project primarily focuses on porting SOEM to the Xinmai Technology TI OMAPL138 C6748 DSP. The main work involves adapting the operating system and hardware layers. Below, let's briefly introduce the concepts. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/123536402/01_9b1706f764117d2f8ce522fac1f004a7.png) EtherCAT is an open-architecture fieldbus system based on Ethernet. The EtherCAT data portion is encapsulated within Ethernet frames, and the master station sends these Ethernet frames for transmission over Ethernet. EtherCAT only requires the physical layer, data link layer, and application layer; the other four layers of the OSI seven-layer protocol architecture are not necessary. The EtherCAT frame structure can also be encapsulated in IP/UDP datagrams, which are then uploaded to the slave's application layer for processing by the slave controller's hardware [16]. This is illustrated in Figure 2.1. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog --- ## Low-Cost, High Real-Time EtherCAT Motion Controller Solution Based on ARM+FPGA - URL: https://intl.sienovo.cn/blog/123392605 - Date: 2022-03-10 - Tags: #FPGADev, #arm, #EmbeddedHardware As a core component of CNC systems, motion controllers are widely used in high-end robotics, CNC machine tools, industrial automation, and other fields. This article, set against the backdrop of practical engineering applications and aiming to develop an efficient, highly reliable, and feature-rich motion controller, conducts research and analysis on motion controllers and motion control algorithms. This work holds significant theoretical importance and practical application value for achieving high-speed, high-efficiency, and high-precision motion control. Based on an ARM+FPGA hardware architecture, a comprehensive hardware design scheme was proposed. The motion controller's hardware circuit, main control board, and expansion board were designed, and a 3D motion control platform was built. A comprehensive software design scheme for the motion controller was also proposed. A serial communication program was designed based on the MODBUS protocol, and a dynamic linked list was designe --- ## Design of Injection Molding Machine Motion Controller and Algorithms Based on DSP - URL: https://intl.sienovo.cn/blog/123392162 - Date: 2022-03-10 - Tags: #DSP, #MotionController, #MotionControlAlgorithm, #InjectionMolding ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/123392162/01_c435468a047f3d20a2b5dfcf8ebec848.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/123392162/02_2410fc9dfbfc507624f46a3724f2c2c2.png) A precision control system for injection molding machines was designed using a DSP as the lower-level controller and an ARM as the upper-level controller. The lower-level controller handles the execution of control algorithms and I/O operations, while the upper-level controller manages the human-machine interface and mold data. This control system offers excellent real-time performance and high control accuracy. However, a limitation is that control algorithms were not implemented directly on the control system, making it impossible to verify compatibility with different control algorithms. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/123392162/03_d97b785cefc4f41411fc4ae66d33ccdd.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/ --- ## TMS320F2837x + Spartan6/Domestic FPGA Low-Cost High-Real-Time Injection Molding Machine Motion Controller Hardware and Software Design Solution - URL: https://intl.sienovo.cn/blog/123390244 - Date: 2022-03-10 - Tags: #DSP+FPGA, #DSP28335, #MotionController A precise injection molding machine control system was designed using a DSP as the slave controller and an ARM as the master controller. The slave controller is responsible for executing control algorithms and I/O control, while the master controller handles the Human-Machine Interface (HMI) and mold data management. This control system offers good real-time performance and high control precision. A drawback is that control algorithms were not designed within the control system itself, making it impossible to verify compatibility with different control algorithms. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/123390244/01_d97b785cefc4f41411fc4ae66d33ccdd.png) The injection molding machine controller is a control system based on TI's TMS320F28335 chip, serving as the core component of the entire injection molding machine's pump-controlled servo system. The control system can perform real-time monitoring of state information such as pressure, position, temperature, and --- ## DSP+FPGA TMS320C665x + Xilinx Artix-7 High-Speed Data Acquisition and Processing Solution - URL: https://intl.sienovo.cn/blog/123142103 - Date: 2022-02-25 - Tags: #FPGADev, #DSP+FPGA To achieve real-time, high-speed acquisition and transmission of dynamic strain variables detected by Fiber Bragg Grating (FBG) sensors, a high-speed data acquisition system based on a DSP and FPGA architecture was designed. This system utilizes a Field-Programmable Gate Array (FPGA) as an auxiliary processor to perform high-speed data acquisition, store configuration programs, and power the development board. A Digital Signal Processor (DSP) is used as the main processor to achieve functions such as data processing and storage. High-speed transmission between the DSP and PC is then achieved via a control chip, displaying the final measured strain variables on the PC for easy analysis of the results. The overall functions, hardware circuit, and software design of the system are described. Experimental simulation analysis proves that this system can meet high-speed acquisition requirements and possesses good stability and real-time performance. To measure internal strain in large stru --- ## TI TMS320C665x + Xilinx Artix-7 DSP+ARM Inter-core Communication Solution - URL: https://intl.sienovo.cn/blog/123141480 - Date: 2022-02-25 - Tags: #FPGADev, #C665x ## Overview The Sienovo XM-C665xF-EVM is a high-performance DSP+FPGA evaluation board designed for applications that demand real-time, high-throughput data acquisition and signal processing. Built around TI's TMS320C665x KeyStone C66x DSP and a Xilinx Artix-7 XC7A100T FPGA, the platform targets demanding workloads including radar signal processing, remote radio unit (RRU) front-ends, high-end machine vision, and broadband audio/video analysis. This post walks through the board's architecture, interconnect topology, hardware specifications, software ecosystem, and typical use cases. ## Processor Architecture The TMS320C665x belongs to TI's KeyStone I architecture family. Depending on variant, it is available as a single-core C6655 (1.0/1.25 GHz) or dual-core C6657. Each C66x core is a fixed- and floating-point DSP capable of 40 GMAC/s and 20 GFLOP/s, making it well suited for FFT-heavy algorithms, FIR/IIR filter banks, and matrix operations typical in communications and imaging pipel --- ## Real-time Industrial Ethernet EtherCAT Master Implementation Based on AM5728 DSP+ARM+FPGA - URL: https://intl.sienovo.cn/blog/93245163 - Date: 2022-02-21 - Tags: #AM5728, #ETHERCAT, #Master, #IndustrialBus ## Real-time Industrial Ethernet EtherCAT Master Implementation Based on AM5728 DSP+ARM+FPGA EtherCAT (Ethernet for Control Automation Technology) is a widely adopted industrial Ethernet protocol that has gained popularity due to its high performance, flexibility, and scalability. In this article, we will explore the implementation of a real-time EtherCAT master using the AM5728 DSP+ARM+FPGA platform. ## Why EtherCAT? EtherCAT is a popular choice for industrial Ethernet applications due to its high performance, flexibility, and scalability. It was developed by Beckhoff in 2003 and is now managed by the EtherCAT Technology Group (ETG). EtherCAT is an open standard that allows devices to communicate with each other using a master-slave principle. This allows for fast and dynamic communication structures, making it an ideal choice for industrial automation applications. ## EtherCAT Master Implementation The EtherCAT master implementation is based on the AM5728 DSP+ARM+FPGA platform. --- ## CNC Machine Tool On-site Data Acquisition and Edge Computing Solution - URL: https://intl.sienovo.cn/blog/122900769 - Date: 2022-02-21 - Tags: #EdgeComputing, #AI With the introduction of the "Made in China 2025" strategy, "intelligence" has become the core keyword. Smart factories, smart manufacturing, and smart logistics are the directions for industrial development. CNC machine tools operate on the front lines of production, directly participating in processing, and are a crucial part of smart manufacturing. The demand for CNC machine tool equipment has significantly increased. Due to the wide product coverage and extensive after-sales service areas of machine tool manufacturers, equipment after-sales maintenance has become a major challenge: 1. Unable to ensure reliable and stable operation of equipment, reducing unnecessary downtime. 2. Inconsistent skill levels among equipment operators, meaning even minor issues might require on-site after-sales personnel, which reduces maintenance staff efficiency and increases maintenance costs. 3. Greater pressure on services: When equipment problems arise during production, manufacturers' customers a --- ## Open-Source EtherCAT Motion Control All-in-One Solution Based on AM5728 Linux - URL: https://intl.sienovo.cn/blog/117696723 - Date: 2022-02-21 - Tags: #AM5728, #LINUX, #OpenSource, #MotionControl, #DSP+ARM Sienovo EtherCAT master station with FPGA high real-time performance and encryption support for up to 32 axes ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/117696723/01_073c3c79f809e50a1cf62c33769a7f50.png) **Performance Advantages** 1. Faster cycle times, down to 31.25μs 2. Lower jitter, less than 0.004μs 3. Excellent synchronization: clock synchronization accuracy between master and slave devices can be far below 1μs (measured at 50ns for 4 axes) **Performance Comparison:** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/117696723/02_189d758fec4b5baf792b6af757282279.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/117696723/03_46a68ecebeac947c57b0ab2dfa34b24c.png) **Further Performance Comparison Summary:** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/117696723/04_422024ab63dd3fc67f7597d8fd4423f0.png) The XM5728-ETH bus controller integrates Gigabit Ethernet and USB 3.0 interfaces (supporting various industr --- ## TMS320C665x + Xilinx Artix7 DSP+FPGA High-Speed Core Board - URL: https://intl.sienovo.cn/blog/122909295 - Date: 2022-02-13 - Tags: #FPGADev, #C665x, #DSP+FPGA ## **1 Core Board Introduction** * Based on TI KeyStone C66x multi-core fixed-point/floating-point DSP TMS320C665x + Xilinx Artix-7 FPGA processor; * The TMS320C665x has a main frequency of 1.0G/1.25GHz, with single-core computing power up to 40G MACS and 20G FLOPS. The FPGA XC7A100T has 101K logic cells and 240 DSP Slices; * The TMS320C665x and FPGA are connected via communication interfaces such as uPP, EMIF, I2C, PCIe, and SRIO. Among these, PCIe and SRIO can achieve a maximum transmission speed of 5 GBaud per lane; * The FPGA acquisition card supports dual-channel 250MSPS*12Bit high-speed high-precision ADCs, and a single-channel 175MSPS*12Bit high-speed high-precision DAC, meeting various data acquisition requirements; * Supports Gigabit Ethernet, connectable to industrial network cameras, and also supports common interfaces such as I2C, SPI, UART, and McBSP; * Supports expansion modules such as CameraLink input/output and VGA output; * Supports bare-metal and SYS/ --- ## Cost-Effective, High Real-Time EtherCAT Fieldbus Industrial Motion Control Solution - URL: https://intl.sienovo.cn/blog/122850713 - Date: 2022-02-09 - Tags: #ethercat, #st32 In the past two months' weekends, I ported the SOEM master to STM32. It runs normally in free run mode and can drive Beckhoff I/O slaves. There are some bugs in DC mode, and it can only drive a portion of servo drives. I plan to document some of the porting process on my blog and share it with everyone. There will certainly be some inaccuracies, and I welcome your criticism and corrections. The entire porting process is actually similar to porting lwIP to STM32. The SOEM master was designed with a hardware abstraction layer and an operating system abstraction layer architecture, so it's sufficient to modify the code in the osal, oshw, and nicdrv sections. Of course, I referenced a lot of online resources during the porting process (not limited to the following). Here, I'd like to thank these experts. lwIP Porting: This part of the information referenced the STM32 tutorials from Atom and Wildfire, as well as the STM32 reference manuals. Just review the Ethernet-related sections. Re --- ## ZYNQ-Based WiFi Solution Implementation and Testing - URL: https://intl.sienovo.cn/blog/122849056 - Date: 2022-02-09 - Tags: #ZYNQ, #WIFI The Sienovo XM-ZYNQ7045-EVM is a software-defined radio (SDR) processing platform based on the Xilinx ZYNQ SoC. This platform uses a high-performance Xilinx ZYNQ series SoC, the XC7Z020, to enable transmission and reception of two channels of AD9361 wireless RF signals. It is widely used in applications such as SDR (software-defined radio), mobile base stations, WiFi, wireless LANs, and specialized or general-purpose wireless devices. The ZYNQ7000 is Xilinx's latest generation extensible processing platform. The ZYNQ SoC integrates a dual-core ARM Cortex-A9 processor, seamlessly combining FPGA programmability with ARM's multimedia and video interfaces, making it ideal for low-power, cost-sensitive signal processing products. High-speed HP interfaces enable data exchange between the PS (Processing System) and PL (Programmable Logic) domains. The PS side supports operating systems such as Linux and includes an embedded Gigabit Ethernet stack, simplifying TCP/IP-based Ethernet communi --- ## Zynq LTE Base Station Design and Implementation - URL: https://intl.sienovo.cn/blog/122848687 - Date: 2022-02-09 - Tags: #DSP+FPGA, #ZYNQ, #LTE Xilinx Zynq-7000 All Programmable SoC enables femtocell, picocell, microcell, and metrocell base station designs to reach new levels of integration, flexibility, and low power consumption. This article walks through why the Zynq-7000 architecture is well-suited to LTE small cell deployments, and uses the XM-ZYNQ7045-EVM evaluation board from Xinmai Technology (深圳信迈科技) as a concrete hardware reference to illustrate how the SoC maps onto a real product platform. ## Why Small Cells Demand a Different Silicon Strategy Small cells are low-power wireless base stations that operate within licensed spectrum under mobile network operator management. Coverage ranges from roughly 10 meters (femtocell, indoor residential) up to a few hundred meters (metrocell, urban outdoor). Because these nodes are often deployed at scale — mounted on lamp posts, inside offices, or on building facades — the design constraints are fundamentally different from a macro base station: - **No active cooling.** Most --- ## Design and Implementation of an Industrial Robot Control System Based on AM5728 DSP+ARM - URL: https://intl.sienovo.cn/blog/93139300 - Date: 2022-02-08 - Tags: #AM5728, #DSP+ARM, #IndustrialRobot, #IndustrialControl Industrial robot control systems often involve large-scale matrix computations and interface interactions. Traditional designs typically use an X86+FPGA system framework. With the development of embedded integration technology and SoC technology, high-performance multi-core controllers such as DSPs, ARMs, CPUs, and GPUs are rapidly expanding in the market due to their high cost-effectiveness. Given the outstanding performance of multi-core embedded systems in terms of integration, power consumption, and computing capability, this paper designs a hardware system based on the DSP+ARM dual-core SoC chip OMAPL138 and develops a complete industrial robot control system. This paper first briefly introduces the fundamentals of robot kinematics. Starting from traditional industrial robot control system models, and considering system development trends, computing capabilities, fault tolerance mechanisms, and motion indicators, an industrial robot control system architecture is proposed for har --- ## ZYNQ-based Data Storage and Real-time Imaging System - URL: https://intl.sienovo.cn/blog/122832903 - Date: 2022-02-08 - Tags: #ZYNQ, #ARM+FPGA, #ImageProcessing This article introduces a data storage and real-time imaging system, primarily addressing the issues of complex structure, long development cycles, and lack of portability in existing imaging systems. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122832903/01_ecb3c3932204e077ab5a69bd81a6d6e2.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122832903/02_c0f0bc76e36d236092a34e64f35adddc.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122832903/03_899c3e48afbd8c61b9ec4538fe4291de.png) ### **1 Evaluation Board Introduction** Xinmai Technology XM-ZYNQ7045-EVM is a high-end heterogeneous multi-core SoC evaluation board designed based on Xilinx Zynq-7000 series XC7Z045/XC7Z100 high-performance processors. The processor integrates a PS-side dual-core ARM Cortex-A9 + PL-side Kintex-7 architecture 28nm programmable logic resources. The evaluation board consists of a core board and an evaluation baseboard. The core board has undergone profes --- ## Design and Implementation of a ZYNQ+AD9361 Based Software-Defined Radio Platform - URL: https://intl.sienovo.cn/blog/122832172 - Date: 2022-02-08 - Tags: #ZYNQ, #ARM+FPGA, #AD9361 Software-Defined Radio (SDR) is a system and technology that uses a general-purpose hardware platform as its foundation and custom software as its core to implement various wireless communication system functionalities. Literally, the term "Software-Defined Radio" is not profound. "Radio" refers to communication technology that uses electromagnetic wave propagation in space to transmit and receive information; the original definition of "software" is a series of commands that control a computer system. Therefore, it can also be said that a Software-Defined Radio system is a computer system specifically designed for communication. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122832172/01_b1442e7f0e704479c453e184d0c87781.png) The AD9361 is a high-performance RF transceiver module manufactured by ADI, and it is also the industry's first highly integrated agile transceiver. Traditional RF modules are built from discrete components, which present numerous drawbacks in term --- ## Applications of the AM5728 DSP+ARM Platform in 5G Industrial Gateways, Industrial Data Acquisition, and Edge Computing - URL: https://intl.sienovo.cn/blog/105554838 - Date: 2022-02-08 - Tags: #AM5728, #EdgeComputing, #IndustrialControl, #IndustrialDAQ, #IndustrialGateway The convergence of billions of IoT devices and 5G networks is poised to profoundly transform how computing workloads are deployed. With the advent of 5G and the IoT era, along with the growing adoption of cloud computing, traditional cloud technologies can no longer meet the terminal-side demands for "massive connectivity, low latency, and high bandwidth." Edge computing has thus emerged as a critical solution. In fact, computing workloads have been shifting for years—first from on-premises data centers to the cloud, and now increasingly from cloud data centers to "edge" locations closer to data sources. This shift aims to minimize data transmission distance, thereby eliminating bandwidth and latency bottlenecks, ultimately improving application and service performance, reliability, and reducing operational costs. Edge computing effectively reduces system latency, decreases data transmission bandwidth, alleviates pressure on cloud computing centers, and enhances data security and pr --- ## MQTT Acquisition Protocol Converter to 103 104 cdt 61850 Environmental Monitoring Industrial Gateway, Customizable Trial - URL: https://intl.sienovo.cn/blog/122781065 - Date: 2022-02-04 - Tags: #IndustrialGateway Xinmai Technology Industrial Gateway supports various protocol conversions and different software/hardware configurations, offering customization. Hardware Configuration: AM335X/IMX6ULL/ST, etc. Software Configuration: Various protocol conversions, supporting IEC61850/IEC103/IEC104/Environmental Monitoring Protocol/1588 Synchronization Clock, etc. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122781065/01_3351eaac6f2c63862e533fae8e082785.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122781065/02_21db5df0478240b1ea148f5d4eb479ed.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122781065/03_9f8aeb84b1d7f8eeb8b4e31d2c55a7f2.jpeg) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122781065/04_2f6d88a0a13bad0511496eef4d45a7a4.jpeg)  ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122781065/05_2daf4a6edbc874b7648e73a13d24bbef.jpeg)  ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/122781065/06_c0 --- ## EtherCAT Master on FPGA AM5728: High Real-time with Encryption for 32 Axes - URL: https://intl.sienovo.cn/blog/122075444 - Date: 2021-12-21 - Tags: #FPGADev Real-time industrial motion control lives or dies on determinism. This post examines the Sienovo FPGA-based EtherCAT master running on the TI AM5728 SoC, covering its headline performance figures — 31.25 µs cycle time, sub-0.004 µs jitter, and 50 ns clock-sync accuracy across four axes — and explains why each of those numbers matters when you are coordinating 32 servo axes on a production line. ## Background: Why FPGA for EtherCAT? EtherCAT (Ethernet for Control Automation Technology) is an IEC 61158 fieldbus protocol designed around a master/slave topology where a single master node communicates with up to thousands of slave devices over standard Ethernet cabling. The protocol's key insight is that slave devices process frames *on the fly*, inserting or extracting data as a frame passes through rather than buffering the entire frame first. This makes latency predictable and extremely low — but it also means the master must be disciplined enough to send frames at exact, repeatable in --- ## Xinmai TMS320C6655 + Xilinx Artix-7 Evaluation Board: DSP+FPGA High-Speed Data Acquisition, Motion Control, Machine Vision Integrated Card - URL: https://intl.sienovo.cn/blog/121503934 - Date: 2021-11-23 - Tags: #SignalProcessing, #DSP+FPGA, #HighSpeedData The Xinmai XM665x-IDK-V3 development board and the Artix-7 development board communicate via a PCIe interface, realizing a DSP+FPGA communication architecture. 1. Processor The TI TMS320C665x is a high-performance fixed-point/floating-point DSP processor with a main frequency up to 1.0/1.25GHz, offering strong processing capabilities. The single-core TMS320C6655 and dual-core TMS320C6657 are pin-to-pin compatible and feature various industrial interface resources. Below is the functional block diagram of the TMS320C665x CPU: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/121503934/01_50ca38423b6fb37de521e8512ff85d2a.png) Cases: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/121503934/02_64e6c90c8c8689c8c6e9ae31eccbd5e1.jpeg) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/121503934/03_59677389b5f6a8d77447c45e8c3a831e.jpeg) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/121503934/04_e6cf909ea8cf87c1b4c86522682d93eb.png) ![]( --- ## XM6748F-IDK TMS320C6748+FPGA High-Speed Data Acquisition and Processing Platform - URL: https://intl.sienovo.cn/blog/121502446 - Date: 2021-11-23 - Tags: #MotionControl, #omapl138, #arm+fpga Supports 32-channel AD acquisition and 32-channel DA output. Supports multiple RS485 and RS232 serial ports; Supports real-time systems and control latency; Supports multi-core communication between DSP and ARM, providing rich sampling demos; Supports graphical interface programming, with touch control! 1. C6748+FPGA Development Board Introduction The XM6748F-IDK-V3, designed by Shenzhen Xinmai, is a DSP+FPGA high-speed data acquisition and processing development board, suitable for data acquisition and processing applications in power, communication, industrial control, medical, and audio/video fields. This design adopts the OMAP-L138+Spartan-6 platform, where OMAP-L138 is Texas Instruments' (TI) low-power, high-performance floating-point DSP C6748+ARM9 dual-core processor, and Spartan-6 is Xilinx's highly cost-effective FPGA processor with flexible platform upgrade capabilities. This design integrates the two chips via communication interfaces such as OMAP-L138's uPP and EMIF. --- ## OMAP-L138 FPGA Triple-Core High-Speed Data Acquisition and Processing Core Platform Solution - URL: https://intl.sienovo.cn/blog/121500572 - Date: 2021-11-23 - Tags: #OMPAL138, #FPGA, #CollisionAvoidanceRadar ## OMAP-L138 + FPGA Triple-Core High-Speed Data Acquisition Platform: XM138F-IDK-V3 Deep Dive The XM138F-IDK-V3 from Shenzhen Xinmai (Sienovo) is a DSP+ARM+FPGA triple-core development board built around TI's OMAP-L138 SoC and a Xilinx Spartan-6 FPGA. This article walks through the board's architecture, the rationale behind each chip selection, the inter-processor communication buses, and how the three cores divide signal-processing responsibilities — making it a useful reference for engineers evaluating the platform for power, communications, industrial control, medical instrumentation, or audio/video data acquisition work. --- ## Why Triple-Core? The Architectural Rationale Modern high-speed data acquisition systems face a three-way tension: raw signal throughput, deterministic real-time processing, and flexible application hosting. A single general-purpose CPU cannot serve all three well simultaneously. The XM138F-IDK-V3 resolves this by assigning each concern to a dedicated pr --- ## OMAPL138 + FPGA AD7606 Data Acquisition Test - URL: https://intl.sienovo.cn/blog/120321742 - Date: 2021-09-16 - Tags: #OMPAL138, #FPGA, #CollisionAvoidanceRadar The development board used for this test is the Sienovo OMAPL138+FPGA multi-core heterogeneous development board XM138F-IDK-V3. This program implements reading and writing to the AD7606 ADC chip using the EMIFA bus. The AD7606 is an 8-channel, 16-bit ADC chip with a 200K sampling rate. It supports parallel port/serial port read/write modes. The module defaults to parallel port mode, which allows a sampling rate of up to 200K. In SPI mode, the sampling rate is only about 100K. It is strongly recommended to use parallel port mode to fully utilize the synchronous sampling performance of the 8-channel AD7606. It supports bipolar signal input of ±10V or ±5V and is widely used in industries such as power and instrumentation. For more information, please refer to the Sienovo AD7606 Data Acquisition Module XM7606 datasheet. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/120321742/01_cafb453a22fd34ed3fabea42b6a49fbc.png) The input voltage range can be set to ±10V or ±5V by conf --- ## Design and Implementation of a Sound Source Localization System Based on the OMAP Platform - URL: https://intl.sienovo.cn/blog/120150818 - Date: 2021-09-07 - Tags: #matlab, #DSP, #SoundLocalization, #MicArray, #RealTime The primary objective of a sound source localization system is to determine the spatial position information of a sound source. Currently, most research achievements in sound source localization systems focus on sound source localization algorithms, with relatively less work on embedded system design and implementation. Therefore, this paper designs a sound source localization system based on the OMAP platform, utilizing sound source localization algorithms to achieve sound source localization on the system. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/120150818/01_5abfa410c9816a4ed7eacc81bf5e59a7.png) This paper first analyzes and compares three main methods for sound source localization based on microphone arrays, focusing on four primary algorithms for sound source localization based on time delay estimation. It then uses Matlab to simulate the Generalized Cross-Correlation (GCC) function algorithm for a planar four-element cross array. Next, this paper designs an --- ## Design and Implementation of a 48-Channel Data Acquisition System Based on OMAPL138 + FPGA - URL: https://intl.sienovo.cn/blog/119950305 - Date: 2021-08-27 - Tags: #stm32, #IoT, #AI In the current global situation, with the world's population continuing to grow and pressure on land resources and the environment increasing, the ocean has objectively become a global reserve resource base and a successor area for certain key strategic resources. To further explore the ocean, humanity has introduced digital signal and image processing technologies into the hydroacoustic field, leading to the creation of various new types of sonar arrays. This paper designs a data acquisition system based on the recording requirements for electro-acoustic signals converted from a 48-element sonar array. The content includes the overall scheme design, hardware circuit design, and software program design of the acquisition system. The data acquisition system uses an FPGA and an OMAP-L138 processor as its control core. After the core controller design was completed, six multi-channel high-precision analog-to-digital converter (ADC) chips were used to synchronously acquire electro-acoust --- ## Design of a Heterogeneous Multi-core Motion Controller Based on OMAPL138 + FPGA - URL: https://intl.sienovo.cn/blog/119950074 - Date: 2021-08-27 - Tags: #MotionControl, #omapl138, #arm+fpga Addressing the shortcomings of traditional motion controllers, such as poor stability, low control efficiency, and incomplete software architecture, and leveraging the advantages of heterogeneous multi-core technology, a heterogeneous multi-core processor motion controller is proposed and developed. This paper elaborates on the system's hardware and software design. The hardware design primarily describes a system architecture centered around the OMAPL138 heterogeneous multi-core processor, with FPGA serving as an extension. The software design utilizes different instruction set operating systems and employs SysLink to achieve multi-system platform communication. Considering the characteristics of motion controllers, a heterogeneous multi-core task scheduling strategy is proposed. The features of SysLink's Notify and ListMP components for heterogeneous multi-core communication are analyzed. The rules of the task scheduling strategy are encapsulated into the ListMP table header, and th --- ## 77GHz Automotive Anti-collision Radar Signal Processing Design and Implementation - URL: https://intl.sienovo.cn/blog/119914525 - Date: 2021-08-25 - Tags: #OMPAL138, #FPGA, #CollisionAvoidanceRadar, #SignalProcessing In recent years, automotive autonomous driving has received increasing attention. Millimeter-wave automotive radar is one of the key technologies for automotive autonomous driving, offering advantages such as stable performance, high measurement accuracy, and low cost. This paper focuses on the signal processing part of automotive anti-collision radar systems, including the construction of the signal processing platform and research on related algorithms for range and velocity measurement. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/119914525/01_d9369879c2c6a8135daa7d6bd719defa.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/119914525/02_f05dd3a503c3f7364c2a22d2af21423b.png) Firstly, the research background and current status of automotive anti-collision radar are outlined, and the basic principles and overall scheme of 77GHz automotive anti-collision radar are introduced. The communication design between the DSP board based on the OMAPL138 platfo --- ## OMAPL138+FPGA-based IF Data Acquisition and Storage System for Ship Automatic Identification System - URL: https://intl.sienovo.cn/blog/119912607 - Date: 2021-08-25 - Tags: #OMAPL138, #FPGA, #HighSpeedDAQ, #Marine The Automatic Identification System (AIS) is a digital navigation aid used at sea for collision avoidance and vessel identification, playing a significant role in maintaining maritime traffic safety. The position information for the AIS system is provided by the Global Navigation Satellite System (GNSS). To enhance the reliability of the AIS system, alternative positioning systems for GNSS, specifically land-based positioning systems, are currently being researched in the maritime domain. A ship autonomous positioning system based on AIS shore stations has been developed. During the research process of this system, to analyze and process real-time signal information from AIS and GNSS, it is necessary to acquire and store the intermediate frequency (IF) data of both AIS and GNSS. This facilitates the detection and evaluation of these signals and provides a large volume of raw data for future use, holding significant value in terms of practical application and research. ![](https://pub --- ## AM5728 Preempt-RT Igh EtherCAT Installation and Testing - URL: https://intl.sienovo.cn/blog/119392297 - Date: 2021-08-04 - Tags: #igh, #ethercat, #am5728, #RealTime, #Preempt-RT ## IgH EtherCAT Master Source Code Compilation and Installation [https://blog.csdn.net/scyhk/article/details/51672136](https://blog.csdn.net/scyhk/article/details/51672136) ## EtherCAT Series---IGH DC Mode Motor Test Program (Preempt-RT) [https://blog.csdn.net/weixin_40293570/article/details/108712655](https://blog.csdn.net/weixin_40293570/article/details/108712655) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/119392297/01_6b47befb60ec54054b047170d5652db2.png) Test data across various platforms: ## Porting and Testing of KPA EtherCAT Master on Zynq Platform [http://www.elecfans.com/d/973353.html](http://www.elecfans.com/d/973353.html) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/119392297/02_723464da26f82188af061f16b412e5b3.png) --- ## Implementing an SDR Software Defined Radio System Based on OMAP-L138 DSP+ARM Processor and FPGA - URL: https://intl.sienovo.cn/blog/118828381 - Date: 2021-07-16 - Tags: #OMAPL138, #FPGA, #SDR, #DSP+ARM A customer of Sienovo needed to develop a spread-spectrum radio transceiver for multiple applications. They had already developed modulation and demodulation algorithms but lacked the resources and hardware expertise to build a complete system around those algorithms. Rather than design custom silicon or a rigid hardware platform, they wanted the flexibility of a Software Defined Radio (SDR) architecture — one where signal-processing behaviour could be updated in software as the algorithms matured. This article describes how Sienovo implemented that system using Texas Instruments' OMAP-L138 DSP+ARM processor paired with an FPGA, covering platform selection, the critical data-transfer bottleneck, and the transmit and receive processing chains. ## Platform Selection Sienovo selected its **XM138F-IDK-V3** embedded system module as the SDR foundation. The module is built around TI's **OMAP-L138 DSP+ARM processor**, which integrates two heterogeneous cores on a single die: - A **456 MHz --- ## Hardware Design and Implementation of an SDR OMAP Platform for Underwater Acoustic Communication - URL: https://intl.sienovo.cn/blog/118784768 - Date: 2021-07-16 - Tags: #OMAPL138, #FPGA, #UnderwaterAcoustic, #SDR, #OMAP Underwater acoustic communication, as the only long-range wireless communication method underwater, is the primary means for achieving comprehensive underwater information sensing and interaction. However, the time delay, Doppler spread, and time-varying characteristics of underwater acoustic channels pose significant challenges for high-rate and high-reliability communication. Therefore, the research and development of high-speed underwater acoustic communication systems hold significant scientific and practical value. The fundamental idea of Software Defined Radio (SDR) technology is to use standardized hardware as a general-purpose platform to implement as many communication functions as possible through upgradeable and extensible software. Applying SDR technology to guide the top-level design of underwater acoustic communication systems can simplify the underlying hardware modules. At the same time, this reserves development interfaces for future software function upgrades of comm --- ## Design of a Three-Phase Power Quality Analyzer Based on OMAP-L138 + FPGA - URL: https://intl.sienovo.cn/blog/118784562 - Date: 2021-07-16 - Tags: #OMAPL138, #FPGA, #PowerQualityAnalyzer, #PowerElectronics With the rapid development of China's economy, electricity has become a vital energy source for people's lives and social production. The increasing variety of electrical equipment has led to numerous unbalanced and non-linear impact loads in the actual power grid, resulting in power quality issues such as supply voltage deviation, frequency deviation, harmonics, interharmonics, three-phase imbalance, voltage sags and swells, and inrush currents. These issues cause equipment malfunctions and economic losses. By strengthening power quality monitoring, users can take appropriate measures to avoid losses, making research into power quality parameter detection highly significant. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118784562/01_699668cac454ed7839d897f1557690b9.png) This paper analyzes the current research status of power quality parameter detection both domestically and internationally, with a particular focus on fundamental frequency, harmonic, and interharmoni --- ## Design and Application of a Multi-channel PWM Generator Based on OMAPL138+FPGA - URL: https://intl.sienovo.cn/blog/118784448 - Date: 2021-07-16 - Tags: #MultiPWM, #PowerElectronics, #OMPAL138, #FPGA To meet the triggering requirements of inverters in power electronic conversion devices for new energy generation, a multi-channel PWM pulse generator implemented using OMAPL138 and FPGA was developed. This pulse generator uses an interface unit to receive data such as PWM pulse duty cycle and configuration parameters written by the OMAPL138, and uses the FPGA to generate PWM waveforms, achieving operation independent of the OMAPL138. The hardware architecture, basic principles, and implementation methods of the pulse generator are also introduced, and validated through simulation and experiments. This PWM generator not only simplifies circuit design and improves system reliability but also ensures synchronous triggering of inverter power components. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118784448/01_76f21d845673e093e2d2d5f19c6a1b22.png) 1 Evaluation Board Introduction Based on TI OMAP-L138 (fixed-point/floating-point DSP C674x + ARM9) + Xilinx Spartan-6 FPGA --- ## Design and Implementation of a High-Precision BeiDou Receiver Based on C6748+FPGA - URL: https://intl.sienovo.cn/blog/118784301 - Date: 2021-07-16 - Tags: #C6748, #FPGA, #BeiDouReceiver, #HighPrecision With the advancement of computer technology, communication technology, and measurement and control technology, satellite navigation technology continues to progress, and its applications are becoming increasingly widespread, especially in military and civilian fields. It is gradually becoming an important benchmark for measuring a nation's military strength and scientific and technological level. China began constructing its BeiDou Satellite Navigation System in the mid-1990s. As of March 30, 2016, China had successfully launched its 22nd BeiDou navigation satellite, and BeiDou had achieved service capability in the Asia-Pacific region, also indicating the continuous improvement and development of Global Navigation Satellite Systems (GNSS). ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118784301/01_3438c34b6ef3cd78b506dc59590d5193.png) Global Navigation Satellite System receivers are an extremely important part of navigation systems. With the application of large-scal --- ## Design of a Wireless Digital Remote Blasting System for Seismic Exploration Based on OMAPL138+FPGA - URL: https://intl.sienovo.cn/blog/118756791 - Date: 2021-07-15 - Tags: #OMAPL138, #FPGA, #WirelessRemote, #SeismicSurvey Seismic exploration technology is one of the effective geophysical exploration techniques in the energy exploration field, widely applied in oil and gas resource exploration. With the rapid development of the global economy, energy demand is increasing, making the update and development of exploration technologies and equipment a top priority in energy exploration. As a critical component in seismic exploration systems, the performance of the remote blasting subsystem significantly impacts the overall performance of the seismic exploration system. Therefore, to meet the demand for domestic production of key seismic exploration equipment, independently designing a seismic exploration remote blasting subsystem is imperative. This paper, based on an enterprise-level project, completes the software design and development for a digital remote blasting subsystem, summarized as follows: 1. Based on the design objectives of the remote blasting subsystem and its hardware platform, the overall --- ## Design of Distributed Fiber Optic Sensor System Based on OMAPL138 + FPGA - URL: https://intl.sienovo.cn/blog/118756705 - Date: 2021-07-15 - Tags: #OMAPL138, #FiberSensor, #FPGA, #Distributed Distributed fiber optic sensors are widely used in various fields due to their advantages such as low cost, high precision, corrosion resistance, and long sensing distance. Based on the principle of Brillouin scattering and using an embedded device as the hardware development platform, a distributed fiber optic sensor software system has been designed and developed. Compared to traditional fiber optic sensing systems, distributed fiber optic sensors based on Brillouin scattering can monitor temperature and strain information of the measured environment, while sensing systems developed on embedded platforms offer advantages including low cost, high performance, and good stability. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118756705/01_7009d209377fd789857373129b76b748.png) The fiber optic sensing system adopts a C/S architecture, with the design focus on the development and design of the server-side software system. The server-side software system is developed on an --- ## Ximai AM5728 Development Board USB3.0 Industrial Camera Development - URL: https://intl.sienovo.cn/blog/118583174 - Date: 2021-07-08 - Tags: #ComputerVision, #opencv, #qt, #Embedded #### **3.2** **OpenCv+OpenCL+OpenGL Demo Program Test** Connect the accompanying USB camera module to the USB 3.0 port of the AM57x development board. Connect an HDMI display to the development board's HDMI port. Disconnect the LCD display from the development board, otherwise it will affect HDMI display output. Connect a mouse to the development board's USB 2.0 port. Power on the development board. After entering the development board system, move the mouse and click the "Video Analytics Demo" icon on the desktop to enter the following interface: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118583174/01_8b85634dd25e931267863d235692f438.png) Figure 8 After clicking the "OpenCv+OpenCL+OpenGL Demo" icon, click RUN to execute the program. In the pop-up interface, click "Connect to Camera" to set the resolution. For this demo, the default resolution "640*480" is sufficient, but users can modify it according to the actual camera parameters. ![](https://pub-048dcb96257f --- ## 基于AM5728的PROFIBUS 通信测试 - URL: https://intl.sienovo.cn/blog/118487522 - Date: 2021-07-05 - Tags: #AM5728, #PROFIBUS, #IndustrialBus --- Title: PROFIBUS Communication Testing Based on AM5728 Content: **PROFIBUS Communication Testing** #### **Ø 1. Hardware Connection** Connect the debug serial ports of two XM5728-IDK-V3 development boards to the PC using Micro USB cables, and open the serial debugging windows. Use jumper wires to connect the PROFIBUS interfaces of the two XM5728-IDK-V3 boards: connect A to A, B to B, and GND to GND. Ensure the terminal blocks are removed before connecting, as poor terminal contact previously caused signal transmission issues. For hot-plug testing, cut one wire (e.g., the A wire) in the middle and manually connect/disconnect it instead of doing so at the terminal blocks (which may cause problems). **Wire connection inspection is critical.** Insert the prepared master/slave SD boot cards into the respective SD card slots of the XM5728-IDK-V3 boards. Power both boards using 12V-2A DC power supplies. #### **Ø 2. Communication Testing** First, power on the XM5728-IDK- --- ## Xinming AM5728 CAN Bus Test Method - URL: https://intl.sienovo.cn/blog/118487400 - Date: 2021-07-05 - Tags: #AM5728, #CAN, #DSP, #ARM, #BusTesting ****CAN Bus Test Method**** On the development board's file system, execute the following commands to configure CAN0 bus (the software CAN0 corresponds to hardware CAN1) with a bit rate of 1 Mbps, and start the CAN bus: Target# canconfig can0 bitrate 1000000 Target# canconfig can0 start Execute the following command to monitor data received from the PC side: Target# candump can0 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118487400/01_d1fde3a2dbfc540fd51da430b687b1f4.png) Driver is automatically installed on the PC ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118487400/02_b2546232f7325064aae068731f024ee3.png) Then launch the debugging instrument software ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118487400/03_68eeb82c277e1746b5de9d495a302c02.png) I. First, set the COM port with a bit rate of 1 Mbps, II. Select any data and click Send or enable cyclic transmission ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blo --- ## High-Performance and High-Stability Medical Test Analyzer System Based on AM5728 - URL: https://intl.sienovo.cn/blog/118410817 - Date: 2021-07-02 - Tags: #AM5728, #DSP, #ARM, #MedicalAnalyzer, #MedicalTester ## Deploying the AM5728 as the Control Core of a Clinical Chemistry Analyzer Medical test analyzers — hematology counters, immunoassay platforms, clinical chemistry analyzers — sit at the intersection of two demanding worlds: the real-time determinism required to orchestrate dozens of synchronized mechanical axes, and the high-level software sophistication needed to present results clearly to clinical staff. Getting both right on a single platform is the central hardware challenge. This case study describes how Sienovo's AM5728 compute module was selected as the core engine for a high-throughput laboratory analyzer, and why that choice addresses the three customer pain points of fast sample delivery, responsive technical support, and uncompromising long-term stability. ## Why the AM5728 Fits Medical Analyzer Architecture The TI Sitara AM5728 is a heterogeneous SoC that combines dual ARM Cortex-A15 application cores running at up to 1.5 GHz with dual TMS320C66x DSP cores, an integrat --- ## Design of a Portable Equipment Condition Monitoring and Diagnostic Instrument Based on OMAP-L138 - URL: https://intl.sienovo.cn/blog/118176742 - Date: 2021-06-24 - Tags: #OMAPL138, #DiagnosticInstrument, #OnlineMonitoring, #DataAcquisition, #DSP The OMAP-L138 processor combines the strengths of both DSP and ARM cores — the DSP handles real-time signal processing while the ARM manages the operating system, graphical interface, waveform display, and peripheral control. Inter-core communication is handled through the DSP/BIOS bridge (DSP/Link), making it an attractive platform for industrial instruments that must simultaneously perform complex signal analysis and present results through a responsive UI. This article walks through the hardware and software design of a portable, dual-channel equipment condition monitoring and diagnostic instrument built around this processor, targeting the predictive-maintenance needs of petrochemical facilities. ## Why OMAP-L138 for Industrial Diagnostics Industrial condition monitoring instruments face a fundamental tension: they need enough computational horsepower to run FFT, shaft-orbit, and dynamic-balancing algorithms in real time, yet they must remain battery-friendly and handheld. The TI --- ## Power Data Acquisition and Transmission Design Based on OMAPL138 + Xilinx Spartan-6 - URL: https://intl.sienovo.cn/blog/118175736 - Date: 2021-06-24 - Tags: #OMAPL138, #C6748, #DSP, #SPARTAN6, #DataAcquisition **Ma Shixi and Yang Han, researchers from Wuhan Fiberhome Furi Electric Co., Ltd., presented in the 10th issue of "Electrical Engineering" magazine in 2015 a power data acquisition and transmission design based on OMAPL138. This solution is built upon Sienovo's OMAPL138+SPARTAN6 development board, with the OMAPL138 microprocessor at its core. The microprocessor analyzes and processes acquired data such as voltage, current, and digital inputs, then transmits the processed data to upper-level host systems via interfaces like RS485/RS232 and Ethernet using various communication protocols. The article details the functions of each module, hardware design, and software design flow. This design is flexible, convenient, and offers significant practical value.** ### **1 Evaluation Board Overview** * Based on TI OMAP-L138 (fixed/floating-point DSP C674x + ARM9) + Xilinx Spartan-6 FPGA processor; * OMAP-L138 and FPGA are connected via uPP, EMIFA, and I2C buses, supporting communication spe --- ## Xinming TI OMAP-L138 (Fixed/Floating-Point DSP C674x + ARM9) + Xilinx Spartan-6 FPGA Development Board Specification - URL: https://intl.sienovo.cn/blog/118175339 - Date: 2021-06-24 - Tags: #OMAPL138, #C6748, #DSP+ARM, #SPARTAN6, #DataAcquisition ### **1 Evaluation Board Introduction** * Based on the TI OMAP-L138 (fixed/floating-point DSP C674x + ARM9) + Xilinx Spartan-6 FPGA processor; * OMAP-L138 and FPGA are connected via uPP, EMIFA, and I2C buses, supporting communication speeds up to 228 MByte/s; OMAP-L138 runs at 456 MHz with computing performance up to 3648 MIPS and 2746 MFLOPS; * FPGA compatible with Xilinx Spartan-6 XC6SLX9/16/25/45, offering strong platform scalability; * The development board exposes abundant peripherals, including Gigabit Ethernet, SATA, EMIFA, uPP, USB 2.0, and other high-speed data interfaces, as well as common interfaces such as GPIO, I2C, RS232, PWM, and McBSP; * Passed high and low temperature testing, suitable for harsh operating environments; * DSP + ARM + FPGA tri-core SOM (System-on-Module), dimensions 66mm × 38.6mm, using industrial-grade B2B connectors to ensure signal integrity; Ø * Supports bare-metal, SYS/BIOS, and Linux operating systems. ![](https://pub-048dcb96257f47 --- ## OMAPL138 + SPARTAN6 DSP+ARM+FPGA Development Examples - URL: https://intl.sienovo.cn/blog/118159455 - Date: 2021-06-23 - Tags: #C6748, #DSP, #DevExamples, #tcp, #OMAPL138 **Table of Contents** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118159455/01_1b93ff3ab3a4426705fd019e883fcf25.png) This example is developed based on the Xinmai OMAPL138+SPARTAN6 evaluation board. 1.   [Development Board Preparation 16](#_bookmark0) 1. [Check Emulator Driver Installation 17](#_bookmark1) 2. [Program Loading and Flashing 19](#_bookmark2) 1. [Program Loading and Flashing via Emulator 19](#_bookmark3) 1. [Configure Project Profile Information 19](#_bookmark4) 2. [Test Emulator Connection 20](#_bookmark5) 3. [Load GEL File 21](#_bookmark6) 4. [CCS Connects to Development Board CPU 22](#_bookmark7) 5. [Check CPU Version Number 23](#_bookmark8) 6. [Load File Flashing Program 24](#_bookmark9) 7. [Flash Program to NAND FLASH via Emulator 24](#_bookmark10) 8. [NAND FLASH Flashing Image Conversion Method 29](#_bookmark11) 2. [Program Loading and Flashing via Serial Por --- ## C6748/OMAPL138 Network Web Server/Socket Example Development - URL: https://intl.sienovo.cn/blog/118159316 - Date: 2021-06-23 - Tags: #C6748, #OMAPL138, #DSP, #Networking, #socket 1. This example is based on the Xinmai XM138F-IDK-V3 development board. 1. ******ENET\_HTTPD********——Network**** ****Web**** ****Server****** This program implements network communication functionality, setting up a lightweight Web server on the development board. Connect the network cable. Load the ENET\_HTTPD.out file according to the project import steps, then click the program run button. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118159316/01_1b93ff3ab3a4426705fd019e883fcf25.png) ****Demonstration Phenomena**** (1) The serial port displays the development board's IP address (169.254.3.5). ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/118159316/02_119c55ddd04ace88930ad9542e850cca.png) Figure 219 1. Enter `cmd` at the bottom of the Windows Start menu to open the console window, then execute the `ping` command to confirm that the development board's network is working correctly. **DOS#** ping 169.254.3.5 ![](https://pub-048dcb96257f --- ## Research and Implementation of a Reactive Power Compensation System Structure for a Static Synchronous Compensator Based on OMAPL138+FPGA - URL: https://intl.sienovo.cn/blog/118016020 - Date: 2021-06-18 - Tags: #OMAPL138, #FPGA, #STATCOM, #PowerMonitoring, #DataAcquisition The increasing variety of nonlinear devices in power systems impacts the power supply, leading to significant fluctuations in supply voltage amplitude, reduced power factor, and increased harmonic distortion in the public grid. Simultaneously, with the rapid development of computer technology and precision control, user demands for power quality are also rising. This energy contradiction has accelerated the theoretical research and engineering application of reactive power compensation technology in power systems. Thanks to the comprehensive improvement in switching device performance, the regulation effect of reactive power compensation devices has become increasingly outstanding. Compared with similar reactive power compensation devices, Static Synchronous Compensator (STATCOM) systems offer advantages such as low harmonics, a wide dynamic adjustment range, and high reliability. Therefore, research into STATCOM control systems, as presented in this paper, holds significant value. Th --- ## Impressions from Testing the C6748 + SPARTAN6 Core Board and Evaluation Board - URL: https://intl.sienovo.cn/blog/117928108 - Date: 2021-06-15 - Tags: #C6748, #SPARTAN-6, #DSP+FPGA, #SoM, #EvaluationBoard Last week, I acquired the C6748 + SPARTAN6 development board from Sienovo. My first impression was that the core board is incredibly compact—about the size of a coin. It uses three DC-DC converters for power, resulting in low power consumption, and all chips are industrial-grade, making it highly suitable for our power monitoring equipment. One notable feature is that the board includes EMC and ESD protection, eliminating concerns about electromagnetic interference in power systems. After spending a week experimenting with the example programs they provided, I found the Qt integration particularly impressive. Here are a few photos I found online for reference. ### **1. Evaluation Board Overview** * Based on the TI TMS320C6748 fixed-point/floating-point DSP C674x and Xilinx Spartan-6 FPGA processor; Ø DSP and FPGA are connected via uPP, EMIFA, and I2C buses, supporting communication speeds up to 228 MByte/s; Ø DSP clocked at 456 MHz, delivering up to 3648 MIPS and 274 --- ## IoT Gateway Solution Based on AM335X - URL: https://intl.sienovo.cn/blog/117905932 - Date: 2021-06-14 - Tags: #AM335X, #IoTGateway, #CostEffective IoT Gateway Solution Based on AM335X * **Background Analysis** Industrial Internet of Things (IIoT) refers to IoT applications in industrial fields and represents the deep integration of industrial automation and information technology. Compared to general IoT, IIoT has stricter requirements, such as ultra-low latency, high reliability, and strong information security. A typical IIoT architecture consists of four layers: perception, network, platform, and application. These layers are embodied in intelligent industrial devices, sensors, cloud platforms, smart control devices, gateways, and edge computing systems. Among these components, industrial IoT gateways and cloud platforms play foundational roles, closely tied to the characteristics of IIoT—such as performance, reliability, and information security requirements. Additionally, the gateway's unique topological position makes it ideal for integration with edge computing. ****Pain Points Analysis:**** 1. Poor scalability—any --- ## Design and Implementation of an OMAPL138+FPGA-based RF Direct Sampling Weather Facsimile Receiver - URL: https://intl.sienovo.cn/blog/117786093 - Date: 2021-06-10 - Tags: #OMAPL138, #FPGA, #RF, #Receiver, #Transmitter Weather facsimile signals cover most of the world's oceans. By receiving weather charts via a weather facsimile receiver, ships in the open ocean can timely predict dangerous factors such as typhoons and high waves that threaten navigation safety, allowing them to plan or alter their routes accordingly. The weather information received by facsimile machines is of significant importance for the safety and route selection of ships. Most weather facsimile machines currently in use employ a superheterodyne architecture, which involves complex analog signal processing, makes fault detection difficult, and has low digital integration. Addressing the pros and cons of existing receiver structures, this paper proposes a design for an RF direct sampling weather facsimile receiver based on software-defined radio principles. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/117786093/01_165a5cbc4bb950af7689f26d2f29ea06.jpeg) With this solution, RF signals are directly digitized after --- ## In Vitro Diagnostic Solution Based on AM5728 - URL: https://intl.sienovo.cn/blog/117768138 - Date: 2021-06-10 - Tags: #AM5728, #DSP, #ARM, #IVD In vitro diagnostic methods enable rapid and accurate diagnosis at early stages of diseases, playing a crucial role in clinical medicine and related fields, and have experienced rapid growth in the global healthcare market. ZLG provides tailored solutions for commonly used equipment in the in vitro diagnostics industry, continuously collaborating with renowned medical device manufacturers to launch a series of intelligent in vitro diagnostic devices that align with healthcare professionals' operational habits. #### Semi-Automatic Biochemical Analyzer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/117768138/01_314616ac46f97e0404d53c52fb58dc81.png) A biochemical analyzer is a device that uses photoelectric colorimetry to measure specific chemical components in body fluids. It automates key steps in medical analysis such as sampling, reagent addition, incubation, reaction, detection, and result calculation. It features fast measurement speed, high accuracy, and low reagen --- ## AM5728 Evaluation Board – Dual-Core Cortex-A15, Up to 1.5GHz per Core - URL: https://intl.sienovo.cn/blog/117715975 - Date: 2021-06-08 - Tags: #AM5728, #SoM, #EvaluationBoard, #DualARM, #DualDSP 1. Core Board Introduction ➢ SOM-XM5728 is an industrial-grade core board developed by Sienovo based on the TI AM5728 processor. It features an ENIG (Electroless Nickel Immersion Gold) lead-free design, a 10-layer PCB, and industrial-grade reliability, making it suitable for applications such as motion control systems, machine vision processing, image recognition, audio analysis, video analytics, and high-end measurement instruments. Customers can choose different CPU, memory, and storage configurations depending on their specific application requirements. The core board is built around the TI AM5728 processor, integrating dual ARM Cortex-A15 cores and dual C66x™ Floating-Point VLIW DSPs running at 750MHz, along with PRU-ICSS modules supporting multiple industrial protocols. It supports industrial-grade DDR3 memory ranging from 1GB to 4GB and eMMC flash storage from 4GB to 16GB, enabling flexible and convenient expansion. The SOM-XM5728 supports industrial communication protocols in --- ## AM5728 Industrial PC and Industrial Panel Motion Control Solution - URL: https://intl.sienovo.cn/blog/117715690 - Date: 2021-06-08 - Tags: #AM5728, #IndustrialTablet, #IndustrialTouchscreen, #DSP, #ARM 1. **Product Introduction** ➢ SOM572x is an industrial-grade core board from Sienovo (XMTECH) based on the TI AM5728 processor. It features immersion gold lead-free technology, a ten-layer board design, and industrial-grade specifications. It can be applied in motion control systems, machine vision processing systems, image recognition systems, audio analysis systems, video analysis systems, high-end measurement instruments, and other industrial applications. * Customers can choose different CPU, memory, and external storage configurations based on their specific applications. The core board supports the TI AM5728 processor, which includes two ARM Cortex-A15 processors and two floating-point DSP C66x™ Floating-Point VLIW DSPs @ 750MHz, along with PRU-ICSS supporting various industrial protocols. Memory supports industrial-grade 1GB-4GB DDR3, and external storage supports industrial-grade 4GB-16GB eMMC, offering highly convenient expansion. * The SOM572x core board supports v --- ## Design and Implementation of a Power Quality Analyzer Based on C6748 DSP+FPGA - URL: https://intl.sienovo.cn/blog/117655595 - Date: 2021-06-07 - Tags: #C6748, #SPARTAN6, #PowerQuality, #HarmonicDetection With the large-scale grid integration of clean energy and the widespread application of power electronic components, the power quality of public grids faces increasingly severe challenges. At the same time, the intelligent development of industrial production and social life makes more power system loads sensitive to power quality, thus users have significantly increased their attention to and pursuit of power quality. As support and basis for addressing power quality issues, the importance of power quality detection and analysis has greatly increased. Implementing power quality detection and analysis on embedded systems also lays a solid foundation for the development of intelligent power meters. This paper investigates the measurement methods of power quality parameters, the feature extraction and classification of power quality disturbance signals, and implements relevant algorithms for parameter measurement and disturbance classification on a Digital Signal Processor (DSP). The sp --- ## Online Monitoring System for Power Parallel Capacitor Equipment Based on OMAPL138 DSP+ARM - URL: https://intl.sienovo.cn/blog/117649926 - Date: 2021-06-07 - Tags: #OMAPL138, #C6748, #HarmonicDetection, #OnlineMonitoring, #FaultDiagnosis Parallel capacitor equipment is a widely used reactive power compensation device in power transmission and distribution systems, effectively improving system power factor and increasing equipment utilization. However, high-voltage parallel capacitors operate under full load with large rated currents, making them prone to aging of capacitor elements after prolonged operation, which can lead to capacitor damage and significant changes in capacitance values. This article aims to develop an online monitoring system for capacitor equipment that effectively monitors the operational status of power capacitors and enables analysis and localization of fault causes when failures occur. The principle of the online monitoring system involves conditioning AC voltage and current signals, which are then connected to an A/D sampling board for isochronous sampling. The sampled sequences are synchronized using a shift linear interpolation algorithm. Subsequently, FFT algorithms from digital signal proc --- ## ADCP Signal Processing System Based on C6748 DSP + FPGA Acoustic Doppler Current Profiler - URL: https://intl.sienovo.cn/blog/117649189 - Date: 2021-06-07 - Tags: #C6748, #FPGA, #DSP+FPGA+ARM, #Power The Acoustic Doppler Current Profiler (ADCP) is a device that measures flow velocities at different depths across a water column by utilizing the Doppler effect of ultrasonic signals and ultrasonic ranging principles. It is widely used in ocean current observation and river discharge measurement. Currently, digital ADCP technology is relatively mature overseas, while there are no commercially available products in China yet. Therefore, it is essential to develop China's own ADCP technology and products. Due to limitations in processor computational performance and power consumption, traditional ADCP algorithms and systems were primarily implemented using analog circuits. With improvements in DSP processing capabilities and in ADC resolution and sampling rates, there is a growing preference to perform signal processing as much as possible in the digital domain. This approach simplifies the analog front-end complexity and enhances the system's versatility, flexibility, and stability. Aft --- ## Research on LFMCW Radar Signal Processing Algorithms Based on C6748 DSP + FPGA - URL: https://intl.sienovo.cn/blog/117547568 - Date: 2021-06-04 - Tags: #C6748, #FPGA, #SPARTAN6, #Radar, #mmWave With the rapid development of China's economy and the continuous improvement of living standards, automobile usage has become increasingly widespread. However, while cars bring convenience and efficiency to daily life, the frequency of traffic accidents has also risen, posing serious threats to personal safety and property, as well as creating significant risks to social stability. In recent years, with advancements in front-end Monolithic Microwave Integrated Circuits (MMIC) and millimeter-wave devices, millimeter-wave radar technology has matured significantly. Millimeter-wave radars are now installed not only in high-end and mid-range vehicles but also in many entry-level compact cars, greatly promoting the development of smart cities and autonomous driving technologies. This paper introduces the fundamental characteristics of millimeter-wave radar and, based on the Linear Frequency Modulated Continuous Wave (LFMCW) system, analyzes and compares three millimeter-wave radar signal p --- ## Design and Application of a Software Radio Platform Based on C6748 DSP and FPGA - URL: https://intl.sienovo.cn/blog/117536046 - Date: 2021-06-03 - Tags: #C6748, #OMAPL138, #DSP, #FPGA, #SDR This article presents a software-defined radio (SDR) platform based on DSP, FPGA, and ASIC technologies. On this experimental platform, the baseband and intermediate frequency (IF) designs of an OFDM system have been implemented and practically verified. The system operates stably and effectively supports multiple communication modes, making it a widely applicable SDR platform. Current research focuses on baseband predistortion techniques for power amplifiers to further enhance system performance. 1. Evaluation Board Overview * Features a TI OMAP-L138 processor (fixed/floating-point DSP C674x + ARM9) combined with a Xilinx Spartan-6 FPGA; * The OMAP-L138 and FPGA are interconnected via uPP, EMIFA, and I2C buses, supporting communication speeds up to 228 MByte/s; the OMAP-L138 runs at a 456 MHz main frequency, delivering up to 3648 MIPS and 2746 MFLOPS computing performance; * FPGA compatible with Xilinx Spartan-6 models XC6SLX9/16/25/45, enabling strong platform scalability; * --- ## Target Detection Method and Platform Design for C6748 + FPGA Based Angle and Range Measurement Continuous Wave Radar - URL: https://intl.sienovo.cn/blog/117535952 - Date: 2021-06-03 - Tags: #C6748, #FPGA, #DSP+FPGA, #Radar, #Navigation Frequency Modulated Continuous Wave (FMCW) radar offers advantages such as low cost, large time-bandwidth product, high signal energy, strong anti-clutter capability, and portability. It plays a significant role in specialized measurement, detection, and security applications. Among the various technologies in continuous wave radar, improving measurement accuracy and detection probability is crucial, making in-depth research in these two areas highly significant. The main work of this paper includes: 1. Introducing the specific flowchart and working principle of sawtooth wave FMCW radar, deriving the principles of range, velocity, and angle measurement, and discussing the range-velocity coupling and decoupling problems in sawtooth wave FMCW radar; analyzing range resolution and velocity resolution. 2. Designing an intermediate frequency hardware platform for sawtooth wave FMCW radar based on an FPGA+DSP framework, fully leveraging the parallel logic capabilities of FPGA and the comput --- ## Modular Design and Implementation of a C6748 DSP+FPGA MIMO Radar Verification System - URL: https://intl.sienovo.cn/blog/117535718 - Date: 2021-06-03 - Tags: none Unlike traditional radar, MIMO radar has attracted significant research interest in recent years due to its unique advantages. The key benefit of MIMO radar lies in its ability to achieve high angular resolution without being constrained by antenna size. This paper presents the design of a MIMO radar verification system that overcomes the drawbacks of conventional MIMO radar systems, such as large size and long processing time, enabling efficient target localization and imaging. The paper begins with an introduction to the fundamentals of MIMO radar, followed by the design of a modular MIMO radar verification system composed of three main components: a radar signal generator module, a signal processing platform module, and a signal transceiver module. Each module can be independently replaced and tuned according to experimental requirements. Subsequently, the tasks and functions of these three modules within the radar system are described in detail. Based on the method of MIMO radar --- ## Design of an Embedded Spray Painting Robot Controller Based on OMAPL138 + FPGA - URL: https://intl.sienovo.cn/blog/117449491 - Date: 2021-06-01 - Tags: #C6748, #OMAPL138, #SPARTAN6, #FPGA, #DSP Spray painting is currently one of the most widely used coating methods in many industries. With the development of computer numerical control technology in an increasing number of industries, robotic spray painting has become an increasingly prevalent trend in modern spray painting operations. Foreign robotic spray painting technology is relatively mature, with research dating back to the 1960s. The current spray painting robot market is still dominated by foreign robot brands, such as KUKA from Germany, ABB from Sweden, and FANUC and MOTOMAN from Japan. In contrast, domestic research on spray painting robots started later, and the technology is relatively backward compared to foreign counterparts. Currently, domestic manufacturers do not yet possess the capability to independently produce spray painting robots in a complete sense. Addressing the domestic market demand for the robotic spray painting industry, and based on the current level of domestic spray painting robot development --- ## Design of a 77GHz Automotive Anti-Collision Radar Signal Processing Platform Based on OMAPL138/C6748 + SPARTAN-6 - URL: https://intl.sienovo.cn/blog/117449374 - Date: 2021-06-01 - Tags: #omapl138, #c6748, #dsp, #fpga, #Radar In recent years, automotive autonomous driving has garnered increasing attention. Millimeter-wave automotive radar is one of the key technologies for autonomous driving, offering advantages such as stable performance, high measurement accuracy, and low cost. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/117449374/01_251ecdd94efc7ab2fe71b32717936a5c.png) This paper investigates the communication design between the DSP board based on the OMAPL138 platform and the millimeter-wave front-end, as well as the communication methods between OMAPL138 and HMC703, AD8285, AD8334, and a gyroscope. It introduces the principles of ranging, velocity measurement, and angle measurement for frequency-modulated continuous wave (FMCW) radar, and provides MATLAB and Code Composer Studio simulation implementations of the radar algorithm. The final algorithm implementation runs correctly on OMAPL138 and has been tested to provide high accuracy. ![](https://pub-048dcb96257f476697b113fcb5939c --- ## High-Speed Data Acquisition and Storage System Based on OMAPL138/C6748 + SPARTAN6 - URL: https://intl.sienovo.cn/blog/117449179 - Date: 2021-06-01 - Tags: #omapl138, #fpga, #spartan6, #ad7606 ## Are these problems in data acquisition/production processing giving you a headache?! * Unable to know equipment status in time, and historical records cannot be queried! * Unable to know equipment operating conditions and load! * Equipment utilization and efficiency are unknown! * Tool life and tool management issues are unclear! * Production line data and production progress information cannot be obtained! * Production data and production progress information cannot be obtained! * The production site is not transparent, statistical charts are lacking, and management is extremely difficult! The Automatic Identification System (AIS) is a digital navigation aid system used at sea for collision avoidance and vessel identification, playing a huge role in maintaining maritime traffic safety. The position information of the AIS system is provided by the Global Navigation Satellite System (GNSS). To improve the reliability of the AIS system, a land-based positioning system --- ## OMAPL138 Power/HDMI/Camera/UART/LCD Schematics Sharing - URL: https://intl.sienovo.cn/blog/117070872 - Date: 2021-05-20 - Tags: #OMAPL138, #Camera, #LCD, #AD7606 ## OMAPL138 Power/HDMI/Camera/UART/LCD Schematics Sharing The OMAPL138 is a System-on-Chip (SoC) designed by Texas Instruments, featuring a dual-core ARM Cortex-A8 processor, along with various peripherals such as HDMI, camera, UART, and LCD interfaces. In this article, we will explore the schematics of the OMAPL138, focusing on its power, HDMI, camera, UART, and LCD interfaces. ### Schematics Overview The OMAPL138 schematics can be broken down into several key components: * Power management: The OMAPL138 features a power management unit (PMU) that regulates power to various peripherals and the processor core. * HDMI interface: The OMAPL138 supports HDMI 1.3a with a maximum resolution of 1080p at 60Hz. * Camera interface: The OMAPL138 features a camera interface that supports up to 12-bit RAW image capture. * UART interface: The OMAPL138 has four UART interfaces, each supporting up to 3 Mbps data transfer rate. * LCD interface: The OMAPL138 supports LCD interfaces with a maximum re --- ## 基于AM5728的OpenCL例程开发分享 - URL: https://intl.sienovo.cn/blog/116897118 - Date: 2021-05-16 - Tags: #AM5728, #OPENCL, #OPENCV, #OPENMP, #MulticoreHeterogeneous --- Title: OpenCL Example Development Guide Based on AM5728 Content: ### **User Manual for OpenCL Examples Based on AM57x** ### **1 Introduction to OpenCL** OpenCL (short for Open Computing Language) is the first open, royalty-free standard for general-purpose parallel programming across heterogeneous systems. It provides a unified programming environment that enables software developers to write efficient and portable code for high-performance computing servers, desktop systems, and handheld devices. OpenCL is widely applicable to various parallel processors such as multi-core CPUs, GPUs, Cell-type architectures, and digital signal processors (DSPs), offering broad prospects in fields like gaming, entertainment, scientific research, and medical applications. **2 Compiling OpenCL Examples** This example is developed using the Sienovo XM5728-IDK-V3 development board. On Ubuntu, execute the following command to install `gawk`, a text find-and-replace utility: Host# sudo apt-get in --- ## AM5728 DSP JTAG Connection and Debugging Method - URL: https://intl.sienovo.cn/blog/116896814 - Date: 2021-05-16 - Tags: #AM5728, #DSP, #JTAG **1 Applicability Description** This example primarily demonstrates connecting to the DSP core using an emulator via the JTAG interface. The example is based on the Sienovo XM138-IDK-V3 AM5728 development board. ## **2 Emulator Connection to DSP in Debug Mode** 1. ****Experiment Steps********:**** * Install CCS6.1.3 according to the instructions in the software installation manual. Pay attention to updating the relevant emulator drivers as per the document. * Select Debug boot mode for the development board, set the DIP switches to 11111, and connect the emulator to the JTAG interface. If using an XDS200 or XDS560V2 emulator, ensure to update the emulator firmware and drivers. * Open CCS, configure the file, connect the ARM core, then connect the DSP core. In the CCS interface, click View, then click Target Configurations. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/116896814/01_8d14e2316d0ab855dceaea4138fa4c3b.png) Figure 1 Right-click in the pop-up t --- ## 基于AM5728 Caffe 机器学习案例-darknet物体分类与人脸识别 - URL: https://intl.sienovo.cn/blog/116895525 - Date: 2021-05-16 - Tags: #AM5728, #MachineLearning, #YOLO, #CAFFE, #ObjectRecognition --- Title: AM5728 Caffe Machine Learning Example – Darknet Object Classification and Face Recognition Content: ## **1 YOLO Darknet Porting and Application Development** YOLO is an end-to-end real-time object detection system based on deep learning methods. Darknet is the implementation of YOLO, but Darknet includes more than just YOLO—it also contains other components. This experiment mainly introduces how to port the YOLO Darknet machine learning framework to the AM5728 platform, and demonstrates a darknet-master example for image recognition. For ease of testing, the Xinmai XM5728-IDK-V3 development board provides verified test files located in the "Demo\\app\\Yolo\_Darknet\\bin" directory on the installation disc. The bin folder contains: the required yolo.weights file, the compiled darknet executable, the cfg folder (configuration files), and the data folder (image data). The following section details the specific compilation method for the darknet-master project. ### **1.1 Co --- ## OMAPL138 TI Official Website Development Resources Collection - URL: https://intl.sienovo.cn/blog/115450055 - Date: 2021-04-05 - Tags: #OMAPL138, #C6748, #SPARTAN6, #MulticoreHeterogeneous, #DevResources OMAPL138 TI Official Website Development Resources Collection [https://wenku.baidu.com/view/321349309b6648d7c0c74612.html](https://wenku.baidu.com/view/321349309b6648d7c0c74612.html) 1 Evaluation Board Introduction Based on TI OMAP-L138 (fixed-point/floating-point DSP C674x + ARM9) + Xilinx Spartan-6 FPGA processor; OMAP-L138 FPGA connects via uPP, EMIFA, I2C bus, with communication speeds up to 228MByte/s; OMAP-L138 main frequency 456MHz, with computing power up to 3648MIPS and 2746MFLOPS; FPGA compatible with Xilinx Spartan-6 XC6SLX9/16/25/45, strong platform upgrade capability; The development board exposes rich peripherals, including Gigabit Ethernet, SATA, EMIFA, uPP, USB 2.0 and other high-speed data transfer interfaces, as well as common interfaces such as GPIO, I2C, RS232, PWM, McBSP; Certified through high and low-temperature tests, suitable for various harsh working environments; DSP+ARM+FPGA triple-core CPU module, with dimensions of 66mm*38.6mm, using industrial-grade B2 --- ## OMAPL138 Duntai I2C LCD Touchscreen Driver Porting - URL: https://intl.sienovo.cn/blog/115430239 - Date: 2021-04-04 - Tags: #OMAPL138, #C6748, #LCD, #Touch, #DriverPorting ## OMAPL138 Duntai I2C LCD Touchscreen Driver Porting In this article, we will explore the process of porting the GT811 touchscreen driver for the OMAPL138 platform, specifically focusing on the hardware analysis and software configuration required to establish a connection via the I2C interface. By the end of this post, you will have a clear understanding of the necessary steps to configure the I2C pins and handle the interrupt and reset functionalities for the GT811 LCD touchscreen. ### Hardware Analysis ![Hardware Setup](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/115430239/01_ebd050ba17d5f0321eda80613cdf2127.png) The GT811 touchscreen controller connects to the OMAPL138's I2C1 interface. To ensure proper communication, it is essential to configure the corresponding pins on the AM335x for I2C functionality. ### Software Configuration To facilitate the communication between the GT811 and the OMAPL138, we need to configure two primary pins associated with I2C1: 1. --- ## LCD Touchscreen Interface on Xinmingxin AM5728_am5718 Development Board - URL: https://intl.sienovo.cn/blog/115382582 - Date: 2021-04-01 - Tags: #AM5728, #LCD, #Touchscreen, #DriverPorting, #SchematicDesign **1 Overview of the Development Kit** * Based on the TI AM5728 floating-point dual DSP C66x + dual ARM Cortex-A15 industrial control and high-performance audio/video processor; * Heterogeneous multi-core CPU integrating dual-core Cortex-A15, dual-core C66x floating-point DSP, dual-core PRU-ICSS, dual-core Cortex-M4 IPU, and dual-core GPU, supporting multi-core development with OpenCL, OpenMP, and SysLink IPC; * Powerful video encoding and decoding capabilities, supporting 2K@30fps, 1×1080P@60fps, 2×720P@60fps, or 4×720P@30fps hardware video encoding/decoding, and H.265 software decoding; * Supports up to 1×1080P@60fps full HD video input, and 1×LCD + 1×HDMI 1.4a output; * Dual-core PRU-ICSS industrial real-time control subsystem supporting industrial protocols such as EtherCAT, EtherNet/IP, and PROFIBUS; * High-performance GPU with dual-core SGX544 3D accelerator and GC320 2D graphics engine, supporting OpenGL ES 2.0; * Rich peripheral interfaces, including dual Gigabit --- ## Issues Encountered During LCD Porting (AM5728) - URL: https://intl.sienovo.cn/blog/115382298 - Date: 2021-04-01 - Tags: #AM5728, #LCD, #Touchscreen, #DSP+ARM, #QT **Development Environment: Using Xinmai AM5728 core board, custom-made board, LCD models: AT080TN64, AT070TN94** **Problems Encountered:** **1. The /dev/fb0 device node is not created** **2. LCD character display order is reversed** **3. LCD color display is incorrect** LCD-related configuration in the device tree is as follows: ```dts aliases { display1 = &lcd; rtc0 = &tps659038_rtc; rtc1 = &isl1208_rtc; }; lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 0>; brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; lcd: display { compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; enable-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; backlight = <&lcd_bl>; label = "lcd"; panel-timing { clock-frequency = <33300000>; hactive = <800>; vactive = <480>; hfront-porch = <210>; hback-porch = <46>; hsync-len = <20>; vfront-porch = --- ## Research and Design of an OFDM Underwater Acoustic Communication System Based on OMAPL138 DSP+ARM - URL: https://intl.sienovo.cn/blog/114708180 - Date: 2021-03-12 - Tags: #omapl138, #UnderwaterAcoustic, #OFDM, #C6748, #FPGA The ocean is a vital part of Earth and contains abundant resources, yet human exploration of the marine environment remains in its early stages. With increasing over-exploitation of terrestrial resources, the importance of studying and utilizing marine resources has become more evident. In this context, information transmission under marine conditions is crucial. Therefore, achieving high-speed and highly reliable communication in underwater environments has become a primary research goal. Among various communication methods, acoustic waves are considered the only viable means for medium- to long-range wireless communication in underwater environments. As such, underwater acoustic (UWA) communication has received significant attention from research institutions worldwide. Underwater acoustic channels are characterized by strong multipath effects, high attenuation, high noise levels, and severe bandwidth limitations. Hence, a modem with strong multipath resistance and high spectral eff --- ## Development of a Rail Transit Sela Door Controller Based on OMAPL138 DSP+ARM Dual-Core CPU - URL: https://intl.sienovo.cn/blog/114707833 - Date: 2021-03-12 - Tags: #omapl138, #c6748, #PlugDoorController, #RailTransit, #FPGA The development of China's high-speed rail industry holds broad prospects. Compared to other modes of transportation, high-speed rail offers greater capacity, lower energy consumption, and advantages such as safety, comfort, and minimal environmental impact. The safety and stability of high-speed train Sela door systems are critical factors for the safe operation of high-speed railways. This project originates from the demand for a high-performance, highly secure Sela door system. By reflecting on and further studying the shortcomings of existing Sela door controllers, this paper investigates a more reliable and secure design approach. First, based on the functional requirements of the Sela door system, a detailed functional design scheme is proposed. Then, the basic architecture and implementation foundation of dual-core communication are introduced, leading to the selection of a dual-core chip as the core control unit for the Sela door controller. Through comparison with earlier Sela --- ## 基于TI C6748+ SPARTAN6的多核异构评估板解决方案 - URL: https://intl.sienovo.cn/blog/114652310 - Date: 2021-03-11 - Tags: #C6748, #DSP+FPGA, #OMAPL138, #SPARTAN6 --- Title: Multi-Core Heterogeneous Evaluation Board Solution Based on TI C6748 + Spartan-6 Content: ### ******1 Introduction to the Evaluation Board****** * Based on TI TMS320C6748 fixed-point/floating-point DSP C674x + Xilinx Spartan-6 FPGA processor; * DSP and FPGA connected via uPP, EMIFA, and I2C buses, supporting communication speeds up to 228 MByte/s; * DSP clock speed of 456 MHz, delivering up to 3648 MIPS and 2746 MFLOPS computational performance; * FPGA compatible with Xilinx Spartan-6 XC6SLX9/16/25/45, offering strong platform scalability; * The development board exposes rich peripherals, including Gigabit Ethernet, SATA, EMIFA, uPP, USB 2.0, and other high-speed data transmission interfaces, as well as common interfaces such as GPIO, I2C, RS232, PWM, McBSP, VGA, PMOD, and RS485; * Passed high and low temperature testing, suitable for harsh operating environments; * DSP+FPGA dual-core SOM (System-on-Module), measuring 66mm × 38.6mm, using industr --- ## OMAPL138+SPARTAN6 Core Board and Evaluation Board Review - URL: https://intl.sienovo.cn/blog/114106007 - Date: 2021-02-25 - Tags: #OMPAL138, #SPARTAN6, #FPGA, #DSP, #C6748 Last week, I received the OMAPL138 development board from Shenzhen Xinmai Company. My first impression was how small the core board is, about the size of a coin. They used a three-way DC-DC power supply, which results in low power consumption, and all chips are industrial-grade, making it very suitable for our power monitoring equipment. It's worth noting that they've implemented EMC and ESD protection, so electromagnetic interference in power systems is not a concern. I've been playing with the provided examples for a week, and the QT part is very well done. Just for fun, here are some photos I found online.   1. OMAP-L138+FPGA Development Board Introduction         The XM138F-IDK-V3 designed by Shenzhen Xinmai is a DSP+ARM+FPGA triple-core high-speed data acquisition and processing development board, suitable for data acquisition and processing in fields such as power, communication, industrial control, medical, and audio/video. This design utilizes an OMAP-L138+Spartan-6 platfor --- ## XM5728_IDK_V3 Gigabit Network Speed Test Guide Using iperf on AM5728 - URL: https://intl.sienovo.cn/blog/113887222 - Date: 2021-02-20 - Tags: #AM5728, #Iperf, #GigabitNetwork, #NetworkPerformance, #linux This test is conducted on the XM5728_IDK_V3 evaluation board based on the TI AM5728 from Sienovo. 1. iperf Network Speed Test Guide iperf is a performance measurement tool for TCP/IP and UDP/IP that provides network throughput information, as well as statistics such as jitter, packet loss rate, maximum segment size, and maximum transmission unit (MTU) size. The following procedure uses iperf to test network communication speed between the development board and Ubuntu. If iperf is not installed, run "sudo apt-get install iperf" on Ubuntu to install it. On Ubuntu, execute the following commands to check the IP address and wait for the development board to connect: ****Host****\# ifconfig ****Host****\# iperf -s On the development board's file system, run the following command to test network speed: ****Target****\# iperf -c 192.168.1.102 -i 1 "192.168.1.102" should be replaced with the actual IP address of the Ubuntu machine. Important notes during testing: * Disable Wi-Fi o --- ## Porting Xenomai Real-time Operating System to TI AM5728 - URL: https://intl.sienovo.cn/blog/113574231 - Date: 2021-02-02 - Tags: #AM5728, #XENOMAI 1. Goal: Implement a real-time kernel using TI Linux 4.4.19 (which runs normally on the board) + Xenomai, i.e., port Xenomai to Linux 4.4.19. Target board: Xinmai TI AM5728 Development Board ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/113574231/01_ce3a8caff441b9260386b01b8b7f28cb.png) 1. Problem: After applying the ipipe patch, a compilation error occurred in `timer.c`. After modification, it compiled successfully. 2. Reference tutorial: [https://www.cnblogs.com/wsg1100/p/12864199.html](https://www.cnblogs.com/wsg1100/p/12864199.html) 3. The compilation process is as follows: The following error occurred during compilation: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/113574231/02_48ef4ac38fe01e28d54e1df7f396e0d4.png) Solution: Make the following changes in `arch/arm/mach-omap2/time.c`: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/113574231/03_255e169addc23a7c2be5ddc4f68fae71.png) ![](https://pub-048dcb96257f476697b113fcb593 --- ## AM5728 eHRPWM Driver and Interrupt Design Notes - URL: https://intl.sienovo.cn/blog/112205483 - Date: 2021-01-04 - Tags: #AM5728, #EHRPWM, #Driver, #Interrupt ### ******eHRPWM Waveform Generation Method****** (1) Copy the pwm1.sh script to the /opt/tools directory. (2) Run the following commands: root@am57xx-evm:/opt/tools# ****chmod 777**** ****pwm1.sh**** root@am57xx-evm:/opt/tools# ****./pwm1.sh 1000000 500000 200000**** Set APWM1 mode successfully! root@am57xx-evm:/opt/tools# ****cat /sys/kernel/debug/pwm**** platform/dmtimer-pwm@16, 1 PWM device pwm-0 (pwm\_fan ): requested enabled platform/48440200.pwm, 2 PWM devices pwm-0 (sysfs ): requested enabled pwm-1 (sysfs ): requested enabled platform/4843e100.ecap, 1 PWM device pwm-0 (backlight ): requested enabled root@am57xx-evm:/opt/tools# ****cat /sys/class/pwm/pwmchip1/pwm0/{enable,period,duty\_cycle}**** 1 1000000 500000 root@am57xx-evm:/opt/tools# ****cat /sys/class/pwm/pwmchip1/pwm1/{enable,period,duty\_cycle}**** 1 1000000 200000 (3) Then measure the EHRPWM2B pin using an oscilloscope. ![](https://pub --- ## AM5728 OpenCL Case Studies: Implementing Sobel Algorithm, Vector Summation, and Matrix Transposition - URL: https://intl.sienovo.cn/blog/112164167 - Date: 2021-01-03 - Tags: #AM5728, #OPENCL, #OPENCV ### Case Study 1: Implementing the Sobel Algorithm OpenCV (Open Source Computer Vision Library) is a cross-platform computer vision library released under a BSD-licensed open-source model. It implements many common computations for image processing and computer vision. Related download link: //download. csdn .net/download/weixin\_38692122/12632180?utm\_source=bbsseo ### Case Study 2: AM5728/AM57XX OpenCL Usage Example 2 (Vector Summation) This example uses a vector addition program to illustrate OpenCL. Given two four-dimensional vectors, A and B, their sum is stored in vector C. OpenCL decomposes the vectors into multiple tasks based on the user-provided dimensions and distributes them to the DSP for parallel computation. An OpenCL program consists of two parts: the kernel code, which handles the specific algorithm, and the host program, which is responsible for initializing OpenCL and preparing data. The host program loads the kernel code and performs computations according to a --- ## AM5728 High-Performance SoC Meets Industrial Protocol Support, Big Data Computing, and Real-Time Control Needs, Suitable for Image Processing and Power Protocol Management - URL: https://intl.sienovo.cn/blog/112163265 - Date: 2021-01-03 - Tags: #AM5728, #RealtimeBigData, #RTOS, #ProtocolManagement, #Power The AM5728 is a high-performance SoC from TI's Sitara series. Thanks to its heterogeneous multi-core processing architecture, the CPU integrates co-processing units such as multi-core DSP, multi-core PRU, IVA-HD, and GPU. These units significantly enhance the CPU's data and multimedia processing capabilities through hardware acceleration, enabling the chip to meet application requirements in industrial protocol support, big data computing, and real-time control. Sienovo has developed an evaluation board based on the TI AM5728 floating-point dual DSP C66x + dual ARM Cortex-A15 processor. The dual-core ARM runs at up to 1.5 GHz, while the dual-core DSP operates at 750 MHz. It is widely used in various industrial applications such as machine vision, power automation, intelligent transportation, medical equipment, automated sorting systems, precision instruments, and high-end CNC systems. ### Case 1: Machine Vision Application Machine vision uses machines to simulate human visual functi --- ## Solution to Error E: Package 'unrar' has no installation candidate when installing rar/unrar on Ubuntu - URL: https://intl.sienovo.cn/blog/111823712 - Date: 2020-12-27 - Tags: none This error message indicates that `apt-get` cannot find a package named `unrar` in any of its configured repositories. While enabling the "multiverse" repository and running `sudo apt-get update` might resolve this for some, an alternative and robust solution is to download and compile the official RAR/unRAR tools directly from the developer, rarlab.com. This method ensures you get the latest stable version and bypasses any repository-related issues. ## Understanding RAR and unRAR RAR is a proprietary archive file format that supports data compression, error recovery, and file spanning. It was developed by Eugene Roshal. While many Linux systems use open-source alternatives like `zip` and `tar.gz`, RAR remains a popular format, especially for sharing large files. The `unrar` utility is the command-line tool specifically designed to extract files from `.rar` archives. Since the RAR format is proprietary, the `unrar` utility often needs to be obtained from the official source or throug --- ## The Data "Grabber" Standard for Industry 4.0 | How to Build a Digital, Modern Factory with TI DSP+ARM AM5728 Industrial Tablets? - URL: https://intl.sienovo.cn/blog/109503593 - Date: 2020-11-05 - Tags: #AM5728, #DSP, #ARM, #IndustrialDisplay #### As the drumbeat of innovation and digitalization grows louder, manufacturers are facing the need to develop new strategies and invest in more advanced technologies to gain a stronger competitive edge. The sudden pandemic has further intensified enterprises' demand for smart manufacturing, driving efforts to reduce reliance on manual labor. ****Challenges Facing Manufacturing in the Data Era**** 1. How can high-standard modern factories ensure precision and quality control? 2. Equipment chaos and frequent failures make remote equipment management urgent; 3. The manufacturing industry is grappling with a severe labor shortage, while simultaneously facing uneven workloads and inefficient workforce allocation. ****The key to addressing these challenges? Data!**** ****Data Collection + Transparent Management | The Path to a Digital Factory**** Featuring durability and stability as core design principles, Sienovo's rugged industrial tablets withstand harsh operating environment --- ## Design and Application of a Hemodialysis Machine Control System Based on AM5728 - URL: https://intl.sienovo.cn/blog/109152055 - Date: 2020-10-18 - Tags: #AM5728, #Hemodialysis, #DSP, #ARM, #Medical Design and Application of a Hemodialysis Machine Control System Based on AM5728 Industry: Test and Measurement Design Challenges: l Product design in a compact space l Multiple interface extensions, high customization requirements l Special requirements l Long product lifecycle Customer Application The customer application is a hemodialysis machine control system, primarily used for controlling dialysate supply and monitoring waste fluid. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/109152055/01_903c4a03cc7236fb5e347affe285a47d.png)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/109152055/02_21502c5f5f49b58c2d06c12403420d4c.png) Customer Goals All-in-one machine, product design in a compact space Multiple interface extensions, high customization requirements Special requirement: extending an eDP touchscreen using an I2C bus Long product lifecycle Solution For many years, Sienovo embedded boards have been favored by customers, who are very satisf --- ## Designing a Reliable and Convenient Outdoor Workstation Based on the AM5728 Core Board - URL: https://intl.sienovo.cn/blog/109151574 - Date: 2020-10-18 - Tags: #OutdoorWorkstation, #AM5728, #DSP+ARM, #Reliability, #Convenience ## **Introduction** In areas with harsh environments and low population density, significant energy management challenges often arise. In this case, the customer sought a rugged and reliable solution to deliver stable, uninterrupted service across vast regions. Instead of building various physical infrastructures locally, they opted for outdoor server cabinets, providing energy services through a centralized server control system with manageable modules. Ultimately, the Sienovo AM5728 solution met the customer's requirements perfectly, thanks to its compact size, high flexibility, and support for remote services. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/109151574/01_e2c7607e60c34fb7cdf06f9cd4677373.png) **Challenges and Objectives** Most integrated system architectures face the following situation: the customer integrates IT and OT for real-time data transmission, enabling collaborative operation through process management, requiring accurate information to be d --- ## Design of an Intelligent Power Inspection Robot Based on AM5728 DSP+ARM - URL: https://intl.sienovo.cn/blog/109059926 - Date: 2020-10-13 - Tags: #AM5728, #PowerInspection, #Robotics, #DSP, #ARM ## **Design of an Intelligent Power Inspection Robot Based on AM5728** With the conclusion of the peak period for fixed asset investment in power systems during China's 12th Five-Year Plan, investment focus has shifted from infrastructure construction to intelligent operation and maintenance. This transition is unleashing significant demand for monitoring, maintenance, and servicing of power equipment. Traditional manual inspection methods suffer from high labor intensity, inconsistent inspection quality, and heavy reliance on subjective judgment, making them inadequate for meeting the rapidly growing demands of power equipment inspections. As a result, intelligent power inspection robots have emerged as a viable solution. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/109059926/01_d9722a0fe01d4a4b9908cbce5f248cb4.png) There are various types of power inspection robots. Currently, substation inspection robots and tunnel corridor inspection robots are the most widely u --- ## Rugged Wide-Temperature AM5728 Solution for High-Speed Rail Pantograph Video Monitoring Assessment - URL: https://intl.sienovo.cn/blog/109059271 - Date: 2020-10-13 - Tags: #AM5728, #HighSpeedRailPantograph, #VideoMonitoring ## **Rugged Wide-Temperature AM5728 Makes High-Speed Rail Pantograph Video Monitoring More Reliable** China's railway development is rapid, with the total length of railways expected to reach 120,000 kilometers by 2020, of which 18,000 kilometers will be high-speed railways operating at over 200 km/h. In recent years, with the increasing number of IT intelligent devices and applications, the construction of China's high-speed railways has reached its peak. Among them, video surveillance systems have played a prominent role in improving communication for China's high-speed railways. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/109059271/01_85179b2ac6653e23b841acd570163cd3.png) ****Application Requirements**** Modern high-speed trains are electrically powered via a pantograph, which is mounted on the train's roof and collects current through sliding contact with overhead power lines. Therefore, the condition of the pantograph is difficult to monitor and is susceptibl --- ## XM5728-GW IoT Gateway: Smart Agriculture System Solution - URL: https://intl.sienovo.cn/blog/109036827 - Date: 2020-10-12 - Tags: #Gateway, #DSP, #ARM, #AM5728, #Agriculture XM5728-GW IoT Gateway: Smart Agriculture System Solution ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/109036827/01_2c911b0d9b1cb21e7e6b6feda518ed76.png) Introduction Humanity faces unprecedented challenges and potential food crises due to the impacts of climate change and population growth. To better utilize limited resources and increase crop yields, leveraging the power of modern technology has become increasingly important. Smart agriculture not only helps improve harvests but also conserves human resources and reduces the harmful effects of pesticides and chemical fertilizers. Application Requirements A client of Sienovo has been facing severe water shortages and insufficient human resources. Although there is strong market demand for safe organic food, unfortunately, due to the nature of its production, it suffers from severe pest problems. Therefore, the industry believes that a modern, intelligent, and more efficient farming method is crucial for its long-t --- ## Edge AI Gateway Accelerates Air Compressor Applications - URL: https://intl.sienovo.cn/blog/109036530 - Date: 2020-10-12 - Tags: #IndustrialGateway, #SmartGateway, #AirCompressor, #AM5728, #DSP+ARM ## **Edge AI Gateway Accelerates Air Compressor Applications** ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/109036530/01_8ed6339a79ac3cfb39b7e402af6b96a4.png) The number of devices connected to the internet is growing daily. A recent report by Strategy Analytics predicts that 38.6 billion devices will be connected to the IoT by 2025. The rapid development of the IoT wave has led to the generation of massive amounts of data, and edge computing gateways are quickly becoming a critical component for device management, data collection, and transmission. To address this, Advantech has launched an edge computing gateway based on the TI Sitara AM5728 Cortex-A15 processor. As a barometer of China's economic development, the air compressor industry widely applies air compressors in metallurgy, electric power, petroleum, and other industries for blast furnace blowing, pulverized coal conveying for blast furnaces and boilers, and ventilation for mines and power plant cooling t --- ## Image Acquisition and Processing Application with AM5728 + QT, Chinese Font Display - URL: https://intl.sienovo.cn/blog/108945120 - Date: 2020-10-06 - Tags: #AM5728, #QT Step 1: Download the WenQuanYi font. I'm using *wenquanyizenhei.ttf*. I'll attach the file later. Step 2: Place the font file into the Ubuntu system's font directory. Create a new folder named *wqy* under `/usr/share/fonts`, then copy the font file into it. Perform the following operations: \# cd /usr/share/fonts \# mkdir wqy \# cd wqy \# cp /...(font file path) /usr/share/fonts/wqy Note: Make sure you remain in the *wqy* directory, then execute the following commands to update the font cache: \# mkfontscale \# mkfontdir \# fc-cache After completion, open Qt, place a label on the UI, type some text, select the label, and locate the *font* property in the right-side property panel. Click to expand, as shown in the image below: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108945120/01_3fef52e84f5694b87774fc0e4c358bc4.png) Find the font you just installed. Isn't that amazing? ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108945120/02_5fb6c53d --- ## Big Data Water Quality Monitoring IoT System Based on AM5728 DSP+ARM - URL: https://intl.sienovo.cn/blog/108804214 - Date: 2020-09-25 - Tags: #AM5728, #DSP, #BigData, #WaterQualityMonitoring, #IoT This system utilizes the Sienovo XM5728-IDK-V3 AM5728 development board and IoT technology to assist water management by enabling remote, real-time online monitoring of water quality, water level, and flow rate. It provides early warnings for water pollution, statistical analysis of water resource usage, and water level alerts. Through visualization, it organically integrates water management authorities with water supply and drainage infrastructure, forming a "Water Resources Internet of Things." The water quality online monitoring IoT system can promptly analyze and process massive amounts of water-related data, generating actionable insights and decision-making support, thereby managing the entire production, management, and service processes of water systems in a refined and dynamic manner—achieving a "smart" state. ![Water Resources Monitoring System](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108804214/01_bdc3db48b7224ab4032ac4e68ea11e60.png) **Features of the Wat --- ## AM5728 Clock Synchronization Protocol PTP 1588 Support, Master-Slave Implementation, and Achievable Accuracy - URL: https://intl.sienovo.cn/blog/108718048 - Date: 2020-09-21 - Tags: #AM5728, #PTP, #1588, #ClockSync, #Power The development board used for the experiment is the Sienovo XM5728-IDK-V3. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108718048/01_1ce06d7a215e401f6e7247df957c200d.png) IEEE 1588 Precision Time Protocol (PTP) is the standard mechanism for synchronizing clocks across an Ethernet network to sub-microsecond accuracy. It is widely used in industrial automation, motion control, and time-sensitive networking (TSN) applications where coordinated timing across distributed nodes is critical. This post documents what we found when evaluating PTP 1588 support on the TI AM5728 SoC — specifically which Ethernet interfaces support hardware-assisted timestamping and which do not. ## AM5728 Architecture Overview The AM5728 is a TI Sitara SoC featuring dual ARM Cortex-A15 application cores, C66x DSP cores, and — critically for industrial networking — a dedicated **PRU-ICSS (Programmable Real-Time Unit and Industrial Communication SubSystem)**. The PRU-ICSS is a pair of small, det --- ## AM5728 OpenCV 4.4 Porting Experience Sharing Part 2: How to Run Examples - URL: https://intl.sienovo.cn/blog/108633258 - Date: 2020-09-17 - Tags: #AM5728, #OPENCV4.4., #Examples, #3DImaging, #DevBoard This porting effort uses the Xinming AM5728 IDK development board. The company's project involves monitoring power system operating conditions and requires high-definition image processing. The project is based on AM5728 + Lattice FPGA. OpenCV 4.4 supports 3D image analysis, whereas the OpenCV 3.1 included in the TI SDK only supports 2D image processing. 1. Prerequisites: Install the SDK, which includes the cross-compilation toolchain. Install the SDK into the default directory, selecting all available components when prompted: ```bash ./ti-processor-sdk-linux-am57xx-evm-03.01.00.06.bin ``` 2. 1. Create a new demo project ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108633258/01_f1f827042308a0a0ca3d6b84ffa48f11.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108633258/02_2c0e404751dc89855f4e44de289e07fe.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108633258/03_63b07bc179ba2a2171543f404b0e8870.png) ![](https://pub-048dcb9 --- ## AM5728 OpenCV 4.4 Porting Success Experience Sharing - URL: https://intl.sienovo.cn/blog/108632924 - Date: 2020-09-16 - Tags: #AM5728, #OPENCV, #Porting, #opencv4.4, #SienovoDevBoard The porting process described here uses the Sienovo AM5728 IDK development board. Our company's project involves power condition monitoring and requires high-definition image processing. The project is based on AM5728 + Lattice FPGA. OpenCV 4.4 supports 3D image analysis, while the OpenCV 3.1 included in the TI SDK only supports 2D image processing. 1. Copy opencv-4.4.0-bin.tar.gz to the development board (via USB drive or SD card). This file is provided in the cloud storage. tar -zxf opencv-4.4.0-bin.tar.gz ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108632924/01_5937f49c02e0f194764fabe398359d33.png) 2. Configure the OpenCV 4.4.0 library First, back up existing libraries: mv /usr/lib/libopencv\* /usr/lib_bk/ ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108632924/02_b4422b61d6557869c3f46aa50697bfbf.png) Copy files from the lib directory to the system: cp ./* /usr/lib/ -r ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog --- ## Industrial Automation Solution Based on AM5728 - URL: https://intl.sienovo.cn/blog/108438716 - Date: 2020-09-06 - Tags: #AM5728, #DSP, #ARM, #DevBoard The biggest highlight of the 2015 Beijing International Internet Conference was the realization of Bill Gates' prediction — "intelligent robots will enter every household just like laptops." For more details, please refer to CCTV's special program introduction, *Robot Revolution*. Since 2015, sales of intelligent robots have begun to grow explosively at a rate of 200–400%. Service robots have surpassed industrial robots, and the market is expected to grow tenfold compared to the industrial robot market, exceeding trillions of dollars in scale, leading China's new technological and industrial development over the next decade. ![Industrial Automation](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108438716/01_f8c71c1187968bec7785fbabc2991aee.png) Industry Product Categories ![Industrial Automation](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108438716/02_545a28c0e92dd183782a7aea29ce10e8.png) Industry Product Showcase Robot System Block Diagram ![Industrial --- ## AM5728 DSP+ARM-Based Industrial Automation Production Line Solution - URL: https://intl.sienovo.cn/blog/108425967 - Date: 2020-09-05 - Tags: #AM5728, #IndustrialControl, #IndustrialProductionLine, #IndustrialMonitoring, #DSP+ARM ## Industrial Automation Production Line Solution 01. Industrial Automation Solution ![Industrial automation solution](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108425967/01_1762d18d94b9ad210750d63e48430562.png) Solution Advantages Designed and customizable based on the Sienovo AM5728-IDK-V3 platform. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108425967/02_66f8d75e6f5206030b67dd64fdcb0447.png) ■ Based on RT-Preempt Patch real-time Linux system, meeting high real-time requirements for industrial control; ■ Dual 1000M + dual 100M Ethernet ports, supporting Ethernet/EtherCAT functionality; ■ Equipped with industrial bus interfaces such as RS485 and CAN; ■ High-speed 32-channel input and output ports, supporting differential/single-ended/pulse output modes, enabling multi-device control in automated production lines; ■ Fanless design with 24Hrs\*7 continuous operation capability, ensuring long-term stable operation under harsh industrial tempe --- ## AM5728 DSP+ARM-based Industrial Motion Control - CNC Machine Tools - Industrial Motion Controller System Solution - URL: https://intl.sienovo.cn/blog/108413479 - Date: 2020-09-05 - Tags: #AM5728, #DSP+ARM, #MotionControl, #MachineVision ## Industrial Motion Control System Solution XM5728-IDK-V3 Machine Vision & Motion Control Motherboard ■ Product adopts core board + carrier board structure, configurable as needed ■ ARM core for HMI interface + DSP core for complex data computation + FPGA for high-speed motion control ■ Supports various motor drives: pulse motors, variable frequency motors, Yaskawa motors ■ Up to 3 network ports, supporting ETHERCAT industrial bus devices ■ ECNC motion control SDK software package, easily implementing functions required for industrial control ■ Can be used in industrial applications such as machine vision processing, machining centers, engraving machines, and robot systems ![Interface Details](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108413479/01_4fe138f2d0e4b4c170a0d878b41d88ec.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108413479/02_66f8b5e6f5206030b67dd64fdcb0447.png) PRU-ICSS—Industrial Protocol Support ![PRU-ICSS—Industrial Protoc --- ## AM5728 DSP+ARM Array Microphone Solution - URL: https://intl.sienovo.cn/blog/108395770 - Date: 2020-09-04 - Tags: #AM5728, #DSP, #MicArray, #ARM #### Array Microphone Solution 01. AI Smart Voice Solution Product Direction ● In voice interaction, the process generally consists of five stages: target signal acquisition, voice enhancement, speech recognition, semantic understanding, and information feedback. Among these, speech recognition technology is already quite mature. Our product's key advantage lies primarily in voice enhancement. We provide signal acquisition and voice enhancement technologies for voice interaction applications; ● Voice enhancement technology as the core application of this product √ Beamforming √ Sound source localization √ Directional audio pickup √ Sound source separation √ Beamforming √ Echo cancellation √ Noise reduction, dereverberation, etc. ![01](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108395770/01_c42faca521da15fac44d3875c8753f32.png) ![0 --- ## AM5728 DSP+ARM-based Smart Control Unit for Vending Machines - URL: https://intl.sienovo.cn/blog/108369612 - Date: 2020-09-02 - Tags: #AM5728, #VendingMachine, #DSP, #ARM, #SmartDevice Smart Control Unit for Vending Machines The vending machine control unit launched by Xinmai is an embedded integrated product that combines control, communication, and display functions for vending machines. Using this control unit can help you quickly build a complete solution for vending machines. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108369612/01_645ee12fbe8bc31aa8d4fb27843d91ea.png) Quick Setup, No Waiting With Xinmai's smart control unit, communication, control, and display for vending machines are all taken care of, shortening the overall R&D time and bringing products to market without delay! ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108369612/02_110e92e6036f4caae45a219fe24f0ab2.png) Powerful Core, Performance Guaranteed! Equipped with TI AM5728 DSP+ARM multi-core high-performance processor, with a main frequency up to 1.5GHz, it easily handles Android systems and high-end processing demands. Rich Interfaces, Easy Connectivity! --- ## Implementing a Wireless Magnetic Vehicle Detection Gateway on the AM5728 DSP+ARM Platform - URL: https://intl.sienovo.cn/blog/108359922 - Date: 2020-09-02 - Tags: #AM5728, #DSP, #ARM, #Gateway #### **1. Principle of Wireless Magnetic Detection Technology** In the absence of external interference, the Earth's magnetic field remains in a relatively stable state. When an object passes over or stops above the detection area, the magnetic field undergoes subtle changes. Metallic objects, in particular, cause more noticeable disturbances. Wireless magnetometers detect vehicles by analyzing variations in the Earth's magnetic field. When no vehicle is present, the magnetic field remains stable, and the system defaults to a "no vehicle" state. When a vehicle passes over the sensor, it disturbs the magnetic field, which the system interprets as the presence of a vehicle, and the data is then transmitted via wireless communication protocols. #### **2. Working Principle of the Wireless Magnetic Detection System** Wireless magnetic sensors embedded in the road surface detect the presence and passage of vehicles. Using low-power radio communication technology, the detection data is tra --- ## Large-Scale Blood Analyzer Based on AM5728 DSP+ARM+FPGA - URL: https://intl.sienovo.cn/blog/108359837 - Date: 2020-09-02 - Tags: #AM5728, #DSP, #ARM, #BloodAnalyzer, #MedicalElectronics Large-Scale Blood Analyzer ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108359837/01_9c91f3153d68c7cdd530f89f11c4e655.png) Industry: Medical Devices Solution Overview: Blood analyzers are a popular type of medical analysis instrument in China's medical device industry. Due to their widespread adoption, the market demand is substantial. Large-scale blood analyzers have relatively complex hardware architectures, typically requiring a combination of ARM and FPGA. This solution implements the necessary hardware functions at the ARM level, enabling medical device customers to rapidly develop complete system solutions. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108359837/02_3fc172e26f51412d07a90a7b3d59fa96.png) Implementation: Module development and customization based on the Sienovo XM5728-IDK-V3 platform. Features: * Based on the TI AM5728 floating-point dual DSP C66x + dual ARM Cortex-A15 industrial control and high-performance audio/video proce --- ## Online Infrared Thermal Imager and Power Infrared Monitoring System Based on AM5728 DSP+ARM - URL: https://intl.sienovo.cn/blog/108353110 - Date: 2020-09-01 - Tags: #AM5728, #DSP+ARM, #InfraredImaging, #Power Online Infrared Thermal Imager Solution ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108353110/01_8ec0fd52e40934dba3638d4231710085.png) **Online Infrared Thermal Imager Solution** An online infrared thermal imager enables real-time temperature monitoring of inspected equipment. In the event of abnormal temperature conditions, it can immediately report alarms to the central station. This solution is widely applicable in scenarios with high demands for power equipment monitoring, such as power grids, power plants, and industrial or mining enterprises. **Power Infrared Monitoring System** ![WeChat Image_20200217085502](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108353110/02_277b3c00645c49a0cbc2a71ee61c8007.png) Implementation: Module development and customization based on the Sienovo XM5728-IDK-V3 platform. Features: * Built around the TI AM5728 floating-point dual DSP C66x + dual ARM Cortex-A15 industrial control and high-performance audio/video p --- ## AM5728 DSP+ARM-based Power Data Concentrator - URL: https://intl.sienovo.cn/blog/108352975 - Date: 2020-09-01 - Tags: #AM5728, #PowerDAQ, #DSP, #ARM Power Data Concentrator ARM Solution Overview: The power data concentrator, along with remote smart meters and data collectors, forms a remote meter reading, control, and management system. The concentrator is a data aggregation device for a meter reading area, used to collect and store data from water, electricity, gas, and heat meters. The concentrator has both an upstream and a downstream channel. The upstream channel can use GPRS wireless, telephone line, or wired LAN to achieve remote communication with the management center. The downstream channel uses low-power wireless, RS485, or pulse methods to collect, process, and store data from the collectors under its jurisdiction. The AM5728 core board can easily implement all the necessary functions for a concentrator. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108352975/01_e214582b1288c05009df960a46f04cf9.png) Solution Implementation: Module development and customization based on Xinmai XM5728-IDK-V3. Features: --- ## 基于TI AM5728设计3D打印机方案 - URL: https://intl.sienovo.cn/blog/108329431 - Date: 2020-08-31 - Tags: #AM5728, #3D, #Printing, #ARM, #DSP, AE, C, #Medical --- Title: 3D Printer Design Solution Based on TI AM5728 Content: **3D Printer Design Solution Based on TI AM5728** 1. Introduction to 3D Printing 3D printing, also known as additive manufacturing, is a rapid prototyping technology that constructs physical objects layer by layer using digital model files and bondable materials such as powdered metal or plastic. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/108329431/01_5ab424b49c1bd263d41addeed7740fc1.png) 2. Applications of 3D Printing 3D printing is typically implemented using digital material printers. It is commonly used in mold manufacturing and industrial design for prototype creation, and has gradually expanded into direct production of end-use parts. Applications span industries including jewelry, footwear, industrial design, architecture, engineering and construction ([AE](https://www.forlinx.com/product/117.html) [C](https://www.forlinx.com/product_index.html)), automotive, aerospace, dentistry and [medic --- ## Design of a Sanitation Vehicle DVR Solution Based on TI AM5728 - URL: https://intl.sienovo.cn/blog/108329161 - Date: 2020-08-31 - Tags: #AM5728, #VehicleDVR, #Environmental Sanitation Vehicle DVR Solution In July 2019, Shanghai officially launched its waste sorting initiative, creating a ripple effect that brought waste classification into the national spotlight. This marked the beginning of China's nationwide promotion of waste classification systems. According to the joint notice issued by the Ministry of Housing and Urban-Rural Development, the National Development and Reform Commission, the Ministry of Ecology and Environment, and seven other departments—*"Notice on Fully Launching Waste Classification Work in All Prefecture-Level and Higher Cities"*—waste classification efforts have been fully initiated since this year in all prefecture-level and higher cities across China. By 2025, these cities are expected to have basically established complete waste classification and treatment systems. The benefits of proper waste disposal are self-evident. Successful implementation requires strong government-led education and public awareness campaigns to ins --- ## Sharing Experience in Secondary Development Based on AM5728 Development Board - URL: https://intl.sienovo.cn/blog/106630728 - Date: 2020-06-08 - Tags: #AM5728, #CustomBoard, #DevBoard, #DSP, #ARM Module development and customization based on the Xinmai XM5728-IDK-V3 development board. Features: * Based on TI AM5728 floating-point dual DSP C66x + dual ARM Cortex-A15 industrial control and high-performance audio/video processor; * Multi-core heterogeneous CPU, integrating dual-core Cortex-A15, dual-core C66x floating-point DSP, dual-core PRU-ICSS, dual-core Cortex-M4 IPU, dual-core GPU and other processing units, supporting OpenCL, OpenMP, SysLink IPC multi-core development; * Powerful video encoding and decoding capabilities, supporting 1-channel 1080P60 or 2-channel 720P60 or 4-channel 720P30 hardware video encoding and decoding, and H.265 software video decoding; * Supports up to 1-channel 1080P60 full HD video input and 1-channel LCD + 1-channel HDMI 1.4a output; * Dual-core PRU-ICSS industrial real-time control subsystem, supporting EtherCAT, EtherNet/IP, PROFIBUS and other industrial protocols; * High-performance GPU, dual-core SGX544 3D accelerator and GC320 --- ## Audio Analysis Using AM5728 DSP + ARM - URL: https://intl.sienovo.cn/blog/106628244 - Date: 2020-06-08 - Tags: #AM5728, #Audio, #Video, #IndustrialControl, #DSP Recently, I've been working on audio analysis based on the AM5728 platform. platform ------------------------------------------> davinci-mcasp.c codec ---------------------------------------------> tlv320aic3x.c machine -------------------------------------------> davinci-evm.c The development board used is the Xinmai XM5728-IDK-V3. ● The mainboard adopts a core board + baseboard architecture, allowing customers to choose different CPU, memory, and storage configurations depending on their application ● The core board features the TI AM5728 processor based on ARM Cortex-A15, integrated with a C66x™ Floating-Point VLIW DSP running at 750MHz ● The AI57xx baseboard integrates two audio codec chips, enabling simultaneous 4-channel audio output ● The AI57xx also provides rich peripheral interface resources, including Gigabit Ethernet, USB_OTG, LCD, HDMI, WIFI + BT, JTAG, TF card, etc. ● The AI57xx supports expansion of circular microphone array boards, offering either a 6+1 --- ## Video Surveillance Smoke Detection System Based on AM5728 DSP+ARM - URL: https://intl.sienovo.cn/blog/106423011 - Date: 2020-05-29 - Tags: #AM5728, #SmokeDetection, #DSP, #ARM Embedded video analytics at the edge demands processors capable of running real-time computer-vision workloads without the overhead—or cost—of a cloud connection or an attached host PC. This post walks through a video surveillance and smoke detection system built around Texas Instruments' AM5728 SoC, explaining how its heterogeneous DSP+ARM architecture is exploited to split video capture, communication, and inference across cores, and how the smoke-detection algorithm is designed to be robust against the false triggers that defeat simpler motion-based approaches. ## Why AM5728? The AM5728 is a member of TI's Sitara family of application processors. Its defining feature for compute-intensive edge tasks is the pairing of dual ARM Cortex-A15 application cores with two TMS320C66x floating-point DSP cores on the same die. The C66x DSPs are capable of up to 40 GFLOPS per core and expose a SIMD instruction set optimised for fixed- and floating-point signal processing, making them a natural --- ## Autonomous Obstacle Avoidance System for UAVs Based on OMAPL138 DSP+ARM+FPGA, Millimeter-Wave Radar, and Monocular Vision Fusion - URL: https://intl.sienovo.cn/blog/106422831 - Date: 2020-05-29 - Tags: #DSP+ARM, #mmWave, #Radar, #omapl138, #fpga In recent years, civil small unmanned aerial vehicles (UAVs) have received increasing attention and application, becoming widely used in fields such as express delivery, food delivery, and power line inspection. UAVs equipped with autonomous obstacle avoidance capabilities hold broad application prospects in social production, scientific research, and aerial photography operations. Such systems not only ensure stable flight but also enable UAVs to effectively avoid obstacles during complex missions, reducing damage from collisions and associated secondary hazards. Scholars worldwide have conducted extensive research on UAV autonomous obstacle avoidance. Conventional UAV obstacle avoidance solutions typically rely on pre-existing 3D elevation maps, multi-camera visual sensors, or combinations of multiple sensors. However, existing obstacle avoidance systems generally suffer from drawbacks such as large size, high power consumption, heavy weight, and high cost. Autonomous obstacle avoida --- ## TI DSP TMS320C66x (1) Hardware Overview - URL: https://intl.sienovo.cn/blog/106414130 - Date: 2020-05-28 - Tags: #AM5728, #DSP, #C66X #### Table of Contents * Overview * C66x Processor Core * C66x Pipeline Architecture ## Overview The C66x DSP represents the latest generation of fixed- and floating-point DSPs, featuring four multipliers designed to perform single-precision floating-point operations. The C66x DSP core can simultaneously execute up to eight floating-point multiplication operations. Combined with a maximum clock frequency of up to 1.4 GHz, this delivers exceptional floating-point processing performance. By integrating multiple C66x DSP cores with other processing elements, highly scalable multicore System-on-Chip (SoC) devices with mid-to-high performance can be created. This article uses the TMS320C6678 as an example to introduce the C66x core. The TMS320C6678 integrates eight C66x cores, each operating at a maximum core frequency of 1.4 GHz, delivering a theoretical processing performance of 179.2 (22.4×8) GFLOPS and 358.4 (44.8×8) GMACS. Each processor includes a multi-level memory hierarc --- ## Design and Implementation of AM5728 DSP+ARM-Based Logistics Robots for Automated Sorting and Delivery, AGV - URL: https://intl.sienovo.cn/blog/106390114 - Date: 2020-05-28 - Tags: #AM5728, #LogisticsRobot, #DSP+ARM, #ImageRecognition, #AGV AM5728 DSP+ARM-based logistics robot enabling automated sorting and delivery ![](https://imgconvert.csdnimg.cn/aHR0cHM6Ly90aW1nc2EuYmFpZHUuY29tL3RpbWc_aW1hZ2UmcXVhbGl0eT04MCZzaXplPWI5OTk5XzEwMDAwJnNlYz0xNTkwNTkzNTg4MzgwJmRpPWU1NjE4NjA5MDVkNTI2NTM1YmEyOGE3MTg3YTQ0ZDRhJmltZ3R5cGU9MCZzcmM9aHR0cCUzQSUyRiUyRnprcmVzMS5teXpha2VyLmNvbSUyRjIwMTkwNiUyRjVjZmU0YzE2OGU5ZjA5Njk3NzBmMWNlYl8xMDI0LmpwZw?x-oss-process=image/format,png)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/106390114/02_dede0e65b49d3982a43403b3138d0c82.png) Physical view of Amazon logistics robots: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/106390114/03_00e65bff0048dd6e93afd42ae66ff986.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/106390114/04_289d2fe0b331895711727e3cfc3d2b4e.png)![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/106390114/05_3026090c99f9acc53ef05cc52fd7d10b.png) **Function Overview and Application Areas** China's logistics industry started relat --- ## Embedded License Plate Recognition Based on AM5728 DSP+ARM Platform - URL: https://intl.sienovo.cn/blog/106390678 - Date: 2020-05-27 - Tags: #AM5728, #LicensePlateRecognition, #DSP+ARM With the emergence of "smart cities," "smart parking," and "smart communities," there has been a continuous wave of equipment upgrades. In industries such as security and transportation, license plate recognition technology is increasingly adopted for vehicle management, enabling artificial intelligence applications. License plate recognition—worth it because of you. By integrating a DSP platform with an embedded license plate recognition SDK, you can develop products under your own brand. License Plate Recognition Workflow Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/106390678/01_2d7b63a8b9e2fab653e9fac2f1fa91c8.png) Five Key Features of License Plate Recognition: 1. High overall recognition rate, especially with Chinese characters significantly outperforming similar products; 2. Fast recognition speed, powered by highly optimized license plate localization and recognition algorithms; 3. Supports various license plate types including blue, yellow, new --- ## High-Speed Interface Design for a Heterogeneous Multi-Core Motion Controller Based on AM5728 and FPGA - URL: https://intl.sienovo.cn/blog/105565714 - Date: 2020-04-16 - Tags: #AM5728, #MotionController, #CNC, #DSP+FPGA With the expanding application of embedded motion control systems in manufacturing, heterogeneous multi-core embedded controllers have become one of the key development directions. This article first highlights the advantages achieved by heterogeneous multi-core controllers and identifies existing deficiencies in current controllers regarding data communication interfaces. The proposed motion controller is centered on a heterogeneous processor architecture—AM5728 + FPGA—where the AM5728 integrates ARM Cortex-A15 and DSP C66x processor cores. The ARM Cortex-A15 runs a Linux operating system to enhance the controller's ability to coordinate multiple tasks, while the DSP operates without an OS to ensure computational real-time performance. The focus is on the design of high-speed interfaces and firmware for communication between ARM and DSP, DSP and FPGA, as well as between the controller and PC. Experimental results show that the motion controller achieves high data exchange rates, large --- ## AM335X and AM5728 NOR Flash Boot - URL: https://intl.sienovo.cn/blog/105554507 - Date: 2020-04-16 - Tags: #AM5728, #NORBoot Below is a summary of key design considerations for implementing NOR flash boot on the AM335X, provided for your reference. 1. NOR Flash Boot Overview Refer to section 26.1.7.2 "XIP Memory" in the Technical Reference Manual (TRM) for detailed information. This section will not be elaborated further here. 2. Design Considerations Due to the limited number of pins on the AM335X, many customers consider using multiplexed GPMC data and address lines when interfacing with external NOR flash. This allows the GPMC_AD[15:0] lines to serve dual purposes: as 16-bit data lines and as the lower 16 bits of the address bus. In such configurations, what specific design aspects should be considered? In this setup, GPMC_AD functions as both the 16-bit data bus and the lower 16-bit address bus. According to Table 7-5 "GPMC Pin Multiplexing Options" in the TRM, GPMC_A[10:1] are used as higher-order address lines for the NOR flash. These GPMC_A[10:1] signals support two multiplexing options: they c --- ## Application of the AM5728 DSP+ARM Platform in Navigation Control Systems - URL: https://intl.sienovo.cn/blog/105080988 - Date: 2020-03-24 - Tags: #AM5728, #DSP+ARM, #NavigationControl ## Application of the AM5728 DSP+ARM Platform in Navigation Control Systems The AM5728 DSP+ARM platform is a powerful processing solution that combines a dual-core ARM Cortex-A15 processor with a TI C66x Digital Signal Processor (DSP). This unique architecture makes it an attractive choice for applications that require high-performance processing of complex signals, such as navigation control systems. In this article, we will explore the application of the AM5728 DSP+ARM platform in navigation control systems and discuss its advantages and potential use cases. ### Introduction to Navigation Control Systems Navigation control systems are critical components of various industries, including automotive, aerospace, and robotics. These systems rely on precise positioning and control to ensure safe and efficient operation. The AM5728 DSP+ARM platform can be used to develop navigation control systems that provide accurate and reliable positioning data. ### Advantages of the AM5728 DSP+ARM --- ## TI AM5728 DSP+ARM+FPGA Heterogeneous Multi-Core Industrial Control Processor - URL: https://intl.sienovo.cn/blog/105074879 - Date: 2020-03-24 - Tags: #AM5728, #DSP+ARM+FPGA, #MulticoreHeterogeneous, #IndustrialControl, #DataAcquisition TI AM5728 DSP+ARM+FPGA heterogeneous multi-core industrial control processor. The DSP handles complex algorithm processing, the ARM manages general-purpose tasks, and the FPGA performs high-speed signal acquisition—forming an ideal high-performance embedded industrial motherboard combination. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/105074879/01_fb43383426a4de606a70d5215003dae3.jpeg) #### DSP Algorithm Development For DSP algorithms, in addition to performance and efficiency considerations, integration requirements dictate that the ARM must be able to invoke DSP algorithms via Codec Engine. Therefore, you need to: 1) Be familiar with the xDAIS and xDM standards. Begin by understanding xDAIS, as xDM is merely an extension of xDAIS. Starting from xDAIS 6.10, a tool called QualiTI is included, which can verify whether your DSP algorithm complies with the xDAIS standard (though it does not check for xDM compliance). For details, refer to: http://processors.wiki.t --- ## Introduction to AM5728 DSP+ARM Industrial Data Bus Usage for EtherCAT/PROFIBUS/CAN/RS485 - URL: https://intl.sienovo.cn/blog/104952731 - Date: 2020-03-18 - Tags: #AM5728, #IndustrialControl, #IndustrialBus, #RPOFIBUS, #EHTERCAT The TI AM5728 is a high-integration SoC from Texas Instruments' Sitara family, built around dual ARM Cortex-A15 application cores paired with dual C66x floating-point DSP cores and a rich set of industrial-grade peripherals. This combination makes it a compelling platform for factory automation, motion control, and industrial gateway designs that need to bridge multiple field-bus ecosystems under a single compute substrate. This article walks through how the AM5728 addresses each major industrial communication protocol and explains why the DSP and FPGA extension capabilities matter for demanding real-time applications. ## Platform Overview The AM5728 integrates a Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS), which is TI's dedicated coprocessor fabric for implementing time-critical industrial Ethernet and serial protocols in firmware without burdening the main ARM cores. Each PRU-ICSS instance contains two 32-bit RISC cores clocked at up to 200 MHz, al --- ## Xinxin AM5728-IDK Development Board Baseboard Schematic for Secondary Development - URL: https://intl.sienovo.cn/blog/104952472 - Date: 2020-03-18 - Tags: #AM5728, #Schematic, #SoM, #DSP+ARM, #DevBoard ## Detailed Baseboard Schematic for the AM5728-IDK Development Board The AM5728-IDK is a development board featuring the Texas Instruments (TI) Sitara processor, specifically the AM5728 chip, which is a dual-core ARM Cortex-A15 processor combined with a digital signal processor (DSP) and field-programmable gate array (FPGA) capabilities. This board is designed for industrial applications and is ideal for secondary development using DSP + ARM + FPGA. For developers working with the AM5728-IDK, understanding the baseboard schematic is crucial for creating custom designs and integrating the board into their projects. In this article, we will explore the detailed baseboard schematic for the AM5728-IDK development board. ### Baseboard Schematic Overview The baseboard schematic for the AM5728-IDK consists of several key components, including: * The AM5728 processor * Memory modules (e.g., DDR3 RAM) * Power management components (e.g., DC-DC converters) * FPGA and DSP interfaces * GPIO a --- ## High-Speed AD Data Acquisition and Processing Design and Implementation Based on AM5728 DSP+ARM Platform - URL: https://intl.sienovo.cn/blog/104951902 - Date: 2020-03-18 - Tags: #AM5728, #DSP, #ARM, #HighSpeedData, #Acquisition Texas Instruments (TI) offers a comprehensive lineup of high-performance video processors, providing complete video processing solutions. The AM5728, as the latest SoC (System-on-Chip) in TI's Sitara series, delivers enhanced computational performance and design flexibility through a heterogeneous multi-core processing architecture, programmable multimedia processing, and ultra-high-speed data communication interfaces. The TI AM5728 industrial automation and machine vision processing technology represents TI's most advanced high-performance industrial solution today, with broad application prospects in areas such as industrial robots, precision CNC machine tools, 5-axis engraving machines, industrial HMIs, intelligent transportation systems, VR/AR, and many more—thanks to its flexible interfaces and powerful performance. Module development and customization are based on the Sienovo XM5728-IDK-V3 platform. * ### Project Overview: On the TI AM5728's DSP side, EDMA is used to ac --- ## OMAPL138 + SPARTAN6 DSP+ARM+FPGA Core Board Solution - URL: https://intl.sienovo.cn/blog/104908358 - Date: 2020-03-16 - Tags: #OMAPL138, #C6748, #SPARTAN-6, #DSP+ARM+FPGA, #MulticoreHeterogeneous The OMAPL138 + SPARTAN6 DSP+ARM+FPGA core board is suitable for [UAV autonomous obstacle avoidance systems integrating millimeter-wave radar and monocular vision](https://kns.cnki.net/kns/detail/detail.aspx?QueryID=0&CurRec=6&recid=&FileName=1019000798.nh&DbName=CMFD201901&DbCode=CMFD&yx=&pr=&URLID=&bsm=), heterogeneous multi-core motion controllers, inertial attitude measurement systems, embedded spraying robots, power meter control systems, bridge vibration monitoring, sound monitoring, and other applications. UPP communication is used between the FPGA and DSP. 1 Evaluation Board Introduction Based on TI OMAP-L138 (fixed-point/floating-point DSP C674x + ARM9) + Xilinx Spartan-6 FPGA processor; OMAP-L138 and FPGA are connected via uPP, EMIFA, and I2C buses, with communication speeds up to 228 MByte/s; OMAP-L138 main frequency is 456MHz, with computing power up to 3648 MIPS and 2746 MFLOPS; FPGA is compatible with Xilinx Spartan-6 XC6SLX9/16/25/45, offering strong platform upgra --- ## AM5728 uboot Execution Flow - URL: https://intl.sienovo.cn/blog/90140811 - Date: 2020-02-27 - Tags: #AM5728, #uboot After the AM5728 CPU powers on, the execution flow is: ROM->MLO(SPL)->u-boot.img **First-stage bootloader:** These codes are automatically executed after the board powers on, such as determining the boot method (SDcard, SPI, NOR), and then jumping to the second-stage bootloader. These codes should be stored in 176KB of ROM. Second-stage bootloader: MLO(SPL), used for hardware initialization, disabling the watchdog, disabling interrupts, setting CPU clock frequency and speed, loading uboot.img, DTS, and other operations. The MLO file should be mapped to 64 KB of Internal SRAM. Third-stage bootloader: u-boot.img, the entry point for C code. The MLO and u-boot execution flow is as follows: ``` reset //(arch/arm/cpu/armv7/start.S) save_boot_params_ret //(arch/arm/cpu/armv7/start.S) |- disable interrupts |- cpu_init_cp15 //(arch/arm/cpu/armv7/start.S) | |- Invalidate L1 I/D | |- disable MMU stuff and caches |- cpu_init_crit //(arch/arm/cpu/armv7/start.S) | |- lo --- ## AM5728 + Euresys Industrial Camera Image Processing Case Study - URL: https://intl.sienovo.cn/blog/89418667 - Date: 2020-02-27 - Tags: #AM5728, #CoreBoard, #ImageProcessing, #ProjectCustomization, #TIBoardCustomization This article discusses the AM5728 + Euresys industrial camera image processing case study. #### I. Core Board Introduction The XM-AM5728-KIT consists of the XM-SOM5728-CORE core board and the XM5728-IDK-V3 industrial baseboard. The XM-SOM5728 core board integrates power management, DDR3, NAND FLASH, QSPI FLASH, EEPROM, and an SD card slot. It also extends the AM5728's HDMI, PCIe, SATA, USB, Ethernet, video, audio, industrial network, UART, SPI, I2C, CAN, and GPIO interfaces via connectors. Users can choose a standard Sienovo baseboard or design their own baseboard according to their needs to implement their specific functions. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/89418667/01_af69c6c85e404a653403aec7a8443ca8.png) Figure 1 XM-OM5728-CORE Core Board Block Diagram ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/89418667/02_bcb1373809b54ac99a6473892fc44f45.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/89418667/03_5ecbca15a0122 --- ## Industrial 4.0 High-Speed Data Acquisition Solution Based on AM5728 DSP+ARM - URL: https://intl.sienovo.cn/blog/104546948 - Date: 2020-02-27 - Tags: #AM5728, #Industry4.0, #HighSpeedDAQ, #5G, #SmartGateway Industrial 4.0 High-Speed Data Acquisition Solution Based on AM5728 DSP+ARM ****1 AM5728 Features**** * Based on TI AM5728 floating-point dual DSP C66x + dual ARM Cortex-A15 industrial control and high-performance audio/video processor; * Multi-core heterogeneous CPU, integrating dual-core Cortex-A15, dual-core C66x floating-point DSP, dual-core PRU-ICSS, dual-core Cortex-M4 IPU, dual-core GPU and other processing units, supporting OpenCL, OpenMP, SysLink IPC multi-core development; * Powerful video encoding and decoding capabilities, supporting 1 channel 1080P60 or 2 channels 720P60 or 4 channels 720P30 hardware video encoding/decoding, and H.265 software video decoding; * Supports up to 1 channel 1080P60 full HD video input and 1 channel LCD + 1 channel HDMI 1.4a output; * Dual-core PRU-ICSS industrial real-time control subsystem, supporting industrial protocols such as EtherCAT, EtherNet/IP, PROFIBUS; * High-performance GPU, dual-core SGX544 3D accelerator and GC320 2 --- ## Applications of AM5728-based 5G Smart Gateways in the Industrial Internet - URL: https://intl.sienovo.cn/blog/104546704 - Date: 2020-02-27 - Tags: #5G, #AM5728, #Gateway, #IIoT, #Industry4.0 ****Xinmai's AM5728 Development Platform-based 5G Smart Gateway**** With the rapid development of the Internet and the Internet of Things (IoT), coupled with the national policy requirements of "Made in China 2025," various industries need to implement information-based management for production to improve production management efficiency and energy efficiency, thereby promoting the development of national Industry 4.0. Therefore, the informatization and monitoring of the five key production elements (Man, Machine, Material, Method, Environment) have become a major urgent need. The essence of the IoT is the interconnection of all things, requiring the sensing and control of object dynamics, which necessitates various sensors and controllable devices, such as temperature and humidity sensors, wind speed sensors, infrared sensors, single-lamp controllers, etc. However, in industrial sites, various devices use different protocols, installation methods, and communication methods, making --- ## Desktop Robot Development Case Study Based on AM5728 Development Board - URL: https://intl.sienovo.cn/blog/104546102 - Date: 2020-02-27 - Tags: #AM5728, #Robotics, #DevBoard, #MachineVision, #DSP ## Desktop Robot Development Case Study Based on AM5728 Development Board The AM5728 development board, designed by Xinmai, is a powerful platform for developing desktop robots. In this article, we will explore a case study that demonstrates the capabilities of the AM5728 in building a desktop robot. ### Introduction The AM5728 development board features a TI Sitara processor with dual ARM Cortex-A15 cores, making it an ideal choice for applications that require high-performance processing. The board also includes a range of peripherals, including Gigabit Ethernet, USB 3.0, and HDMI. ### Hardware Configuration The desktop robot developed in this case study uses the AM5728 development board as its brain. The robot is equipped with a range of sensors, including cameras, lidar, and ultrasonic sensors. The cameras are used for machine vision tasks, such as object recognition and tracking, while the lidar and ultrasonic sensors are used for obstacle detection and navigation. ### Softw --- ## AM5728-Based Industrial IoT Data Acquisition Platform - URL: https://intl.sienovo.cn/blog/104545375 - Date: 2020-02-27 - Tags: #AM5728, #IIoT, #Digitalization The Xinmai Industrial Equipment IoT Cloud Platform is a highly customizable information platform developed based on Xinmai's core operational control products and integrated information technology. It is designed to adapt to the network interconnection of industrial equipment, provide value-added services to customers, create a new ecosystem for technical services, and bridge the last mile of industrial applications. This platform communicates with the cloud platform through the network communication function in the controller, offering a fully integrated and interconnected solution spanning device control, sensing layer, scheduling layer, and information management layer, allowing for rapid deployment without extensive development. The Industrial Equipment IoT Cloud Platform is widely applied in fields such as smart manufacturing, digital factories, and "Internet+". Manager Liang Quan, Head of SAP Greater China South Region Business Unit, stated that Xinmai Technology is a reliable --- ## Design of Harvesting Manipulator Control System Based on AM5728 DSP+ARM - URL: https://intl.sienovo.cn/blog/104483002 - Date: 2020-02-24 - Tags: #AM5728, #DSP, #ARM, #robotics, #manipulator By leveraging image processing techniques from pattern recognition and using the AM5728 processor from TI's Sitara series, this paper presents a harvesting manipulator control system based on a vision system and servo motor driving methods. Experimental results show that the system can accurately harvest target fruits with a success rate of 89%. It takes about 9 seconds to pick one apple. The system features fast operation, high accuracy, and strong feasibility, meeting general fruit harvesting requirements and demonstrating excellent practicality. Robotics is one of humanity's greatest inventions of the 20th century. With increasing population, food supply pressures, and a continuous decline in agricultural labor, "unmanned farms" are becoming a mainstream trend. Harvesting robots, in particular, offer significant advantages in reducing labor intensity and improving work efficiency, making them a key player in "smart agriculture." Given this context, this paper combines pattern reco --- ## TI AM5728 RTOS Environment Setup Notes - URL: https://intl.sienovo.cn/blog/104255204 - Date: 2020-02-10 - Tags: #AM5728, #RTOS, #DSP ## TI AM5728 RTOS Environment Setup Notes Setting up a Real-Time Operating System (RTOS) environment on the TI AM5728 processor can be a complex task, especially for those new to embedded systems development. In this article, we will provide a step-by-step guide on how to set up the RTOS environment on the AM5728 processor, using the Processor SDK RTOS. ### Official Documentation For detailed information on setting up the RTOS environment on the AM5728 processor, please refer to the official documentation provided by Texas Instruments: http://software-dl.ti.com/processor-sdk-rtos/esd/AM57X/latest/index_FDS.html Note that the documentation provided by TI is comprehensive and covers all aspects of setting up the RTOS environment, including hardware requirements, software installation, and configuration. ### Setting Up the RTOS Environment To set up the RTOS environment on the AM5728 processor, follow these steps: 1. Download and install the Processor SDK RTOS from the TI website. --- ## AM5728 CPSW Ethernet Port Debugging Notes - URL: https://intl.sienovo.cn/blog/103429756 - Date: 2019-12-06 - Tags: #AM5728, #CPSW, #Ethernet 1. During debugging, the Gigabit Ethernet port failed to initialize. The issue was later found to be caused by a mismatch in PHY addresses. 2. The 100Mbps Ethernet port also failed to come up. The board has four Ethernet ports in total, but only two are being detected as hardware. The root cause is still under investigation. There are many online resources explaining device tree syntax, but even after understanding the syntax, one might still struggle with how device trees actually work in conjunction with kernel drivers. Here, I'll use TI's CPSW as an example to illustrate the subtle relationship between device trees and kernel drivers. CPSW stands for TI's Common Platform Ethernet Switch. It is a three-port switch consisting of one CPU port and two external ports. The CPSW, or Ethernet switch driver, follows the standard [Linux](http://lib.csdn.net/base/linux) network interface architecture. For TI's AM335x CPSW device tree, the definition is located in the `am33x.dtsi` file, as --- ## TI AM5728 DSP+ARM Multi-core Communication Development Example - URL: https://intl.sienovo.cn/blog/94589325 - Date: 2019-07-03 - Tags: #AM5728, #InterCoreCommunication, #MultiCoreCommunication, #SYS/BIOS, #SharedMemory Inter-core communication methods include MailBox, OpenCL, DCE, IPC, and Big Data IPC. Since we need to use SYS/BIOS, MailBox is excluded. Also, we are not dealing with multimedia signal processing, so DCE is likely unsuitable. I found that OpenCL doesn't allow memory control for DSP code optimization, so OpenCL is also excluded. Now, it seems only IPC and Big Data IPC remain. For shared memory, there is a Big Data IPC example. processors.wiki.ti.com/.../Processor-sdk-MultiWay-of-ARM\-DSP-Communication ### 1. Communication Principle Diagram: The Spartan-6 FPGA collects AD data via the ADS8568 and transmits it to the AM5728 ARM through the GPMC high-speed parallel interface, which connects the core board internally to the ARM side. The ARM side runs a Qt application, which displays the AD data read from the GPMC interface as waveforms. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/94589325/01_8f210b57f234c7a1d92192744c1c6af9.png) ### 2. Hardware Connection: This cas --- ## Sienovo AM5728 CAN Bus Testing and SDK Upgrade, Linux CAN Debugging Commands - URL: https://intl.sienovo.cn/blog/94588789 - Date: 2019-07-03 - Tags: #AM5728, #CAN, #DCAN, #SDKUpgrade, #Porting I. AM5728 CAN Bus Testing Execute the following commands in the development board's file system to configure the CAN0 bus (CAN0 in software corresponds to CAN1 in hardware) with a bitrate of 1MHz and start the CAN bus: Target# canconfig can0 bitrate 1000000 Target# canconfig can0 start Execute the following command to monitor data sent from the PC: Target# candump can0 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/94588789/01_d27c4021eabe94d16c7d73c8e567a4a2.png) Driver automatically installed on PC ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/94588789/02_28421cebc8effcca51909b0e904111a1.png) Then open the debugging instrument software ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/94588789/03_15e311b557ac44e5cba3b063a72bbce9.png) 1. First, set the COM port and bitrate to 1MHz. 2. Select either 'Send Data' or 'Loop Send'. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/94588789/04_38c1c9dcc34f0305fb74d7fc8658e2a0.p --- ## AM5728 High-Performance Computing (Parallel Computing) OpenCL/OpenMP Introduction and Testing - URL: https://intl.sienovo.cn/blog/93607538 - Date: 2019-06-25 - Tags: #AM5728, #OpenCl, #OpenMP, #Opencv, #HeterogeneousComputing ### I. OpenCL/OpenMP Introduction **OpenCL** (Open Computing Language) is a framework for writing programs for heterogeneous platforms. It is an API, similar to the OpenGL architecture, and this heterogeneous platform can consist of CPUs, GPUs, or other types of processors. Recently, I spent some time briefly reviewing technologies related to high-performance computing, such as [OpenMP](http://openmp.org/wp/), [OpenCL](http://www.khronos.org/opencl/), and MPI (with various implementations like [Open MPI](http://www.open-mpi.org/)). I'm documenting a few things I learned from this quick overview here. These summaries and notes are somewhat superficial and require deeper learning and research.        **First**, GPU computing is becoming increasingly popular, and with China's Tianjin supercomputer claiming the top spot in international computing power, it demands attention. Existing technologies, categorized by vendor, include NVIDIA's [CUDA](http://developer.nvidia.com/object/cuda_3_ --- ## Sienovo AM5728 DSP+ARM High-Performance Image Processing Core Board Features Introduction - URL: https://intl.sienovo.cn/blog/93362245 - Date: 2019-06-22 - Tags: #AM5728, #CoreBoard, #IndustrialGrade, #DSPARM, #HeterogeneousMulticore ****1. Core Board Introduction**** ➢ The SOM-XM5728 is an industrial-grade core board from Sienovo Technology based on the TI AM5728 processor. It features immersion gold, lead-free, ten-layer PCB, and industrial-grade design, making it suitable for applications in motion control systems, machine vision processing systems, image recognition systems, audio analysis systems, video analysis systems, high-end measurement instruments, and other industrial applications. * Customers can choose different CPU, memory, and external storage configurations based on their specific applications. The core board supports the TI AM5728 processor, which integrates two ARM Cortex-A15 processors, two floating-point DSP C66x™ Floating-Point VLIW DSPs @ 750MHz, and PRU-ICSS for various industrial protocols. It supports industrial-grade 1GB-4GB DDR3 memory and industrial-grade 4GB-16GB eMMC external storage, offering highly convenient expansion. * The SOM-XM5728 core board supports multiple industrial --- ## Research and Development of an AM5728 DSP + ARM-based Online Fault Monitoring System for Wind Turbines - URL: https://intl.sienovo.cn/blog/93245745 - Date: 2019-06-21 - Tags: #AM5728, #DSP, #FaultDiagnosis In recent years, the total installed capacity and size of wind turbines in China have continuously increased. Mechanical failures in wind turbines are becoming more frequent, and operation and maintenance (O&M) costs are rising, becoming a major factor affecting the cost of the wind power industry. Therefore, the safe, efficient, and reliable operation of wind turbine equipment is particularly crucial. To monitor equipment operating status in real-time, detect hidden faults, and take preventive measures in advance, the development of an online fault monitoring system for wind turbines is of paramount importance. This paper primarily designs an AM5728 DSP+ARM-based online fault monitoring system for wind turbines. The system uses TI's AM5728 as the core controller to achieve multi-channel vibration signal acquisition, fault analysis of vibration signals, human-machine interface (HMI) display, and host computer communication functions. By installing sensors at appropriate locations on t --- ## High-Speed Multi-Channel Data Acquisition and Processing System Based on Sienovo AM5728 Core Board - URL: https://intl.sienovo.cn/blog/93138976 - Date: 2019-06-20 - Tags: #AM5728, #DSP, #FPGA, #MultiChannelDataAcquisition, #HighSpeedAcquisition With the continuous development of hydroacoustics, array signal processing technology has gradually been introduced into hydroacoustic applications and serves as a key research direction, assisting in the exploration of the ocean's mysterious realm. Sonar array systems, as typical representatives of new sonar architectures, have improved various performance aspects such as the directivity, sensitivity, and gain of individual transducers, and provide the material basis for research into array signal processing technology in the hydroacoustic field. Based on the need to record signals picked up by sonar arrays, a multi-channel data acquisition and storage system was designed. The system synchronously acquires 48-element sonar array signals after processing by signal conditioning circuits and uses GPS to obtain time information for data sampling points. The start time of data acquisition is precisely aligned with the hour mark, allowing multiple sets of equipment to work synchronously to --- ## Design of an Embedded Binocular Stereo Vision Hardware and Software Platform Based on AM5728 DSP+ARM - URL: https://intl.sienovo.cn/blog/93138572 - Date: 2019-06-20 - Tags: #AM5728, #BinocularVision, #DSPARM Binocular Stereo Vision is an important form of machine vision. It has broad application prospects because it can easily calculate the depth information of objects relative to the camera within the camera's field of view using image information from the left and right cameras. Especially with its development over recent decades, stereo vision has been increasingly applied in fields such as robot vision, aerial surveying and mapping, reverse engineering, military applications, medical imaging, and industrial inspection. However, the technical complexity of binocular stereo vision technology means it is rarely applied in embedded scenarios. Due to its inherent large computational load, binocular stereo vision technology often requires implementation on PC platforms or through the collaborative efforts of DSPs and FPGAs. This paper focuses on systematically researching the design of an embedded binocular stereo vision hardware and software platform, and delves into the principles of bin --- ## AM5728 Core Board Factory Test Notes - URL: https://intl.sienovo.cn/blog/92718549 - Date: 2019-06-17 - Tags: #AM5728, #FactoryTest, #eMMC ## AM5728 Core Board Factory Test Notes When working with industrial computing boards, thorough testing and validation are crucial to ensure reliable operation and prevent potential issues. In this article, we will cover the factory test notes for the AM5728 core board, including eMMC formatting, power testing, and SPI flash flashing. ### eMMC Formatting Before proceeding with the factory test, it's essential to format the eMMC storage. The eMMC mounting, partitioning, and formatting process is well-documented in the article "eMMC mounting, partitioning, and formatting" by [https://blog.csdn.net/u011975319/article/details/51803126](https://blog.csdn.net/u011975319/article/details/51803126). For the purpose of this article, we will assume that the eMMC has been properly formatted. ### Power Testing The first step in the factory test is to check for power short circuits on the board using a multimeter. It's also essential to verify that the input terminal power voltage and signal se --- ## TI AM5728 LCD Touchscreen Driver Porting and DTS Configuration - URL: https://intl.sienovo.cn/blog/92019971 - Date: 2019-06-14 - Tags: #AM5728, #LCD, #DriverPorting, #DTS, #Touchscreen Adding an LCD screen to the Sienovo XM5728-IDK-V3 development board. The result after successful integration: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/92019971/01_905920e4c9c79ed2156dc6fdbb8a0e27.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/92019971/02_ffab82ca136c262e335d618a0c2c1797.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/92019971/03_e62077c5a47f5efe4d0c0320b96ba1b7.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/92019971/04_d5a12dc34dde67521f8751e1af904f69.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/92019971/05_958b7b819702d0dbde768841ced0467c.png) References: Porting LCD on AM335x using DTS (Part 1) [https://blog.csdn.net/xiaojiezuo123/article/details/49890733](https://blog.csdn.net/xiaojiezuo123/article/details/49890733) For driver source code, add WeChat: 13670212541, technical discussions are welcome. Debugging Experience/Notes: **Development Environment: Using Si --- ## AM5728 Linux Kernel Compilation Method - URL: https://intl.sienovo.cn/blog/91978735 - Date: 2019-06-14 - Tags: #AM5728, #内核, #编译, #linux I. Compiling the Linux Kernel In the Linux kernel source installation directory, execute the following command to compile the Linux kernel: ```hljs Host# make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- zImage -j 32 ``` "-j 32" is a compilation option that tells the operating system to use 32 threads for compilation, thereby speeding up the compilation process. After compilation, the kernel image file `zImage` will be generated in the "arch/arm/boot" path within the Linux kernel source installation directory. The compiled kernel image file can be used to replace the kernel image file in the development board's file system. When booting the system using an SD boot card, if you need to replace the kernel image, there are the following methods: * Use the new kernel image file, keeping the filename consistent with the original, to replace the corresponding file in the "/boot" directory of the SD boot card's rootfs partition. * Use the new kernel image file, keeping the filename co --- ## AM5728-based High-Speed Image Processing Platform for Machine Vision - URL: https://intl.sienovo.cn/blog/91353345 - Date: 2019-06-09 - Tags: #AM5728, #DSP+ARM, #HighSpeedImageProcessing, #StereoCamera Machine vision involves using machines to simulate human vision, performing measurements and judgments on images. It is an effective way to achieve precise control, intelligence, and automation in instrumentation and equipment. Machine vision can accomplish many tasks that humans cannot, while also helping to improve product quality and production efficiency. Research into machine vision systems holds significant importance and broad market prospects. High speed, integration, and personalization are the future directions for machine vision systems, necessitating an embedded general-purpose high-speed image acquisition and processing hardware platform to adapt to its development. Currently, domestic machine vision manufacturers primarily act as agents for foreign products, including hardware, especially for high-speed, high-resolution applications in high-end scenarios. Domestic machine vision manufacturers have recognized the need to develop their own products, and some research insti --- ## AM5728-Based Power Quality Monitoring System - URL: https://intl.sienovo.cn/blog/90745266 - Date: 2019-06-02 - Tags: #AM5728, #SmartPowerMonitoring, #MultiCoreCommunication, #PowerQualityMonitoring, #CoreBoard With the advancement of science, technology, and industry, many highly automated users are becoming increasingly sensitive to power quality. Any power quality issue can lead to a decline in product quality, or even a halt in engineering operations, causing immeasurable losses to users. Improving power quality can reduce grid losses, extend equipment lifespan, and decrease power production accidents. The management of power quality pollution is inseparable from power quality monitoring. Therefore, accurate and comprehensive power quality monitoring is one of the essential means of power quality management. Compared to foreign countries, China's research and development of power quality monitoring devices is relatively backward. Most domestic manufacturers use microcontroller or industrial PC architectures. While these instruments offer the sole advantage of low cost compared to advanced foreign technologies, they present many problems in practical applications. Therefore, this paper de --- ## Design of a Vision Sorting System Based on AM5728 EtherCAT Technology - URL: https://intl.sienovo.cn/blog/90744953 - Date: 2019-06-02 - Tags: #AM5728, #MachineVision, #EtherCAT, #Sorting As Industry 4.0 advances, the concepts of intelligent manufacturing and smart factories are emerging, and industrial manufacturing is moving towards automation and intelligence. In this development process, the internet, robotics, image processing, and machine learning are being widely applied in industrial production and manufacturing. On the other hand, cameras are like the eyes of robots, and image processing algorithms are the visual perception areas in the brain. The integration of image processing with motion controllers is an inevitable trend in current industrial intelligent development. Therefore, this project uses an open motion controller as the master for image processing, interacting with actuators via real-time Ethernet EtherCAT, thereby improving the accuracy of actuator gripping. Regarding controllers, traditional dedicated robot controllers are highly specialized with closed interfaces, making it difficult for users to directly perform secondary development. They requ --- ## Design and Implementation of a Multi-axis Embedded Motion Controller Based on AM5728 EtherCAT - URL: https://intl.sienovo.cn/blog/90744820 - Date: 2019-06-02 - Tags: #AM5728, #MotionController, #CNC, #Interpolation, #DualCoreComm With the rapid advancement of embedded system technology and the widespread industrial application of high-performance, low-power processor chips, a new technical domain—embedded motion control—has emerged. By integrating embedded system technology into motion control, this field has achieved rapid development and broad application due to advantages such as high cost-performance ratio, strong stability, and the ability to operate independently without a PC. This paper focuses on the research and development of an embedded motion controller based on the OMAP platform, providing a viable solution for general-purpose embedded motion controller design. First, the current state of motion controller research both domestically and internationally is analyzed, with a comparative discussion highlighting the advantages of embedded motion controllers. Based on this analysis, TI's dual-core processor AM5728 is selected as the main control chip. Functional modules are then designed and integrated --- ## A Brief Discussion on AM5728 Bare-Metal Debugging - URL: https://intl.sienovo.cn/blog/90317159 - Date: 2019-05-18 - Tags: #AM5728, #BareMetalBoot, #JTAGDebug ## I. A Brief Discussion on ARM Bare-Metal Debugging 1. Connecting the Emulator and Reading/Writing Registers Plug the hardware emulator into the ARM board's JTAG port, then connect it to the PC. Most modern ARM emulators connect to the PC via USB. After connecting, power on the board, then open the debugging software on the PC. Here, I'm using an ARM11 emulator with AXD as the debugging software. If AXD recognizes the ARM processor, the connection is successful; otherwise, there's an issue. (1) Verify that all power supplies to the ARM processor are correct. (2) Verify the ARM processor's RESET pin. (3) Verify that the ARM processor's crystal oscillator is oscillating. (4) Verify the JTAG interface is correct. If all four points above are normal, the emulator should be able to detect the ARM. 2. Initializing the ARM Processor and DRAM via Script Since it's a bare-metal board, the ARM undergoes no initialization after power-on. Typically, a script is executed to perform basic initia --- ## DSP No-Boot Mode Startup Debugging - URL: https://intl.sienovo.cn/blog/90146559 - Date: 2019-05-12 - Tags: none ### 1 Introduction to JTAG Debugging for ARM/DSP/FPGA Chips On the periphery of the CPU, the processor internally incorporates a hardware implementation of JTAG, providing an external interface through four pins: TMS, TCK, TDI, and TDO. * TCK: Clock signal, providing an independent, fundamental clock signal for TAP operations. * TMS: Mode Select signal, used to control the state transitions of the TAP state machine. * TDI: Data Input signal. * TDO: Data Output signal. * TRST: Reset signal, used to reset (initialize) the TAP Controller. This signal interface is not mandatory in the IEEE 1149.1 standard, as the TAP Controller can also be reset via TMS. * STCK: Clock Return signal, not mandatory in the IEEE 1149.1 standard. ![JTAGåç](http://www.veryarm.com/wp-content/uploads/6a3658a0575286c0d9bbc5dd9989f603.jpg) We know that the CPU communicates with peripherals via pins, and all data is input or output through these pins. JTAG achieves chip testing by monitoring the sign --- ## Implementing High-Speed Data Communication between AM5728 and FPGA via GPMC Interface - URL: https://intl.sienovo.cn/blog/88045541 - Date: 2019-02-28 - Tags: #AM5728, #GPMC, #FPGA, #DSP+ARM+FPGA Hardware: AM5728 Development Board; Artix-7 Development Board Software: Linux am57xx-evm 4.4.19; Vivado 2015.2 Author: Hangzhou Shizhi Information Technology Co., Ltd. Email: admin@sysjoint.com The AM5728 has rich peripheral interfaces, such as V-PORT, PCIe, GPMC, USB, UART, etc. For high-speed data communication with an FPGA, V-PORT, PCIe, or GPMC are typically chosen. Here, we use GPMC, which is the simplest to implement, to achieve high-speed data transfer from the FPGA to the AM5728. The ARM core of the AM5728 runs the Linux 4.4 kernel operating system. It uses DMA via the GPMC interface to read data from the FPGA. Reading 32KB of data took approximately 540us, achieving a speed of about 60MB/s. In practice, by configuring the GPMC interface's timing parameters and operating mode, even faster speeds can be achieved. * GPMC Interface Introduction GPMC stands for General-Purpose Memory Controller. It is an interface used by TI's Sitara series processors, such as the AM5728, to --- ## DSP FPGA Real-time Image Processing Technology Survey - URL: https://intl.sienovo.cn/blog/88043679 - Date: 2019-02-28 - Tags: #DSP+FPGA, #Image #### 1. Requirements Analysis * **Real-time image processing technology**, especially real-time image processing technology based on multi-core DSP + FPGA architecture, has become a highly focused area in current new image processing technology research due to the inherent advantages of this solution. * Infrared images * Cell images * Image stitching #### 2. Overall Design Scheme: The FPGA is responsible for the logical control of video image acquisition and display; the DSP is responsible for implementing the image stitching algorithm; and data exchange between the FPGA and DSP is achieved by directly communicating between the FPGA's internal FIFO and the DSP's EMIFA interface. **2.1 DSP and FPGA Communication Interface Design** * This framework performs inter-core data interaction within the processor based on a data stream mode, using the high-speed transmission interface **SRIO** for communication with the FPGA. * Between multi-core DSPs and FPGAs, either the **uP --- ## DSP+ARM Dual-Core Power: Optimizing Your Applications - URL: https://intl.sienovo.cn/blog/87924615 - Date: 2019-02-25 - Tags: #DSP ARM, #AM5728 ####   Nowadays, application systems in fields such as machine/industrial vision, high-end measurement and testing, medical/bio-imaging, and avionics require extensive computation. In addition to robust display capabilities, they also demand very high signal processing power. Taking machine vision as an example, machine vision systems (e.g., automatic/visual inspection) require industry-standard APIs for optimized software reuse; high throughput capability to process massive data; system control and high-speed connectivity for sending inspection results or images; and the ability to prototype and adapt visual algorithms on a PC and easily connect with embedded environments. To meet these requirements, Texas Instruments (TI) has launched its new Integra™ series of DSP + ARM processors. The C6A816x Integra DSP + ARM processor not only delivers the industry's fastest single-core floating-point and fixed-point DSP performance at up to 1.5 GHz, but also integrates the industry's fastest s --- ## TI AM5728 OMAP Platform BSP Learning Notes - LCD Driver (1) - URL: https://intl.sienovo.cn/blog/87830458 - Date: 2019-02-20 - Tags: #AM5728, #LCD, #Driver, #OMAP, #AM5728LCD ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/87830458/01_618d5bb5b2ecfaf993abbe038e6d4f38.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/87830458/02_6da72f88ef836bda14701ee20c1a1fe0.png) Copyright Notice: This article is an original work by the blogger. Please cite the source when reprinting. Commercial use is not permitted without the blogger's permission. If you have any questions, feel free to point them out. https://blog.csdn.net/hsg\_\_tg2/article/details/86703168 The development board referenced in this article is the Sienovo XM5728-IDK-V3 series development board. The LCD driver is part of the Display Subsystem (DSS). DSS is an abbreviation for Display Subsystem. In the kernel, DSS can be implemented using either framebuffer or DRM, selectable through different configurations. This article will cover the basic knowledge of DSS, and later we will study the LCD driver code for porting. It's important to note that the display system is a modu --- ## Which is Better for Image Processing: FPGA or DSP? - URL: https://intl.sienovo.cn/blog/87745038 - Date: 2019-02-20 - Tags: #FPGA, #DSP, #ImageProcessing, #DigitalSignalProcessing DSPs focus on data processing, where algorithms are crucial. FPGAs primarily handle logic circuits. Many current frameworks are based on combined DSP and FPGA platforms, with DSPs managing algorithms and FPGAs handling logic timing. An FPGA can also perform DSP functions (DSP is the English abbreviation for Digital Signal Processing, and there isn't a significant difference between Digital Signal Processing and Digital Image Processing). This means you can use an FPGA for hardware design to implement the functions of a [DSP chip](https://www.baidu.com/s?wd=DSP%E8%8A%AF%E8%8A%AF%E7%89%87&tn=SE_PcZhidaonwhc_ngpagmjz&rsv_dl=gh_pc_zhidao). However, compared to specialized [DSP chips](https://www.baidu.com/s?wd=DSP%E8%8A%AF%E8%8A%AF%E7%89%87&tn=SE_PcZhidaonwhc_ngpagmjz&rsv_dl=gh_pc_zhidao), the cost can be too high. Therefore, there's no need to choose FPGA+DSP; simply selecting a [DSP chip](https://www.baidu.com/s?wd=DSP%E8%8A%AF%E8%8A%AF%E7%89%87&tn=SE_PcZhidaonwhc_ngpagmjz&rsv_dl=gh_pc_ --- ## Collection of DSP+ARM (OMAPL138) Industrial Applications, and How DSP and FPGA Collaborate - URL: https://intl.sienovo.cn/blog/87196323 - Date: 2019-02-13 - Tags: #OMAPL138, #DSP+ARM+FPGA, #C6748, #SPARTAN6 First, why is DSP needed? Instead of popular FPGA SoCs like ZYNQ 7000? Is it power consumption? Cost? Or specific application scenarios? **I. Industrial Image Acquisition and Recognition** * **Design and Implementation of a Digital Display Instrument Character Recognition System Based on OMAPL138: Character Image Recognition** * **Design and Implementation of an Elderly Care System Based on Video Image Analysis** **II. Communication** * **Development of an Underwater Acoustic Communication Signal Processing System** This article primarily focuses on driver development for the communication interface between the OMAP core board and FPGA, including GPIO control drivers and UPP data bus drivers for the interface. The character device drivers are designed using methods such as ioctl and memory mapping. For the OMAPL138 dual-core processor, DSPLINK is used for dual-core communication development in this paper, enabling data exchange and collaborative operation between the underw --- ## TI AM5728 SDK Upgrade: Linux Device Tree Parsing, Taking the Network Port CPSW as an Example - URL: https://intl.sienovo.cn/blog/86761811 - Date: 2019-02-09 - Tags: #DTS, #DTB, #AM5728, #DeviceTree ## TI AM5728 SDK Upgrade: Linux Device Tree Parsing, Taking the Network Port CPSW as an Example When working with Linux-based embedded systems, understanding the Linux device tree (DT) is crucial for device initialization and configuration. In this article, we will explore the Linux device tree parsing process, focusing on the network port CPSW (Common Platform Ethernet Switch) as an example. ### What is the Linux Device Tree? The Linux device tree is a data structure that describes the hardware components of a system, including their properties and relationships. It is used by the Linux kernel to initialize and configure devices during boot. The device tree is represented as a hierarchical structure, with nodes representing devices and properties representing their characteristics. ### Device Tree Compilation There are two ways to compile the device tree: 1. Copy the device tree file to the kernel source code directory `arch//boot/dts//` and ex --- ## AM335x Boot Process (BootRom->MLO->Uboot) In-depth Source Code Analysis - URL: https://intl.sienovo.cn/blog/86761479 - Date: 2019-02-03 - Tags: none Excellent writing, saving for study. References: 1. AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual.pdf; 2. am3359.pdf; **1. Where does the AM335x CPU jump to execute after power-on?** Answer: Chip to U-Boot boot process: ROM → MLO(SPL) → uboot.img The bootloader in AM335x is divided into 3 parts: **First-stage bootloader:** This bootloader automatically executes after the board powers on. It determines the boot method (e.g., NAND, SDcard, UART...) and then jumps to the second-stage bootloader. This code should be stored in the 176KB ROM. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/86761479/01_cc9a7560c724d6a3196f3cb260dd78ff.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/86761479/02_850ba788105232337e3e4b23ca7be18c.png) **Second-stage bootloader:** MLO (SPL), used for hardware initialization: disabling the watchdog, disabling interrupts, setting CPU clock frequency, speed, and other operations. It then jumps to the --- ## Fundamentals of UART, RS232, and RS485 - URL: https://intl.sienovo.cn/blog/86755590 - Date: 2019-02-03 - Tags: #UART, #RS485, #RS232 ## I. Relationship between UART, RS232, and RS485: Communication issues are like traffic. We can use public transportation as an analogy for serial communication. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/86755590/01_4f2b9c9db0940ce8c00a501d172af461.jpeg)      ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/86755590/02_3205c3ffc2adf7cb7a0d9e3f1f06e692.jpeg) Bus operation can be simply divided into two parts: 1. Bus stops 2. Roads The bus stops determine what is loaded onto the bus (people), how often it departs (schedule), etc. When a bus is on the road, it must follow road traffic rules. There are rules for crossing bridges, rules for highways, and these are unrelated to the bus stops. Returning to serial communication, UART is essentially equivalent to the bus stop, while RS232/RS485 correspond to the rules of the road. UART, or Universal Asynchronous Receiver/Transmitter, is a "device." Clearly, it's just a piece of hardware designed to per --- ## Understanding the CAN Bus - URL: https://intl.sienovo.cn/blog/86741664 - Date: 2019-02-01 - Tags: #CAN, #Bus ## Introduction The Controller Area Network (CAN) bus is a robust vehicle bus standard designed to facilitate communication among various electronic components without a host computer. Its applications have grown significantly in industrial and automotive environments due to its reliability and efficiency. This article delves into the physical structure and characteristics of the CAN bus, its signal representation, and key concepts that govern its operation. ## CAN Bus Physical Structure and Characteristics ### CAN Bus Network The CAN bus network operates primarily through two lines: CAN_H (high) and CAN_L (low). These lines enable serial differential signal transmission between nodes. To mitigate signal reflection and interference, it is essential to connect a 120-ohm termination resistor between CAN_H and CAN_L. This specific resistance value is chosen because it matches the characteristic impedance of the cable used in the network, ensuring optimal signal integrity. ### CAN Tra --- ## Sienovo TI AM5728 DCAN Driver Deep Dive - URL: https://intl.sienovo.cn/blog/86741348 - Date: 2019-02-01 - Tags: #DCAN, #AM5728, #TI, #Driver ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/86741348/01_14d016cb0dd8cecae2011fee8e6b1b23.png) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/86741348/02_55ce7a4381135be1b61e279478170b5b.png) Device Tree DTS:          can @481cc000 {             compatible = "ti,dra7-d\_can";             ti,hwmods = "dcan1";             reg = <0x4ae3c000 0x2000>;             syscon-raminit = <0x9 0x558 0x0>;             interrupts = <0x0 0xde 0x4>;             clocks = <0x10d>;             status = "disabled";             phandle = <0x209>;         };         can@481d0000 {             compatible = "ti,dra7-d\_can";             ti,hwmods = "dcan2";             reg = <0x48480000 0x2000>;             syscon-raminit = <0x9 0x558 0x1>;             interrupts = <0x0 0xe1 0x4>;             clocks = <0x11>;             status = "disabled";             phandle = <0x20a>;         }; ## **CAN Bus Testing Method** Execute the following comma --- ## Prospects and Application Survey of DSP+FPGA - URL: https://intl.sienovo.cn/blog/86716179 - Date: 2019-01-31 - Tags: #2048AICommunity, #JoinCommunity DSP+FPGA processing systems are widely used in complex signal processing fields. In areas such as radar signal processing and digital image processing, the real-time performance of signal processing is crucial. Due to the advantages of FPGA chips in processing large volumes of low-level algorithms and DSP chips in handling complex algorithms, the application of DSP+FPGA real-time signal processing systems is becoming increasingly widespread. The main advantages of DSP are programmability, low cost, and a large pool of available talent. FPGA's advantages include high performance, but this comes at a high cost. Furthermore, hardware design involves long cycles and a limited number of skilled professionals. A common advantage of DSP/FPGA is their real-time signal processing capability. Main application areas: complex signal processing, such as video processing, radar and sonar processing. Software-defined radio, Beidou satellite signal synthesis. DSP+FPGA is used to generate digita --- ## How TI's DSP+ARM Dual-Core Architecture Communicates - URL: https://intl.sienovo.cn/blog/86622753 - Date: 2019-01-24 - Tags: #DSP+ARM, #HeterogeneousMultiCoreComm, #AM5728, #OMAPL138, #DSP+FPGA+ARM, #2048AICommunity, #JoinCommunity ### 1 Introduction to Communication Architecture To address the complexity of current applications, SoC chips are better equipped to meet application and media demands, integrating numerous interfaces. ARM serves as the application processor for diverse application development, user interfaces, and interactions, while DSP is utilized for algorithm acceleration, particularly for media codec algorithm acceleration. This approach maintains algorithmic flexibility while providing powerful processing capabilities. Following its first series of Davinci chips, the DM644x, Texas Instruments (TI) successively launched a series of ARM+DSP or ARM+video co-processor multimedia processor platforms, including the DM643x, DM35x/36x, DM6467, OMAP35x, and OMAPLx. Many engineers with strong DSP development experience, as well as those with application processing development experience, have transitioned to developing products such as video surveillance, video conferencing, and portable multimedia term --- ## Reasons for Using Core Boards - URL: https://intl.sienovo.cn/blog/85218300 - Date: 2018-12-22 - Tags: #CoreBoards, #EmbeddedDevelopment, #IoT, #TI When developing a series of products across high, medium, and low tiers, a common challenge arises: the main chips might be ARM9, dual-core A9, and DSP, with their respective operating systems being µC/OS-II, Linux, and SysBIOS. Not only are the driver codes incompatible, but the application layer codes also differ. Consequently, merely maintaining these disparate codebases consumes significant human resources. Moreover, developers, constantly burdened by this heavy maintenance work, find it difficult to focus on the product itself and discover new innovation points. Traditional embedded development has a high barrier to entry. From hardware to software, from low-level drivers to various protocol stacks, middleware, and finally to applications, these are all essential skills for embedded development. For instance, using a new MCU requires reading thousands of pages of datasheets; using an OS necessitates delving deep into its principles and porting core low-level code; and for produc --- ## IPU Overview - URL: https://intl.sienovo.cn/blog/85038763 - Date: 2018-12-16 - Tags: none 1. IPU Overview (I) Architecture First, let's look at the overall system architecture diagram of the i.MX 6Q to understand the IPU's position within the entire SoC system: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/85038763/01_85626bf59613fee93a2ca105328e072b.png) As can be seen, the entire IPU is connected to the AXI and AHB buses, allowing it to communicate with modules such as ARM, VPU, GPU, and RAM via these buses. Additionally, each IPU has two camera interfaces, as shown below: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/85038763/02_3c3aafbf0cf60478e56091f6213ecfef.png) It controls LVDS screens via LDB, directly controls LCD screens, and can display content via HDMI or MIPI.   The function of the IPU is explained in the diagram below: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/85038763/03_40742905f89bcb41e5d606283ae52d15.png) Alternatively, the diagram below provides a clearer representation: ![](https://pub-048dcb96257 --- ## Comparison of ARM, DSP, and FPGA - URL: https://intl.sienovo.cn/blog/79339978 - Date: 2018-02-20 - Tags: #ARM, #DSP, #FPGA, #EmbeddedSystems In the field of [embedded](http://www.armlr.com/Intel/) development, ARM is a very popular microprocessor with extremely high market penetration. DSP and FPGA, on the other hand, serve as co-processors for embedded development, assisting microprocessors in better realizing product functionalities. So, what are the technical characteristics and differences among the three? Below is a brief introduction to this topic. 　　The ARM architecture was the first RISC microprocessor designed for the low-budget market, essentially becoming the industry standard for 32-bit microcontrollers. It offers a series of cores, architectural extensions, microprocessors, and system-on-chip solutions, with four functional modules that manufacturers can configure for production according to different user requirements. Since all products use a common software architecture, the same software can run across all products. Currently, ARM holds over 90% of the handheld device market, effectively shortening applica --- ## How to Change Time Zone and Time on Ubuntu - URL: https://intl.sienovo.cn/blog/52103445 - Date: 2016-08-03 - Tags: #RSpaceCreatorCommunity, #JoinCommunity 1. First, check the current time zone: swfsadmin@swfsubuntu:~$ date -R Tue, 17 Dec 2013 18:23:01 +0800 To change the time zone, run `sudo tzselect`. 2. Select region: Asia swfsadmin@swfsubuntu:~$ sudo tzselect \[sudo\] password for swfsadmin: Sorry, try again. \[sudo\] password for swfsadmin: Please identify a location so that time zone rules can be set correctly. Please select a continent or ocean. 1) Africa 2) Americas 3) Antarctica 4) Arctic Ocean 5) Asia 6) Atlantic Ocean 7) Australia 8) Europe 9) Indian Ocean 10) Pacific Ocean 11) none - I want to specify the time zone using the Posix TZ format. #? 5 3. Select country: China Please select a country. 1) Afghanistan 18) Israel 35) Palestine 2) Armenia 19) Japan 36) Philippines 3) Azerbaijan 20) Jordan 37) Qatar 4) Bahrain 21) Kazakhstan 38) Russia 5) Bangladesh 22) Korea (North) 39) Saud --- ## Setting Up an HTTPS Server Using Nginx - URL: https://intl.sienovo.cn/blog/45693443 - Date: 2015-05-13 - Tags: #WebSecurity, #Nginx, #SSL, #DevOps Recently, I've been researching Nginx and encountered a requirement to encrypt data transmitted between the server and clients to prevent information leakage from intermediate eavesdropping. However, purchasing certificates from official certificate authorities was not cost-effective since only internal personnel access the server. Therefore, I decided to self-sign the certificate and simply ignore the browser's trust warnings. Below are the steps for generating the certificate and configuring Nginx. First, ensure that OpenSSL and OpenSSL-devel are installed on your system: ```bash #yum install openssl #yum install openssl-devel ``` Next, generate a self-signed certificate: ```bash #cd /etc/nginx/nginxhttps #openssl genrsa -des3 -out server.key 1024 #openssl req -new -key server.key -out server.csr #openssl rsa -in server.key -out server_nopwd.key #openssl x509 -req -days 365 -in server.csr -signkey server_nopwd.key -out server.crt ``` The certificate is now generated. Next, conf --- ## How to Configure HTTPS for Tomcat on Ubuntu - URL: https://intl.sienovo.cn/blog/45691257 - Date: 2015-05-13 - Tags: #UbuntuTomcatHTTPS **References:** http://www.cnblogs.com/xwdreamer/p/3466661.html (The latter half needs correction) [http://tomcat.apache.org/tomcat-7.0-doc/ssl-howto.html](http://tomcat.apache.org/tomcat-7.0-doc/ssl-howto.html) [http://blog.sina.com.cn/s/blog\_682b5aa1010113uu.html](http://blog.sina.com.cn/s/blog_682b5aa1010113uu.html) (Chinese, quite practical) [https://help.ubuntu.com/community/TomcatSSL](https://help.ubuntu.com/community/TomcatSSL) [http://blog.csdn.net/fjssharpsword/article/details/6851969](http://blog.csdn.net/fjssharpsword/article/details/6851969) (Server and client certificates) **Background** This article uses an Ubuntu environment as an example; the specific environment is as follows: OS: ubuntu-server\_12.04 TOMCAT\_HOME:/usr/local/tomcat7, For installation instructions, refer to: [Registering Tomcat as a Service on Windows and Linux](http://www.cnblogs.com/xwdreamer/p/3411986.html) JAVA\_HOME:/usr/lib/jvm/jdk1.7.0\_45, For installation instructions, refer to: [In --- ## Three Steps to Quickly Set Up an Android Development Environment (Download Package Includes Ready-to-Use SDK – No Need to Visit Google Sites, Convenient!) - URL: https://intl.sienovo.cn/blog/45371717 - Date: 2015-04-29 - Tags: #AndroidDev, #SDK, #DevelopmentEnvironment ## Three Steps to Quickly Set Up an Android Development Environment Setting up an Android development environment can be a straightforward process if you follow the right steps. In this guide, we will walk you through the essential steps to download and configure the Android Development Tools (ADT) bundle, which includes a ready-to-use SDK and Eclipse IDE. This setup eliminates the need to navigate through various Google sites, making it convenient for developers. ### Step 1: Download the ADT Bundle To get started, you need to download the ADT bundle, which contains everything you need to begin Android development. You can find the ADT bundle at the following link: - [Download ADT Bundle](http://blog.csdn.net/LANG791534167/article/details/45061509) Look for the file named `adt-bundle-windows-x86_64-20140321.zip`. This package is approximately 510.0 MB and includes an all-in-one Android development package suitable for versions 4.2 and possibly 4.4. **Note:** The included Eclipse --- ## Summary of Multithreaded Programming - URL: https://intl.sienovo.cn/blog/45032199 - Date: 2015-04-13 - Tags: #Multithreading ## Understanding Multithreaded Programming with pthread_join Multithreaded programming is a fundamental concept in concurrent programming, allowing a program to execute multiple threads or flows of execution concurrently. This can significantly improve the responsiveness and efficiency of a program, especially when dealing with computationally intensive tasks. However, multithreaded programming also introduces complexities, such as synchronization and thread management. In this article, we will explore the role of `pthread_join` in ensuring that created threads have the opportunity to execute. ### The Importance of pthread_join In multithreaded programming, threads are created and managed using the POSIX Threads library, which provides a set of APIs for thread creation, synchronization, and management. One of the critical functions in this library is `pthread_join`, which allows a thread to wait for the completion of another thread. Without `pthread_join` in the code, the main threa --- ## Explaining the Socket send and recv Functions from a Protocol Perspective - URL: https://intl.sienovo.cn/blog/45031625 - Date: 2015-04-13 - Tags: #Networking, #SocketDev, #TCPIP ## ### 1. send Function **int send(SOCKET s, const char FAR \*buf, int len, int flags);** Both client and server applications use the send function to transmit data to the other end of a TCP connection. Typically, client programs use send to send requests to the server, while servers use send to send responses back to clients. The first parameter of this function specifies the sending socket descriptor; The second parameter points to a buffer containing the application data to be sent; The third parameter indicates the number of bytes of data to actually send; The fourth parameter is usually set to 0. Here, we only describe the execution flow of the send function for synchronous sockets. When this function is called: (1) send first compares the length of data to be sent (`len`) with the size of the socket `s`'s send buffer. If `len` is greater than the send buffer size, the function returns `SOCKET_ERROR`; (2) If `len` is less than or equal to the send buffer siz --- ## Differences Among HTTP GET, POST, PUT, and DELETE - URL: https://intl.sienovo.cn/blog/44985403 - Date: 2015-04-10 - Tags: #HTTP, #WebDev, #REST ## Understanding HTTP Request Methods: GET, POST, PUT, and DELETE When interacting with web resources, it's essential to understand the different HTTP request methods at your disposal. In this article, we'll delve into the four primary methods: GET, POST, PUT, and DELETE, and explore their respective uses in web development. ### Background on HTTP Request Methods HTTP (Hypertext Transfer Protocol) is a request-response protocol used for transferring data over the web. It relies on a client-server architecture, where the client (usually a web browser) sends a request to the server, which then responds with the requested data. HTTP request methods are used to specify the action the client wants the server to perform on a particular resource. ### Retrieving Resources: GET The GET method is used to retrieve a resource from the server. It's the most commonly used HTTP request method and is often used for web browsing. When a user enters a URL into their browser, the browser sends a GET --- ## How Does a Mobile Phone Access the Internet? How Does 3G Establish a TCP Connection? How Does 3G Establish an HTTP Connection? - URL: https://intl.sienovo.cn/blog/44851663 - Date: 2015-04-03 - Tags: #Networking, #TCP, #HTTP, #3G Best answer from Zhihu: [http://www.zhihujingxuan.com/23124.html](http://www.zhihujingxuan.com/23124.html) ### [TCP Connection, HTTP Connection, and Socket Connection](http://www.blogjava.net/thisliy/archive/2009/11/08/301615.html) [http://www.blogjava.net/thisliy/archive/2009/11/08/301615.html](http://www.blogjava.net/thisliy/archive/2009/11/08/301615.html) Socket Communication Between Android Client and Server Based on TCP/IP Protocol [http://blog.csdn.net/ryantang03/article/details/8274517](http://blog.csdn.net/ryantang03/article/details/8274517) Embedded CDMA Wireless Terminal with TCP/IP Protocol [http://www.ednchina.com/ART_24871_29_20027_AN_57a2cee9.HTM](http://www.ednchina.com/ART_24871_29_20027_AN_57a2cee9.HTM) --- ## Comprehensive Guide to C Language String Operations (Very Detailed) - URL: https://intl.sienovo.cn/blog/44778771 - Date: 2015-03-31 - Tags: #CProgramming, #StringManipulation, #C++ ## Comprehensive Guide to C Language String Operations Strings in C can often be a challenging aspect of programming, but understanding how to manipulate them is crucial for effective coding. This guide will cover essential string operations, conversion functions, and character checks in C, providing examples to illustrate each concept. ## 1) String Operations C provides a variety of functions for string manipulation, which are defined in the `` header file. Below are some of the most commonly used string functions: - **`strcpy(p, p1)`**: Copies the string from `p1` to `p`. ```c #include #include void main(void) { char str1[10] = { "TsinghuaOK" }; char str2[10] = { "Computer" }; cout << strcpy(str1, str2) << endl; // Output: Computer } ``` **Note**: The destination array must be large enough to hold the source string. - **`strncpy(p, p1, n)`**: Copies the first `n` characters from `p1` to `p`. ```c #in --- ## Understanding pthread_cond_wait() and pthread_cond_signal() - URL: https://intl.sienovo.cn/blog/44650705 - Date: 2015-03-26 - Tags: none ## Understanding `pthread_cond_wait()` and `pthread_cond_signal()` In this article, we will delve into the functions `pthread_cond_wait()` and `pthread_cond_signal()`, which are crucial for managing thread synchronization in multi-threaded applications using POSIX threads (pthreads). Understanding these functions will help you effectively coordinate the execution of threads and avoid common pitfalls such as race conditions and deadlocks. ### `pthread_cond_wait()` The `pthread_cond_wait()` function is used to block the current thread until another thread signals it to wake up. This function is typically used in scenarios where a thread needs to wait for a certain condition to be met before it can proceed with its execution. Here’s how it works: - **Mutex Requirement**: `pthread_cond_wait()` must be used in conjunction with a `pthread_mutex`. This ensures that the condition variable is protected from concurrent access. - **Automatic Mutex Release**: When a thread calls `pthread_co --- ## HTTP Request Returns and Parses JSON Data - URL: https://intl.sienovo.cn/blog/42391669 - Date: 2015-01-04 - Tags: none ```java /* Note the difference in sending GET and POST requests * 1. Create an HttpGet (or HttpPost) object, passing the URL to be requested into the HttpGet (or HttpPost) object via its constructor; 2. Use the execute method of the DefaultHttpClient class to send an HTTP GET or HTTP POST request and return an HttpResponse object; 3. Retrieve the response information via the getEntity method of the HttpResponse interface. * */ public class TestHttpActivity extends Activity { private Button btn_get; private Button btn_post; @Override public void onCreate(Bundle savedInstanceState) { super.onCreate(savedInstanceState); setContentView(R.layout.main); btn_get=(Button)findViewById(R.id.btn_get); btn_post=(Button)findViewById(R.id.btn_post); btn_get.setOnClickListener(listener); btn_post.setOnClickListener(listener); } private OnClickListener listener=new OnClickListener() { @Override public void onClick(View v) { switch (v --- ## Connection to http://dl-ssl.google.com refused - URL: https://intl.sienovo.cn/blog/40112741 - Date: 2014-10-15 - Tags: #Networking, #DevelopmentTips ## Troubleshooting Connection Issues to dl-ssl.google.com If you're facing difficulties connecting to `dl-ssl.google.com`, you're not alone. This issue can arise due to various network configurations or proxy settings. In this post, we will explore a few practical solutions that can help you resolve this problem and get back to your development work seamlessly. ### Step 1: Update the Hosts File One effective way to bypass connection issues is to modify your system's hosts file. This file allows you to map hostnames to IP addresses directly. Here’s how to do it: 1. Open the hosts file located at `/windows/system32/drivers/etc/hosts` using a text editor with administrative privileges. 2. Add the following lines to the file: ``` 203.208.46.146 www.google.com 203.208.46.146 dl.google.com 203.208.46.146 dl-ssl.google.com 74.125.113.121 developer.android.com ``` This step redirects requests for these domains to the specified IP addresses, potentially resolving connect --- ## android: Online Source Code Viewing Addresses - URL: https://intl.sienovo.cn/blog/39613645 - Date: 2014-09-27 - Tags: none ## Online Source Code Viewing Addresses for Android When working with Android development, having access to the source code is essential for debugging, optimization, and learning. In this article, we will explore two popular online resources for viewing Android source code: code.metager.de and androidxref.com. ### Viewing Android Source Code Online Android source code can be viewed online through the following websites: #### [http://code.metager.de/source/xref/android/](http://code.metager.de/source/xref/android/) This website provides a browsable version of the Android source code. It allows users to navigate through the codebase, view individual files, and search for specific functions or variables. #### [http://androidxref.com/](http://androidxref.com/) androidxref.com is another popular online resource for viewing Android source code. It offers a similar browsing experience to code.metager.de, with additional features such as code search and a repository of Android-related d --- ## MAC ,PHY, MII - URL: https://intl.sienovo.cn/blog/38661137 - Date: 2014-08-18 - Tags: none MAC and PHY handle the lowest two layers of the OSI seven-layer network model. (I) The PHY is responsible for electrical signal conversion, line status, data encoding, etc. When transmitting data, the PHY receives data from the MAC (for the PHY, there is no concept of frames; it treats everything as data, regardless of addresses, data content, or CRC). It adds a 1-bit error detection code for every 4 bits, then converts parallel data into a serial stream, encodes the data according to physical layer encoding rules (NRZ encoding for 10BASE-T or Manchester encoding for 100BASE-T), and finally converts it into an analog signal for transmission. The process is reversed when receiving data. (II) The MAC is responsible for frame assembly, CRC checking, interfacing with the IP protocol layer, addressing mechanisms, etc. The data link layer chip in an Ethernet card is called a MAC controller. In many network cards, these two parts are integrated. Their relationship is that the PCI bus conne --- ## When and Where are Network Hardware Timestamps Applied? - URL: https://intl.sienovo.cn/blog/38657483 - Date: 2014-08-18 - Tags: none This post is divided into several sections: 1. Linux Time System 2. Network Card Working Principle 3. Hardware Timestamp Options in Socket Programming 4. When and Where are Network Hardware Timestamps Applied? ### 1. Linux Time System Chen Lijun's "In-depth Analysis of Linux Kernel Source Code" includes an excellent article: [Linux Time System](http://www.eefocus.com/article/09-06/74890s.html) Linux has two clock sources: RTC and OS clock. The RTC (Real-Time Clock) is independent of the operating system and powered by a battery, allowing it to maintain its time even when the system is powered off. The Linux system obtains its initial time value from the RTC during startup. The OS clock obtains its timing from a programmable counter (such as Intel's 8524). The output pulses shown in Figure 1 form the basis of the OS clock's operation, as they generate clock interrupts. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/38657483/01_20140818134845205.png) Figure 1: --- ## Understanding the exec Family of Functions - URL: https://intl.sienovo.cn/blog/38445005 - Date: 2014-08-08 - Tags: none ## Understanding the exec Family of Functions in Linux In Linux, processes utilize the `exec` family of functions to initiate the execution of another program. This article will delve into the `exec` family, focusing on how these functions work, particularly `execve()`, and the implications of using them in a process lifecycle. By the end, you will have a clearer understanding of how to use these functions effectively in your applications. ### Overview of exec Functions The `exec` family of functions includes several variants: `execl`, `execlp`, `execle`, `execv`, `execve`, and `execvp`. Each of these functions serves the purpose of replacing the current process image with a new process image, but they differ in how they handle arguments and environment variables. - **`execl`**: This function takes a variable number of arguments, ending with a NULL pointer. It is useful when you know the exact number of arguments at compile time. - **`execlp`**: Similar to `execl`, but it searches --- ## The Relationship Between Socket Connections and TCP Connections - URL: https://intl.sienovo.cn/blog/38426135 - Date: 2014-08-07 - Tags: none When transmitting data, we can use only the (transport layer) TCP/IP protocol. However, without an application layer, the data content cannot be recognized. For the transmitted data to be meaningful, an application layer protocol must be used. There are many application layer protocols, such as HTTP, FTP, TELNET, etc., and custom application layer protocols can also be defined. The web uses the HTTP protocol as the application layer protocol to encapsulate HTTP text information, and then uses TCP/IP as the transport layer protocol to send it over the network. 1) A Socket is an interface for TCP and UDP programming; you can use it to establish TCP connections and so on. TCP and UDP protocols belong to the transport layer. HTTP, on the other hand, is an application layer protocol, and it is actually built on top of the TCP protocol. (HTTP is like a car, providing the specific form for encapsulating or displaying data; Socket is like an engine, providing network communication capabiliti --- ## Difference Between Multithreading and Multiprocessing - URL: https://intl.sienovo.cn/blog/38318709 - Date: 2014-07-31 - Tags: none (This is a key question—what interviewers care about the most. You must answer comprehensively from various aspects such as CPU scheduling, context switching, data sharing, multi-core CPU utilization, resource consumption, etc. Then, there's one question that will definitely come up: *What resources are private to a thread?* The answer must include *registers*, or you're in trouble.) **Reentrancy**: There isn't a widely accepted formal definition for this concept, but reentrancy imposes stricter requirements than thread safety. Based on practical experience, "reentrancy" commonly refers to the following scenario: when a program is executing a certain function `foo()`, it receives a signal, causing the currently running function to pause and transfer control to a signal handler. During the execution of this signal handler, it happens to call the same function `foo()` again—this is known as reentrancy. If `foo()` can execute correctly in this nested context, and the previously suspende --- ## Difference between Buffer and Cache - URL: https://intl.sienovo.cn/blog/38313929 - Date: 2014-07-31 - Tags: none ### I. `free` command ```bash [root@xen_202_12 /]# free -m total used free shared buffers cached Mem: 3072 2459 612 0 207 1803 -/+ buffers/cache: 447 2624 Swap: 1913 0 1913 ``` Line 2: total memory: 3072 used memory: 2459 free memory: 612 shared: currently unused, always 0 buffers: Buffer Cache memory: 207 cached: Page Cache memory: 1803 Relationship: total = used + free Line 3: Meaning of -/+ buffers/cache: -buffers/cache memory: 447 (equals used - buffers - cached from line 1) +buffers/cache memory: 2624 (equals free + buffers + cached from line 1) Note: The memory values calculated using the above formulas show slight discrepancies (reason unknown). It can be seen that -buffers/cache reflects the memory actually consumed by applications, while +buffers/cache reflects the total available memory that can be repurposed. Line 4 specifically addresses the sw --- ## Illustrated Linux Boot Process - URL: https://intl.sienovo.cn/blog/37901567 - Date: 2014-07-17 - Tags: none ### Overview ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/37901567/01_20140717100741860.png) Figure 1: High-Level View of the Linux System Process ### Stage 1 Boot Loader The primary boot loader in the MBR is a 512-byte image containing program code and a small partition table (see Figure 2). The first 446 bytes constitute the primary boot loader, which includes executable code and error message text. The next 64 bytes form the partition table, containing records for 4 partitions (each record is 16 bytes in size). The MBR ends with two special bytes (0xAA55). This number is used to validate the MBR. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/37901567/02_20140717101119703.png) Figure 2: MBR Anatomy ### Stage 2 Boot Loader The secondary boot loader (Stage 2 boot loader) can be more aptly called the kernel loader. The task of this stage is to **load the Linux kernel and the optional initial RAM disk**. ### GRUB Stage Boot Loader The `/boot/grub --- ## Linux Initial RAM Disk (initrd) Overview - URL: https://intl.sienovo.cn/blog/37901337 - Date: 2014-07-17 - Tags: none ## [Original Link](http://www.ibm.com/developerworks/cn/linux/l-initrd.html) ### Using the Initial RAM Disk to Boot the System Now that we understand how to build and use a custom initial RAM disk, this section will explore how the kernel identifies initrd and mounts it as the root file system. We will introduce several key functions in the boot chain and explain what operations are performed. Bootloaders, such as GRUB, define the kernel to be loaded and copy the kernel image along with the associated initrd into memory. Much of this functionality can be found in the `./init` subdirectory of the Linux kernel source directory. After the kernel and initrd images are decompressed and copied into memory, the kernel is invoked. It performs various initialization operations, eventually leading to the `init/main.c:init()` (subdir/file:function) function. This function performs a large number of subsystem initialization operations. Here, a call to `init/do_mounts.c:prepare_namespace()` is --- ## Principles of Sharing Dynamic Link Libraries Among Multiple Processes - URL: https://intl.sienovo.cn/blog/37657937 - Date: 2014-07-10 - Tags: none [Principles of Sharing Dynamic Link Libraries Among Multiple Processes](http://blog.chinaunix.net/uid-26983585-id-3364514.html)  This was a question my director asked me during an interview. I've been busy these past few days and haven't had a chance to read much. Today, let's summarize this question: Why can one process continue to use a dynamic link library (DLL) after another process has finished with it? My answer at the time was vague and only half-correct. Let's properly summarize it here. As we've discussed before, there are several ways for inter-process communication (IPC). In fact, the dynamic link library (DLL) mechanism we are discussing now is also one form of IPC. Whether it's Windows or Linux operating systems, the underlying principles of all operating systems are essentially the same. Dynamic Link Libraries (DLLs) are fundamental to the Windows operating system, with most Windows APIs provided in DLL form. Generally, DLLs cannot be executed directly or receive messag --- ## Learning Methods of Excellent Programmers - URL: https://intl.sienovo.cn/blog/37594909 - Date: 2014-07-09 - Tags: none Every experienced engineer has wrestled with the same frustration: you read a chapter, nod along, close the book — and then can't explain the concept to anyone the next morning. The gap between passive exposure and genuine understanding is where most self-taught developers stall. This post distills four hard-won learning habits that separate programmers who keep growing from those who plateau. ## 1. Repetition Is Not a Sign of Weakness For deep technical domains — OS kernels, compilers, distributed consensus algorithms, numerical methods — a single pass through the material is almost always insufficient. The concepts are dense, the mental models are unfamiliar, and the vocabulary itself is a barrier on the first read. The practical prescription: identify the top three books or authoritative references on the topic and cycle through them repeatedly. On a second reading you will notice things invisible on the first. On a third, patterns emerge that connect earlier chapters to later on --- ## In-depth Understanding of pthread_cond_wait and pthread_cond_signal - URL: https://intl.sienovo.cn/blog/37593533 - Date: 2014-07-09 - Tags: none ===============================Explanation from man pthread_cond_wait========================== In a LINUX environment, multithreaded programming will inevitably encounter situations requiring condition variables, which necessitates the use of the `pthread_cond_wait()` function. However, the execution process of this function can be difficult to understand. The workflow of `pthread_cond_wait()` is as follows (using the EXAMPLE from the MAN page): Consider two shared variables x and y, protected by the mutex mut, and a condition vari- able cond that is to be signaled whenever x becomes greater than y. int x,y; pthread_mutex_t mut = PTHREAD_MUTEX_INITIALIZER; pthread_cond_t cond = PTHREAD_COND_INITIALIZER; Waiting until x is greater than y is performed as follows: pthread_mutex_lock(&mut); while (x <= y) { pthread_cond_wait(&cond, &mut); } /* operate on x and y */ --- ## Makefile $@ $^ $< .c.o Variable Practice - URL: https://intl.sienovo.cn/blog/36898505 - Date: 2014-07-04 - Tags: none Let's assume we have a program like the following, with source code as shown: ```c /* main.c */ #include "mytool1.h" #include "mytool2.h" int main(int argc, char **argv) { mytool1_print("hello"); mytool2_print("hello"); } /* mytool1.h */ #ifndef _MYTOOL_1_H #define _MYTOOL_1_H void mytool1_print(char *print_str); #endif /* mytool1.c */ #include "mytool1.h" void mytool1_print(char *print_str) { printf("This is mytool1 print %s ", print_str); } /* mytool2.h */ #ifndef _MYTOOL_2_H #define _MYTOOL_2_H void mytool2_print(char *print_str); #endif /* mytool2.c */ #include "mytool2.h" void mytool2_print(char *print_str) { printf("This is mytool2 print %s ", print_str); } ``` Of course, since this program is very short, we can compile it like this: ```bash gcc -c main.c gcc -c mytool1.c gcc -c mytool2.c gcc -o main main.o mytool1.o mytool2.o ``` This way, we can also generate the `main` program, and it's not too much trouble. However, what if we consider a scena --- ## Linux Boot Process and a Brief Understanding of the /etc/rc.d/init.d/ Directory - URL: https://intl.sienovo.cn/blog/36885497 - Date: 2014-07-04 - Tags: #LinuxBoot, #InitD, #Runlevels ### The contents of rc.d are as follows: init.d/: Directory for binary files of various servers and programs. rcx.d/: Directory for executable program links for each runlevel. The contents are all symbolic links pointing to files in init.d/. Details will be described later. There are also three scripts: rc.sysinit, rc, rc.local The Red Hat boot method and execution order are: Load kernel Execute init program /etc/rc.d/rc.sysinit # The first script executed by init /etc/rc.d/rc RUNLEVEL # RUNLEVEL is the default runlevel /etc/rc.d/rc.local /sbin/mingetty # Wait for user login In Red Hat, /etc/rc.d/rc.sysinit primarily performs initialization tasks common to all runlevels, including: Load keymap and system fonts Start swapping Set hostname Set NIS domain Check (fsck) and mount file systems Enable quotas Load sound card modules Set system clock And so on. /etc/rc.d/rc then executes scripts in the corresponding directory based on the runlevel specified by its parameter (which you can --- ## Linux Soft Links and Hard Links - URL: https://intl.sienovo.cn/blog/36419727 - Date: 2014-07-02 - Tags: #Linux, #SoftLink, #HardLink 1. Linux Link Concepts Linux links are divided into two types: hard links and symbolic links. By default, the `ln` command creates hard links. ### Hard Links Hard links connect files via their inode numbers. In the Linux file system, every file stored on a disk partition, regardless of its type, is assigned a unique number called an inode number (Inode Index). In Linux, it is possible for multiple filenames to point to the same inode. This type of connection is generally a hard link. The purpose of hard links is to allow a single file to have multiple valid pathnames, enabling users to create hard links to important files to prevent accidental deletion. As mentioned, this is because the inode corresponding to the directory has more than one link. Deleting just one link does not affect the inode itself or other links. Only when the last link is removed are the file's data blocks and directory entries released. In other words, a file is truly deleted only when all associated hard link --- ## linux find - URL: https://intl.sienovo.cn/blog/36186695 - Date: 2014-07-01 - Tags: none * `pathname`: The directory path to search for files. * `-options`: Options to specify the search criteria. * `-print`: Print the matched files to the standard output. * `-exec`: Execute a shell command on the matched files. * `-ok`: Similar to `-exec`, but prompts the user for confirmation before executing the command. Some common options used with `find` include: * `-name`: Search for files by name. * `-perm`: Search for files by permissions. * `-user`: Search for files owned by a specific user. * `-group`: Search for files owned by a specific group. * `-mtime`: Search for files modified within a specified time range. * `-size`: Search for files of a specified size. * `-nogroup`: Search for files without a valid group. * `-newer`: Search for files modified after a specified file. * `-depth`: Search for files in the specified directory and its subdirectories. Here are some examples of using `find`: --- ## Segmentation Fault and Coredump Debugging - URL: https://intl.sienovo.cn/blog/34115971 - Date: 2014-06-24 - Tags: none ## Segmentation Fault A [segmentation fault](http://baike.baidu.com/view/120927.htm) refers to accessing [memory](http://baike.baidu.com/view/1082.htm) beyond the memory space allocated to a program by the system. This value is typically stored in the GDTR (Global Descriptor Table Register), which is a 48-bit register. The 32 bits of the GDTR store the base address of the [GDT](http://baike.baidu.com/view/1082.htm) it points to, the next 13 bits store the index corresponding to the GDT, and the last 3 bits include information such as whether the program is in memory, and its privilege level in the [CPU](http://baike.baidu.com/view/2089.htm). The GDT pointed to by the GDTR is a table where each entry is 64 bits. This table stores information such as the starting addresses of the program's [code segment](http://baike.baidu.com/view/1315853.htm) and [data segment](http://baike.baidu.com/view/1005328.htm), along with corresponding segment limits, paging information, program privilege l --- ## maKefile Learning: An Introduction - URL: https://intl.sienovo.cn/blog/32692649 - Date: 2014-06-20 - Tags: none ## maKefile Learning: An Introduction As a beginner in the world of Makefiles, it can be overwhelming to learn the basics and understand how to use them effectively. Makefiles are a crucial part of any build process, allowing you to automate tasks and simplify the compilation of complex projects. In this article, we will provide an introduction to maKefiles, a simplified guide to learning Makefiles, and explore the basics of how they work. ### What is a Makefile? A Makefile is a text file that contains a set of instructions, or "recipes," that are used to build and compile projects. It is a powerful tool that allows you to automate tasks, such as compiling code, running tests, and creating documentation. Makefiles are typically used in conjunction with the `make` command, which reads the Makefile and executes the instructions contained within. ### Benefits of Using Makefiles Using Makefiles offers several benefits, including: * **Automation**: Makefiles allow you to automate repe --- ## Understanding Condition Variables - URL: https://intl.sienovo.cn/blog/32101815 - Date: 2014-06-18 - Tags: #TechnicalArticle ### Understanding the role of `pthread_cond_wait()` is crucial – it's the core, and often the most challenging part, of the POSIX thread signaling system. First, let's consider the following scenario: a thread has locked a mutex to inspect a linked list, but the list happens to be empty. This particular thread can't do anything – its design intent is to remove nodes from the list, but there are no nodes currently. Therefore, it can only: While holding the mutex, the thread will call `pthread_cond_wait(&mycond, &mymutex)`. The `pthread_cond_wait()` call is quite complex, so we'll go through its operations one at a time. The **first thing** `pthread_cond_wait()` does is simultaneously unlock the mutex (allowing other threads to modify the linked list) and wait for the condition `mycond` to occur (so that when `pthread_cond_wait()` receives a "signal" from another thread, it will wake up). Now that the mutex is unlocked, other threads can access and modify the linked list, potentially --- ## Completely Uninstall MySQL on Ubuntu - URL: https://intl.sienovo.cn/blog/26371817 - Date: 2014-05-20 - Tags: #Ubuntu, #MySQL [Completely Uninstall MySQL on Ubuntu](http://www.blogjava.net/yjhmily/articles/336926.html) 1. Remove MySQL ``` 1  sudo apt \- get autoremove  \-- purge mysql \- server \- 5.0 2  sudo apt \- get remove mysql \- server 3  sudo apt \- get autoremove mysql \- server 4  sudo apt \- get remove mysql \- common (非常重要) ``` Some of the above steps might be redundant, but it's recommended to execute them in order. Clean up residual data ``` dpkg  \- l  | grep  ^ rc | awk  ' {print $2} '   | sudo xargs dpkg  \- P ``` Note: ``` dpkg: warning: while removing mysql-common, directory '/etc/mysql' not empty so not removed. ``` Manually rename debian.cnf to disable it: ``` yeyuangen@ubuntu:/$ cd /etc/mysql/ yeyuangen@ubuntu:/etc/mysql$ ls debian.cnf yeyuangen@ubuntu:/etc/mysql$ mv debian.cnf debian.cnf1 ``` 2. Install MySQL ``` 1  sudo apt \- get install mysql \- server 2  sudo apt \- get install mysql \- client 3  sudo apt \- get install php5 \- mysql (安装php5-mysql 是将php和mysql连接起来  ) ``` --- ## Recursive and Non-recursive Implementations of Binary Tree Traversal (C Language) - URL: https://intl.sienovo.cn/blog/26363235 - Date: 2014-05-20 - Tags: #BinaryTree, #Traversal, #Recursive, #NonRecursive ```cpp /* * Description: * Related operations for a Binary Search Tree (creation, node insertion, pre-order, in-order, and post-order recursive and non-recursive binary tree traversal) * Author :FinL * Language: C * Date : 2010-08-29 */ #include#include typedef struct Node{ int data; Node *leftchild; Node *rightchild;}Node; /* Initialize a binary search tree. */void InitBinaryTree(Node**root,int elem){ *root=(Node*)malloc(sizeof(Node)); if(!(*root)) { printf("Memory allocation for root failed.\n"); return; } (*root)->data=elem; (*root)->leftchild=NULL; (*root)->rightchild=NULL;} /* Insert a node into the binary search tree. */void InsertNode(Node *root,int elem){ Node *newnode=NULL; Node *p=root,*last_p=NULL; newnode=(Node*)malloc(sizeof(Node)); if(!newnode) { printf("Memory allocation for newnode failed.\n"); return; } newnode->data=elem; newnode->leftchild=NULL; newnode->rightchild=NULL; while(NULL!=p) { last_p=p; if(newnode->datadata) --- ## Given a binary tree with post-order traversal sequence DABEC and in-order traversal sequence DEBAC, its pre-order traversal sequence is: - URL: https://intl.sienovo.cn/blog/26247397 - Date: 2014-05-19 - Tags: none ## Determining the Pre-Order Traversal Sequence of a Binary Tree Given a binary tree with post-order traversal sequence DABEC and in-order traversal sequence DEBAC, you might be wondering how to find its pre-order traversal sequence. In this article, we will walk you through the step-by-step process of determining the pre-order traversal sequence using the given post-order and in-order traversal sequences. To start, let's recall the definitions of post-order and in-order traversal: * Post-order traversal: Left-Right-Root * In-order traversal: Left-Root-Right With these definitions in mind, let's analyze the given post-order traversal sequence DABEC and in-order traversal sequence DEBAC. ### Step 1: Identify the Root Node From the post-order traversal sequence DABEC, we can see that C is the root node. This is because the post-order traversal sequence starts with the leftmost node, which is D, followed by the rightmost node, which is E, and finally the root node, C. ### Step 2: D --- ## Given that the postorder traversal sequence of a binary tree is DABEC and the inorder traversal sequence is DEBAC, what is its preorder traversal sequence? - URL: https://intl.sienovo.cn/blog/26247201 - Date: 2014-05-19 - Tags: none ## Understanding Binary Tree Traversals: From Postorder and Inorder to Preorder In this article, we will explore how to derive the preorder traversal sequence of a binary tree when given its postorder and inorder traversal sequences. Specifically, we will analyze the postorder sequence DABEC and the inorder sequence DEBAC, and we will learn how to reconstruct the binary tree and determine its preorder traversal sequence. ### Binary Tree Traversal Definitions Before diving into the solution, it’s essential to understand the different types of tree traversals: - **Postorder Traversal (Left-Right-Root)**: In this traversal method, we visit the left subtree first, then the right subtree, and finally the root node. For our example, the postorder sequence is DABEC. - **Inorder Traversal (Left-Root-Right)**: In this method, we visit the left subtree, then the root node, and finally the right subtree. The inorder sequence we have is DEBAC. ### Step-by-Step Reconstruction of the Binary --- ## The break Statement - URL: https://intl.sienovo.cn/blog/21964443 - Date: 2014-03-24 - Tags: none [The break statement](http://zhidao.baidu.com/search?word=break%E8%AF%AD%E5%8F%A5&fr=qb_search_exp&ie=utf8) [The break statement](http://zhidao.baidu.com/search?word=break%E8%AF%AD%E5%8F%A5&fr=qb_search_exp&ie=utf8) is typically used in [loop statements](http://zhidao.baidu.com/search?word=%E5%BE%AA%E7%8E%AF%E8%AF%AD%E5%8F%A5&fr=qb_search_exp&ie=utf8) and switch statements. When `break` is used within a [switch](http://zhidao.baidu.com/search?word=switch&fr=qb_search_exp&ie=utf8) statement, it allows the program to exit the [switch](http://zhidao.baidu.com/search?word=switch&fr=qb_search_exp&ie=utf8) block and execute the statements following the [switch](http://zhidao.baidu.com/search?word=switch&fr=qb_search_exp&ie=utf8) statement. Without a [break statement](http://zhidao.baidu.com/search?word=break%E8%AF%AD%E5%8F%A5&fr=qb_search_exp&ie=utf8), it would result in an [infinite loop](http://zhidao.baidu.com/search?word=%E6%AD%BB%E5%BE%AA%E7%8E%AF&fr=qb_search_exp&ie=utf8) that cannot --- ## SO_TIMESTAMP - A Socket Option Not Covered in 'Unix Network Programming' - URL: https://intl.sienovo.cn/blog/21943925 - Date: 2014-03-24 - Tags: none In the setsockopt function, commonly used socket options are employed to make necessary settings for a socket, allowing it to operate with the desired characteristics. SO_TIMESTAMP, a socket option, is not mentioned in the authoritative work 'Unix Network Programming,' and even on Google, it's hard to find a detailed explanation and usage for it. However, this socket option is used in the open-source code ptpv2d-rc1. So, what exactly is it used for? After analyzing the Linux 2.6.32 kernel source code, it was found that by setting this option, we can make the kernel protocol stack timestamp a network frame upon reception, and deliver this timestamp as ancillary data along with the network frame data to the upper layer protocol. netif_receive_skb(), a critical function in the Linux kernel protocol stack, is typically called as the last step in the network card driver's poll function (the RX interrupt handler schedules the poll function; for details, refer to the latest kernel mechani --- ## Directly Swapping Two Variable Values Without a Third Variable - URL: https://intl.sienovo.cn/blog/21518509 - Date: 2014-03-19 - Tags: #ProgrammingTechniques, #VariableSwapping, #BitwiseOperations, #EmbeddedDevelopment I recall seeing examples of directly swapping the values of two variables without introducing a third variable. The two methods I've encountered are as follows: Method One: var a=1; var b=2; a=a+b; b=a-b; a=a-b; Printing a and b will show that their values have been swapped.   Method Two: var a=1; var b=2; a=a^b; b=a^b; a=a^b; Printing a and b will show that their values have been swapped.     On the surface, these two methods might seem like mere tricks or clever maneuvers. However, they play a significant role in embedded development. In embedded systems, space is limited, and the fewer variables introduced, the more space is saved, thereby increasing the available development space. Thus, these techniques are quite commonly used.   A brief analysis of the two methods is as follows: Method One demonstrates a relatively clearer logical thought process, making it easier to understand. Method Two is comparatively faster because it directly utilizes bitwise operation --- ## Large Number Multiplication Algorithm - URL: https://intl.sienovo.cn/blog/21515839 - Date: 2014-03-19 - Tags: none A few days ago, my senior colleague had an online coding test. Fearing she wouldn't have enough time, she asked me for help. I solved a few problems, and I felt they were commonly used in interviews. Large number multiplication was one of them, and I believe it will be frequently encountered in future interviews, so I made a note of it. The method I adopted here is to store large numbers as strings, then multiply the two strings digit by digit, followed by carrying and shifting. There should be more efficient code available. Source Code: ```cpp #include #include #include #define N 100 /* *将在数组中保存的字符串转成数字存到int数组中*/void getdigits(int *a,char *s){ int i; char digit; int len = strlen(s); //对数组初始化 for(i = 0; i < N; ++i) *(a + i) = 0; for(i = 0; i < len; ++i){ digit = *(s + i); *(a + len - 1 - i) = digit - '0';//字符串s="12345",因此第一个字符应该存在int数组的最后一个位置 }} /* *将数组a与数组b逐位相乘以后存入数组c */void multiply(int *a,in --- ## QoS Traffic Shaping - URL: https://intl.sienovo.cn/blog/20533491 - Date: 2014-03-05 - Tags: none ## What Is QoS Traffic Shaping? Quality of Service (QoS) encompasses a broad set of techniques that network equipment uses to manage bandwidth, delay, jitter, and packet loss. Among these techniques, **Traffic Shaping (TS)** occupies a specific and important role: it actively adjusts the rate at which traffic leaves an interface so that the outgoing flow conforms to a defined profile. This article explains how traffic shaping works, how it differs from the closely related mechanism of traffic policing, and why the distinction matters for real-world network design. ## The Core Mechanism: Rate Control Through Buffering Traffic Shaping is a measure that actively adjusts the traffic output rate. A typical application is to control the output of local traffic based on the TP (Throughput) metric of downstream network nodes. In practice this means that when an upstream device — say, a core router or an edge gateway — knows that the next hop can only sustain a certain throughput, it uses s --- ## QoS Token Bucket Algorithm Analysis - URL: https://intl.sienovo.cn/blog/20529793 - Date: 2014-03-05 - Tags: none Traffic Policing in QoS controls traffic by monitoring the rate of traffic entering a network port and "punishing" excess traffic (this punishment can be dropping or delaying transmission), thereby limiting the traffic entering the port to a reasonable range. For example, it can restrict HTTP messages from occupying more than 50% of the network bandwidth; otherwise, the QoS traffic policing function can choose to drop the messages or reconfigure their priority. The QoS traffic policing function is implemented using a Token Bucket mechanism. Here, a "token bucket" refers to an internal storage pool within a network device, and "tokens" refer to virtual information packets that fill the token bucket at a given rate. These virtual information packets are used to determine the current rate of incoming messages. When a switch receives each frame, it adds a token to the token bucket. However, this token bucket has a hole at the bottom, constantly releasing tokens (i.e., removing tokens fr --- ## Interview: String Class Constructor and Destructor Implementation - URL: https://intl.sienovo.cn/blog/20405279 - Date: 2014-03-03 - Tags: none Given the String class definition: ```cpp class String { public: String( const char *str = NULL); // General constructor String(const String &another); // Copy constructor ~ String(); // Destructor String & operater =(const String&rhs); // Assignment operator private: char *m_data; // Used to store the string }; ``` Attempt to implement the member functions of the class. Answer: ```cpp // General constructor String::String(const char *str){ if ( str == NULL ) // This check is necessary because strlen throws an exception if the parameter is NULL. { m_data = new char[1] ; m_data[0] = '\0' ; } else { m_data = new char[strlen(str) + 1]; strcpy(m_data,str); } } // Copy constructor String::String(const String &another){ m_data = new char[strlen(another.m_data) +1]; strcpy(m_data,another.m_data); } // Assignment operator String& String::operator =(const String&rhs){ if ( this == &rhs) return *this ; delete --- ## Interview: Union Memory Representation - URL: https://intl.sienovo.cn/blog/20403425 - Date: 2014-03-03 - Tags: none In this example, the union `a` has two members: an integer `i` and a character array `x` of size 2. Since both members share the same memory space, the memory layout is as follows: * `a.x[0]` occupies the low byte of the memory space (address 0) * `a.x[1]` occupies the high byte of the memory space (address 1) When we assign values to `a.x[0]` and `a.x[1]`, the resulting memory layout is `0x010A`, where `0x0A` is the low byte (address 0) and `0x01` is the high byte (address 1). This is known as little-endian byte order. ### Struct vs Union Memory Layout To better understand the difference between struct and union memory layouts, let's compare the two: --- ## Interview: Clever Use of Binary - URL: https://intl.sienovo.cn/blog/20402883 - Date: 2014-03-03 - Tags: #Binary, #BitManipulation, #InterviewQuestion, #Programming ## Counting Set Bits with Binary Operations In this article, we will explore a clever use of binary operations to count the number of set bits in a given integer. This technique is often used in programming interviews and is a fundamental concept in computer science. The function in question is a simple C function that takes an integer `x` as input and returns the number of set bits (1s) in its binary representation. The function uses a while loop to repeatedly apply a binary operation to `x` until it becomes 0. ### The Function ```c int func( x ) { int countx = 0; while(x) { countx ++; x = x&(x-1); } return countx; } ``` ### Approach The approach used in this function is based on the observation that the binary representation of a number can be manipulated using bitwise operations. Specifically, the expression `x&(x-1)` is used to clear the least significant set bit in `x`. This is because when `x` is subtracted by 1, the least significant set --- ## [Sorting] Quick Sort C++ Implementation Summary - URL: https://intl.sienovo.cn/blog/20212637 - Date: 2014-03-01 - Tags: #QuickSort, #C++ ## I. Algorithm Steps The basic idea of Quick Sort is: 1. Select an element from the array as the pivot. 2. Partitioning process: Place all elements greater than the pivot to its right, and all elements less than or equal to the pivot to its left. 3. Recursively apply step 2 to the left and right sub-arrays until each sub-array contains only one element. Algorithm steps: 1) Initialize two variables i and j. At the start of sorting: i=0, j=N-1; 2) Use the first array element as the key data, assign it to **key**, i.e., **key**\=A\[0\]; 3) Search backward from j (j--), find the first value A\[j\] less than **key**, and assign A\[j\] to A\[i\]; 4) Search forward from i (i++), find the first value A\[i\] greater than **key**, and assign A\[i\] to A\[j\]; 5) Repeat steps 3 and 4 until i=j; ## II. Illustrated Execution Process Although Quick Sort is referred to as a divide-and-conquer algorithm, the term 'divide-and-conquer' alone doesn't fully encapsulate all its steps. Therefore, --- ## Distributed Big Data Processing on Linux - URL: https://intl.sienovo.cn/blog/20080509 - Date: 2014-02-27 - Tags: none ## Distributed Big Data Processing on Linux Distributed big data processing is a crucial aspect of modern data analysis and science. It involves processing massive amounts of data across a network of computers, often using specialized software frameworks. In this article, we will explore the basics of distributed big data processing on Linux and discuss some of the key considerations and tools involved. ### Big Data Processing on Linux Big data processing on Linux can be achieved through various methods, including the use of distributed computing frameworks such as Hadoop and Spark. These frameworks allow users to process large datasets across a cluster of nodes, leveraging the power of parallel processing to achieve faster results. However, big data processing is not just about processing large datasets. It also involves caching and storing the data in a way that allows for efficient access and retrieval. This is where distributed caching and storage systems come into play, such a --- ## 【c++对象模型】 - URL: https://intl.sienovo.cn/blog/19918433 - Date: 2014-02-25 - Tags: #C++ virtual ## Understanding the C++ Object Model In this post, we will delve into the C++ object model, focusing on the implications of using `virtual` functions and how they facilitate polymorphism. By the end of this article, you will gain insights into the overhead introduced by virtual functions, the structure of the virtual table (Vtbl), and the mechanisms that enable polymorphism in C++. ### 1. Overhead in C++ Due to Virtual Functions The primary source of overhead in C++ regarding layout and access time is due to the use of `virtual` functions. There are two key aspects to consider: 1. **Virtual Function**: This refers to runtime binding, where the function to be executed is determined at runtime rather than compile time. This allows for more dynamic behavior in object-oriented programming but introduces additional overhead due to the need for runtime lookups. 2. **Virtual Base Class**: This is a base class that is declared as virtual. It ensures that only one instance of the base cla --- ## [Interview] 3. How to Detect a Cycle in a Linked List? How to Calculate the Cycle's Length? - URL: https://intl.sienovo.cn/blog/19831737 - Date: 2014-02-24 - Tags: none 1. How to detect a cycle? If you have two pointers, one moving fast and one moving slow, after a certain number of steps, the fast pointer will eventually overtake the slow pointer by one full cycle. 2. How to calculate the length of the cycle? Start counting when they meet for the first time (after the fast pointer has completed one cycle), and stop counting when they meet for the second time. 3. How to find the entry point of the cycle: The distance from the collision point (p) to the cycle's entry point is equal to the distance from the head pointer to the cycle's entry point. Therefore, if you start one pointer from the collision point and another from the head pointer, and both move one step at a time, the point where they meet will be the cycle's entry point. Why? Here's a simple derivation: (1) When fast and slow pointers meet, the slow pointer has definitely not traversed the entire linked list, while the fast pointer has completed n (n >= 1) cycles within the loop. Assume --- ## 1588 Analysis and Implementation Overview - URL: https://intl.sienovo.cn/blog/19813081 - Date: 2014-02-24 - Tags: none ## 1588 Analysis and Implementation Overview The IEEE 1588 protocol, also known as Precision Time Protocol (PTP), is a widely used standard for synchronizing clocks in distributed systems. This article provides an overview of the 1588 protocol analysis and implementation, covering its key concepts, synchronization algorithms, and implementation details. ## Protocol Analysis The 1588 protocol has a certain level of difficulty due to its wide range of aspects and complex synchronization algorithms. To better understand the protocol, it's essential to analyze its key concepts and address difficult problems. ### Clock Types and Synchronization The 1588 protocol supports two synchronization types: End-to-End (E2E) and Peer-to-Peer (P2P). E2E synchronization involves a master clock and one or more slave clocks, while P2P synchronization involves two peer clocks. ### PTP Clock Entities A PTP clock entity is a device that implements the 1588 protocol and provides timing information. Clo --- ## Interview Topic Overview - URL: https://intl.sienovo.cn/blog/19809689 - Date: 2014-02-24 - Tags: none ## Interview Topic Overview When preparing for technical interviews, it's essential to have a solid understanding of various topics that are commonly covered. In this article, we'll provide an overview of the interview topics that are typically discussed during technical interviews. ### (I) Linux Topics Linux is a widely used operating system in the industry, and understanding its basics is crucial for any technical role. Linux topics may include: * Linux file systems and permissions * Process management and system calls * Shell scripting and command-line interfaces * Networking and communication protocols ### (II) C/C++ Topics C and C++ are fundamental programming languages used in many industries, and proficiency in these languages is often a requirement for technical positions. C/C++ topics may include: * Data types, operators, and control structures * Functions, pointers, and memory management * Object-Oriented Programming (OOP) concepts * Exception handling and error manage --- ## Interview Questions: Linux Topics - URL: https://intl.sienovo.cn/blog/19808805 - Date: 2014-02-24 - Tags: #Linux, #InterviewQuestions, #Programming, #Networking, #Debugging ## Interview Questions: Linux Topics As a Linux system administrator or developer, it's essential to be familiar with various Linux topics, including thread synchronization, daemon processes, server processes, and network programming. In this article, we'll cover some common Linux interview questions and provide tips on how to approach them. ### (I) APUE (Advanced Programming in the UNIX Environment) APUE is a comprehensive book on Unix programming that covers various topics, including thread synchronization, daemon processes, server processes, and memory management mechanisms. Here are some key concepts to focus on: - **Thread synchronization**: Understanding how to synchronize threads using mutexes, semaphores, and other synchronization primitives is crucial in multi-threaded programming. - **Daemon processes**: A daemon process is a long-running process that runs in the background and performs specific tasks. Understanding how to create and manage daemon processes is essential. --- ## Interview Questions: Data Structures Catalog - URL: https://intl.sienovo.cn/blog/19807101 - Date: 2014-02-24 - Tags: none ** (I) Linked List Operations ** **1. Reverse a linked list. Iterative algorithm.** **2. Reverse a linked list. Recursive algorithm.** **3. Determine if a linked list has a cycle.** **4. Delete elements from one linked list that are present in another.** **5. Two linked lists, one ascending and one descending. Merge them into a single ascending linked list.** **6. Delete a specified element from a doubly linked list.** ** (II) Binary Tree Topics ** **1. Breadth-first traversal of a binary tree.** **2. Determine if a binary tree is balanced.** **3. Return the depth of a binary tree.** ** (III) String Topics ** **1. Quickly implement a String class.** **2. Output all permutations of a string. Note: handle duplicate characters.** **3. Reverse a string.** **4. Implement the strstr function.** **5. Implement the strcmp function.** ** (IV) Recursion Topics ** **1. Towers of Hanoi problem.** **2. Minimum number of steps for the three-peg Towers of Hanoi.** --- ## Interview Question [2]: The Difference Between 'exit()' and '_exit()' - URL: https://intl.sienovo.cn/blog/19613189 - Date: 2014-02-21 - Tags: none In the realm of C and C++ programming, particularly when dealing with system-level operations and process management, understanding the nuances between seemingly similar functions is crucial. This article delves into the critical distinctions between `exit()` and `_exit()`, two functions used to terminate a program. While both ultimately stop a process, their underlying mechanisms and the cleanup operations they perform differ significantly, impacting resource management, data integrity, and multi-process programming, especially when combined with `fork()` and `vfork()`. By the end of this post, you'll have a clear understanding of when to use each function and the implications of your choice. ## Understanding Process Termination in Linux/Unix When a program finishes execution, either normally or due to an error, the operating system needs to reclaim the resources it was using. This includes memory, open files, network connections, and other system-level constructs. The `exit()` and --- ## Interview Question [1]: Is i++ an atomic operation? Explain why. - URL: https://intl.sienovo.cn/blog/19612795 - Date: 2014-02-21 - Tags: none No, it is not an atomic operation. Reasons: **1. i++ consists of three stages:** - Load from memory to register - Increment in register - Write back to memory These three stages can be interrupted and separated. **2. The behavior of ++i depends on how the compiler compiles it.** Some compilers, such as VC, in non-optimized builds, may generate the following assembly code: ```asm __asm { mov eax, dword ptr[i] inc eax mov dword ptr[i], eax } ``` In this case, it is definitely not an atomic operation, and mutual exclusion via locking is required. Suppose optimization is enabled—will it always be compiled into `inc dword ptr[i]`? The answer is no. It depends on the compiler. If the result of ++i is to be used afterward, it definitely won't be compiled into the `inc dword ptr[i]` form. Now, suppose it *is* compiled into `inc dword ptr[i]`. Since this instruction is atomic, does that mean locking is unnecessary? On a single-core machine, skipping locks may not --- ## Smart Pointers (auto_ptr and shared_ptr) - URL: https://intl.sienovo.cn/blog/9177185 - Date: 2013-06-26 - Tags: none ### [Smart Pointers (auto_ptr and shared_ptr)](http://www.cppblog.com/expter/archive/2009/03/29/78270.html) This is a summary of my reading and coding this week:        In STL, auto_ptr is just one of many possible smart pointers. What auto_ptr does is dynamically allocate objects and automatically perform cleanup when the objects are no longer needed.     Here's a simple code example without auto_ptr:           1 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/9177185/29_None.gif) void ProcessAdoption(istream &data)  2 ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/9177185/30_ExpandedBlockStart.gif) {  3![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/9177185/37_InBlock.gif)   4![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/9177185/37_InBlock.gif)    while (data)                            // If there is still data  5![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/9177185/33_ExpandedSubBlockStart.gif)     --- ## htonl(),htons(),ntohl(),ntons()-- Endianness Conversion Functions - URL: https://intl.sienovo.cn/blog/9092717 - Date: 2013-06-14 - Tags: none ## [htonl(),htons(),ntohl(),ntons()-- Endianness Conversion Functions](http://www.cnblogs.com/kungfupanda/archive/2013/04/24/3040785.html) Different machines store variable bytes in different orders internally; some use big-endian mode, while others use little-endian mode. Big-endian mode means that the most significant byte (MSB) is stored at the lowest memory address, and the least significant byte (LSB) is stored at the highest memory address. Little-endian mode means that the least significant byte (LSB) is stored at the lowest memory address, and the most significant byte (MSB) is stored at the highest memory address. When transmitting data over a network, because the two ends of data transmission may correspond to different hardware platforms and the byte order used for storage may also be inconsistent, the TCP/IP protocol therefore stipulates that network byte order (which is big-endian mode) must be used on the network. Analysis of the endianness storage principles reveals t --- ## Starting Wireshark Packet Capture as a Regular User in Linux - URL: https://intl.sienovo.cn/blog/9092455 - Date: 2013-06-14 - Tags: none ## Starting Wireshark Packet Capture as a Regular User in Linux Wireshark is a powerful network protocol analyzer that allows users to capture and interactively browse the traffic running on a computer network. While it is often run with root privileges to access raw network packets, there are ways to configure it to allow regular users to perform packet captures. This article will guide you through the steps necessary to set up Wireshark for use by non-root users in a Linux environment. ### Why Run Wireshark as a Regular User? Running Wireshark as a regular user instead of root can enhance security by minimizing the risk of accidental system changes or vulnerabilities that could be exploited. It also helps in maintaining a clean separation between user-level applications and system-level operations. ### Prerequisites Before proceeding, ensure you have the following: - A Linux distribution with Wireshark installed. You can install it using your package manager. For example, on De --- ## Basic Operations and Usage of C++ map - URL: https://intl.sienovo.cn/blog/9036595 - Date: 2013-06-06 - Tags: none ### Basic Operations and Usage of C++ map    Source: ([http://blog.sina.com.cn/s/blog_61533c9b0100fa7w.html](http://blog.sina.com.cn/s/blog_61533c9b0100fa7w.html)) - Basic Operations and Usage of C++ map_Live_Sina Blog     Map is a standard C++ container that provides an excellent one-to-one relationship. Creating a map in some programs can achieve twice the result with half the effort. Here's a summary of some basic, simple, and practical map operations! 1. Most basic map constructors;    map mapstring;          map mapint;    map mapstring;          map mapchar;    map mapchar;             map mapint; 2. Adding data to map;    map maplive;       1. maplive.insert(pair(102, "aclive"));    2. maplive.insert(map::value_type(321, "hai"));    3. maplive[112] = "April"; // The simplest and most commonly used insertion method for map! 3. Searching for elements in map:    --- ## C语言模块化编程(我见过最好的) - URL: https://intl.sienovo.cn/blog/8716824 - Date: 2013-03-25 - Tags: none ## C Language Modular Programming (The Best I've Ever Seen) C language modular programming is a crucial aspect of software development, allowing developers to break down complex programs into smaller, manageable modules. In this article, we will explore the concept of modular programming in C and discuss its benefits. ### What is Modular Programming? Modular programming is a programming paradigm that involves breaking down a program into smaller, independent modules. Each module has a specific function or set of functions and can be written, tested, and maintained independently. This approach has several benefits, including improved code reusability, easier debugging, and faster development times. ### Benefits of Modular Programming in C Modular programming in C offers several advantages, including: * **Improved Code Reusability**: Modular programming allows developers to reuse code across multiple projects, reducing the amount of code that needs to be written and maintained. * --- ## POSIX Thread-Specific Data - URL: https://intl.sienovo.cn/blog/8585758 - Date: 2013-02-17 - Tags: none Original sources: [http://baike.baidu.com/view/974776.htm](http://baike.baidu.com/view/974776.htm) [http://www.blogjava.net/tinysun/archive/2010/05/29/322210.html](http://www.blogjava.net/tinysun/archive/2010/05/29/322210.html) In single-threaded programs, functions often use global or static variables without affecting program correctness. However, if functions called by threads use global or static variables, it can easily lead to programming errors, because the global and static variables used by these functions cannot store their respective values for different threads. Problems can arise when different threads within the same process call such functions almost simultaneously. One way to solve this problem is to use thread-specific data (TSD). Thread-specific data employs a technique known as 'one key, multiple values,' meaning a single key corresponds to multiple values. When accessing data, it's always done via the key, appearing as if a single variable is being accessed, bu --- ## Classic Interview Question - URL: https://intl.sienovo.cn/blog/8462591 - Date: 2013-01-03 - Tags: none ## Classic Interview Question: Debugging Techniques for Edge-AI Applications Debugging edge-AI applications can be a daunting task, especially when working with complex systems and limited resources. In this article, we'll explore a classic interview question that can help you develop your debugging skills and become more proficient in troubleshooting edge-AI applications. ### Background Edge-AI applications often involve custom hardware and software solutions, making it challenging to identify and resolve issues. The AM5728, a TI Sitara processor with dual ARM Cortex-A15 cores, is a popular choice for edge-AI applications due to its low power consumption and high performance. However, debugging this processor can be tricky, especially when dealing with complex software stacks and limited resources. ### The Classic Interview Question The classic interview question is: "How would you debug a system crash on an edge-AI application running on an AM5728 processor?" This question requi --- ## Doubly Linked List Creation, Insertion, and Deletion - URL: https://intl.sienovo.cn/blog/8462460 - Date: 2013-01-03 - Tags: none ```cpp #includeusing std::cout;using std::endl; template class Node{ // Definition of a node public: Node(T t):item(t),previous(0),next(0){} T item; Node* previous; Node* next;}; template class TwoWayLinkedList{ // Definition of a doubly linked list public: TwoWayLinkedList():length(0),head(0),tail(0){}; ~TwoWayLinkedList(); int getLength(){return length;} void add(T t); T get(int i); void insert(int i,T t); void del(int i); void display();private: Node* head; Node* tail; int length;}; template void TwoWayLinkedList::add(T t){ // Add a new element to the end of the list if(head==0){ // If the list is empty head=new Node(t); tail=head; } else { Node* q=new Node(t); // Create a new node to store the new element tail->next=q; // Add to the end of the current list q->previous=tail; // Its previous node is the current tail tail=tail->next; // Move the tail to this new element } length++;} template mymap;` And a `std::set` is declared as: `set myset;` A `std::set` (collection) contains sorted data, and the values in a set must be unique. A `std::map` (mapping) is a collection of sorted pairs. Each element in a map consists of two values: a key (the key in a map must be unique), which is used for sorting or searching and whose associated value can be retrieved from the container. For example, in addition to finding data like `ar[43] = "overripe"`, a map allows finding data using `ar["banana"] = "overripe"`. If you want to retrieve element information, you can easily do so by providing the full name (key) of the element. A `std::map` is a mapping where keys within the collection mus --- ## Mediator Pattern - URL: https://intl.sienovo.cn/blog/8452356 - Date: 2012-12-30 - Tags: none Mediator Pattern The goal of object-oriented design is to achieve high cohesion and low coupling, ultimately leading to the development of software that is easy to maintain, extend, and reuse. Therefore, during software high-level design and architecture setup, we should consciously reduce the coupling between classes and minimize inter-class interactions. When we first start with object-oriented development, due to a lack of knowledge and experience, we often prioritize functionality over software structure. Code often becomes cluttered with situations where class A's header file includes a pointer to class B, and class B's header file includes a pointer to class A. Such operations lead to excessively strong coupling between classes A and B. We need to reduce the interactions between classes A and B, and the Mediator pattern can help us lower inter-class coupling. First, let's look at a highly coupled program: ```cpp //类A头文件 class B; class C; class A { public:    void    Set --- ## Adapter Pattern and Facade Pattern (Highly Recommended) - URL: https://intl.sienovo.cn/blog/8452320 - Date: 2012-12-30 - Tags: none Original Link: [适配器模式和外观模式](http://www.cnblogs.com/goody9807/archive/2011/09/06/2168729.html) **Adapter Pattern (Adapter)** Let's start with an introduction and a problem. As is well known, the common voltage in China is 220V, while in the United States it is 110V. If an IT professional frequently travels between the US and China, always carrying their laptop, how can the laptop's voltage issue be resolved? (Because the voltage differs between the US and China, general electrical appliances are not interchangeable.) This is where the adapter shines. Modern laptops all have a power adapter, and it is precisely this power adapter that solves the aforementioned adaptation problem. For example, a Sony laptop might have an input voltage range of AC 100V~240V, with a unified DC output of 19.5V. AC current is input into one end of the power adapter, which then converts the power to the required voltage. In essence, the adapter's role is to make one thing suitable for another. **Here is --- ## Differences Between Mutex and Semaphore - URL: https://intl.sienovo.cn/blog/8364466 - Date: 2012-12-21 - Tags: none ## Differences Between Mutex and Semaphore In multi-threaded programming, understanding synchronization mechanisms is crucial for ensuring that multiple threads can operate without conflict. Two commonly used synchronization primitives are Mutexes and Semaphores. This article will explore the key differences between these two concepts, their usage, and provide code examples to illustrate how they function. ### Mutex: The Key Analogy A Mutex (short for mutual exclusion) can be thought of as a key to a room. When a thread takes the key (i.e., locks the mutex), it gains exclusive access to the room (the critical section of code). Once the thread is done with its task, it returns the key (unlocks the mutex) to the queue, allowing the next waiting thread to enter. The primary purpose of a mutex is to serialize access to a critical section of code, ensuring that only one thread can execute that section at any given time. This prevents race conditions and ensures data integrity. ### Semap --- ## C Perspective (Part 1) - Any C Program Can Be Understood as a Pointer Pointing to a Character, Followed by Character Matching - URL: https://intl.sienovo.cn/blog/8171291 - Date: 2012-11-11 - Tags: none ## C Perspective - Understanding Character Matching in C Programs In this article, we will explore the concept of character matching within C programs, focusing on the simple matching algorithm and the more advanced Knuth-Morris-Pratt (KMP) algorithm. Understanding these algorithms is crucial for anyone involved in string processing or searching tasks in programming. ### 1. History of Character Matching Character matching has a rich history in computer science, particularly in the context of string searching. The need for efficient algorithms to find substrings within larger strings has led to the development of various algorithms, each with its own advantages and trade-offs. ### 2. Character Matching Algorithms #### I. Simple Matching Algorithm Let's start with a straightforward example to illustrate the simple matching algorithm. Suppose we want to search for the substring T = "abcabd" within the string S = "abcabcabdabba". We can assume a 0-based indexing system for our chara --- ## The Purpose of `static` (Scope, Storage Area, Lifetime) - URL: https://intl.sienovo.cn/blog/8138624 - Date: 2012-11-01 - Tags: none [The Purpose of `static` (Modifying Functions, Local Variables, Global Variables)](http://www.cnblogs.com/stoneJin/archive/2011/09/21/2183313.html) In C language, the literal meaning of `static` can easily lead us astray. In fact, it has three main purposes. (1) Let's first introduce its first and most important purpose: hiding. When we compile multiple files simultaneously, all global variables and functions without the `static` prefix have global visibility. To understand this, I'll illustrate with an example. We will compile two source files simultaneously: `a.c` and `main.c`. Below is the content of `a.c` char a = 'A'; // global variable void msg() { printf("Hello\\n"); } Below is the content of `main.c` int main(void) { extern char a; // extern variable must be declared before use printf("%c", a); (void)msg(); return 0; } The program's output is: A Hello You might ask: why can the global variable `a` and function `msg` defined in `a.c` be used in `main.c`? As mentioned --- ## const int *p,const * int p,int const *p - URL: https://intl.sienovo.cn/blog/8138580 - Date: 2012-11-01 - Tags: none Let's start with a Microsoft interview question. 5.What is the output of the follow code ? voidmain(int argc, char\* argv\[\]) { int i = 11; int const \*p = &i; p++; print(“%d”,\*p); } A. 11 B. 12 C.Garbage value D. Comipler error E. None of above Choose:C #### const int *p,const * int p,int const *p 1 Let's start with const int i When 'ic' is modified by 'const', we don't call it a variable, but rather a symbolic constant, representing the number 20. This is the purpose of 'const'. 'ic' cannot be reassigned a new value elsewhere. After understanding the role of 'const', we also need to know the format. There are two ways: `const int ic=20;` and `int const ic=20;`. They are completely identical. This point must be clear. In short, you must remember that whether 'const' or 'int' comes first does not affect the semantics. With this concept in mind, let's look at these two: `const int * pi` and `int const * pi`. According to your logic, do their semantics differ? Haha, --- ## 2012 Microsoft Written Exam Questions (Summer Internship Recruitment) - URL: https://intl.sienovo.cn/blog/8134127 - Date: 2012-10-31 - Tags: none #### [2012 Microsoft Written Exam Questions (Intern)](http://blog.csdn.net/dgglx/article/details/7441877) --- ## Detecting a Cycle in a Singly Linked List - URL: https://intl.sienovo.cn/blog/8123352 - Date: 2012-10-29 - Tags: none 1. How to determine if a linked list has a cycle? 2. If a linked list has a cycle, how do you find the entry point of the cycle? Solution: I. Detecting if a Linked List Has a Cycle, the method is as follows: Set two pointers (fast, slow), both initially pointing to the head. The `slow` pointer advances one step at a time, and the `fast` pointer advances two steps at a time. If the linked list contains a cycle, the `fast` pointer will inevitably enter the cycle first, followed by the `slow` pointer, and the two pointers will eventually meet. (Of course, if the `fast` pointer reaches NULL at the end of the list, then it's a cycle-free linked list). The code is as follows: ```c bool IsExitsLoop(slist *head) { slist *slow = head, *fast = head; while ( fast && fast->next ) { slow = slow->next; fast = fast->next->next; if ( slow == fast ) break; } return !(fast == NULL || fast->next == NULL); } ``` II. Finding the Entry Point of the Cycle Wh --- ## Demystifying Binary Trees (Part One) - URL: https://intl.sienovo.cn/blog/8119742 - Date: 2012-10-27 - Tags: none This article aims to provide an accessible explanation for common confusions encountered during personal study of binary trees. Donald Knuth has a book, 'The Art of Computer Programming,' which discusses how 0s and 1s construct the vast world. Binary trees are an introductory topic in the non-linear part of data structures, and one of the most fascinating and widely used structural forms in the computer world (e.g., file directories are tree structures). Starting from the simplest definitions and deriving the various properties of binary trees, as well as operations like traversal, insertion, deletion, and sorting, is highly valuable for logical training and learning about computers themselves. I. Binary Tree Storage Sequential Storage: Full binary trees; Linked Storage: Saves space; II. How to Understand Binary Tree Recursive Traversal? (Code) [Refer to the Recursion and Stack chapter] Once binary tree storage (primarily linked storage) is understood, the first challenge in bina --- ## Binary Search Implementation (C Code) - URL: https://intl.sienovo.cn/blog/8095539 - Date: 2012-10-21 - Tags: #c, #linux ## Binary Search Implementation (C Code) Binary search is a fast search algorithm that finds the position of a target value within a sorted array. It compares the target value to the middle element of the array and eliminates half of the array from consideration at each step. This process continues until the target value is found or the search space is empty. In this article, we will explore a C code implementation of binary search. ### Introduction Binary search is particularly useful when dealing with large datasets, as it has a time complexity of O(log n), making it much faster than linear search (O(n)) for large datasets. However, it requires the data to be sorted, which can be a significant overhead in some cases. ### Implementation Here is a simple C code implementation of binary search: ```c #include int binary_search(int arr[], int n, int target) { int left = 0; int right = n - 1; while (left <= right) { int mid = left + (right - left) / 2; --- ## Analysis of Function Stack Change Process - URL: https://intl.sienovo.cn/blog/8090167 - Date: 2012-10-19 - Tags: #gcc, #c http://blog.21ic.com/user1/5585/archives/2009/56681.html**[Stack and Function Calls](http://blog.21ic.com/user1/5585/archives/2009/56681.html) [http://blog.csdn.net/cos_sin_tan/article/details/6769493](http://blog.csdn.net/cos_sin_tan/article/details/6769493)[C Function Calls and Stack Changes](http://blog.csdn.net/cos_sin_tan/article/details/6769493) http://www.linuxso.com/linuxbiancheng/14561.html**In-depth Analysis of GCC Function Call Stack Change Process --- ## The Relationship Between TCP/IP and Sockets (An Absolute Classic) - URL: https://intl.sienovo.cn/blog/7394866 - Date: 2012-03-26 - Tags: #socket, #360 ## The Relationship Between TCP/IP and Sockets TCP/IP and sockets are fundamental concepts in computer networking. In this article, we will explore the relationship between these two concepts and what you can learn from understanding them. TCP/IP is a suite of communication protocols used to interconnect devices on the internet. It provides a set of rules and standards for data transmission between devices. Sockets, on the other hand, are endpoints for communication between two devices in a network. A socket is a unique identifier that allows devices to communicate with each other. ### What is a Socket? A socket is a software construct that represents a connection between two devices in a network. It is a combination of an IP address and a port number that identifies a specific endpoint for communication. Sockets are used to establish connections between devices and to send and receive data. ### Relationship Between TCP/IP and Sockets TCP/IP and sockets are closely related. TCP/I --- ## Detailed Explanation of PV Primitive Operations - URL: https://intl.sienovo.cn/blog/7361976 - Date: 2012-03-16 - Tags: #Semaphore, #Work, #Communication, #Activity, #Tool, #Testing ## Detailed Explanation of PV Primitive Operations PV primitives are a fundamental concept in operating systems, used to handle inter-process synchronization and mutual exclusion issues. In this article, we will delve into the details of PV primitives, exploring their core concepts, implementation, and practical applications. ### What are PV Primitives? PV primitives are a pair of operations, P (short for "Proberen," the Dutch word for "to test") and V (short for "Verhogen," the Dutch word for "to increase"). These primitives are used to operate on semaphores, which are a type of variable used to control access to shared resources. ### Semaphores Semaphores were first proposed by the renowned Dutch computer scientist Edsger W. Dijkstra in 1965. The basic idea behind semaphores is to use a new variable type to record the number of currently available resources. There are two ways to implement semaphores: 1. The value of a semaphore must be greater than or equal to 0. A value of 0 --- ## Selecting the 3 Fastest Cows out of 38, Using a Track that Can Only Accommodate 6 Cows at a Time, Requiring the Fastest Method. (Organized) - URL: https://intl.sienovo.cn/blog/7359146 - Date: 2012-03-15 - Tags: #MathematicalComputation =================================Correct Solution================================================ Putting 6 cows on the track is equivalent to one sorting operation. To find the 3 fastest cows out of 38, you are essentially looking for the top 3 elements in a sorted list. The track already suggests using merge sort for implementation; you can directly refer to merge sort. Since the track can only accommodate a maximum of 6 elements (cows), and the last 3 elements in each merge 'box' are definitely eliminated, this is a special type of merge. Each merge only takes the top 3 elements from each 'box' and performs pairwise merge sort. Done. Reference for pairwise merge sort: [http://www.hiahia.org/datastructure/paixu/paixu8.5.1.1-1.htm](http://www.hiahia.org/datastructure/paixu/paixu8.5.1.1-1.htm) In essence, the efficiency should be slightly better than O(n log n). ================================The following method is incorrect and cannot guarantee the 3 largest numbers======== --- ## Swapping Left and Right Children in a Binary Tree (Recursive and Iterative Methods) - URL: https://intl.sienovo.cn/blog/7359121 - Date: 2012-03-15 - Tags: #null, #Algorithm #### Explanation: 1. **Base Case**: If the current node (`pTree`) is `NULL`, the function returns immediately. 2. **Swapping**: A temporary pointer `pTemp` is used to hold the left child while we swap the left and right children. 3. **Recursive Calls**: The function calls itself for the left and right children to ensure that all nodes in the tree are processed. ### Iterative Method Using a Queue The iterative approach uses a queue to perform a level-order traversal of the tree. This method avoids the use of recursion and is often preferred in environments where stack overflow could be a concern due to deep recursion. Here is the C++ implementation of the iterative method: --- ## Four Processes A, B, C, D: A Writes to Buffer, B, C, D Read from Buffer, Implemented with P/V Operations - URL: https://intl.sienovo.cn/blog/7359104 - Date: 2012-03-15 - Tags: #c, #semaphore ## Implementing a Producer-Consumer Model with P and V Operations In this article, we will explore a producer-consumer model implemented using P and V operations. The model consists of four processes: A, B, C, and D. Process A acts as the producer, writing data to a buffer, while processes B, C, and D act as consumers, reading data from the buffer. The key requirement of this model is that process A can only write again after it has finished writing and processes B, C, and D have all read once. This is achieved using a combination of semaphores and a mutex. ## Semaphores and Mutex To implement this model, we use five semaphores: `empty`, `full`, `mutex`, `b`, `c`, and `d`. The `empty` semaphore is initialized to `n`, where `n` is the number of slots in the buffer. The `full` semaphore is initialized to 0. The `mutex` semaphore is initialized to 1, which allows only one process to access the buffer at a time. The `b`, `c`, and `d` semaphores are initialized to 1, which indicates th --- ## Reverse Linked List - URL: https://intl.sienovo.cn/blog/7359099 - Date: 2012-03-15 - Tags: #null, #list, #Test, #QQ Define the linked list node as: **\[cpp\]**  [view plain](http://blog.csdn.net/niuer09/article/details/5961004# "view plain") [copy](http://blog.csdn.net/niuer09/article/details/5961004# "copy") 1. typedef struct tagListNode{   2.     int data;   3.     struct tagListNode\* next;   4. }ListNode, \*List;   The requirement is to reverse a singly linked list with a head node `List head`. Analysis:   1). If the linked list is empty or contains only one element, return directly;   2). Set up two adjacent pointers, `p` and `q`. The node pointed to by `p` will become the successor of the node pointed to by `q`;   3). Repeat step 2) until `q` is null.   4). Adjust the head and tail of the linked list. Example: Taking A->B->C->D as an example for reversal, the diagram is as follows: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/7359099/01_0_1287825676duab.gif) The implementation and test code are as follows: **\[cpp:nogutter\]**  [view plain](http://blog.csdn.net --- ## The TASK_RUNNING Process Linked List in Linux - URL: https://intl.sienovo.cn/blog/7353107 - Date: 2012-03-14 - Tags: #linux, #struct, #list Earlier versions of Linux organized all processes in the TASK\_RUNNING state into a linked list called the runqueue. Maintaining processes sorted by priority within the list incurred significant overhead, consequently, early schedulers had to scan the entire queue to select the 'best' runnable process. The runqueue implementation in Linux 2.6 is different. **To select the 'best' runnable process within a fixed time, the kernel divides the priorities of runnable processes into 0-139 and, for this purpose, establishes 140 linked lists for runnable processes to organize processes in the TASK\_RUNNING state, with each process priority corresponding to a different list.** Furthermore, in a multiprocessor system, each CPU has its own runqueue. The structure of the runqueue implemented in Linux 2.6 is as follows: | Type | Field | Description | | :------------------ | :--------- --- ## Analysis of Linux Atomic Operations - URL: https://intl.sienovo.cn/blog/7351451 - Date: 2012-03-14 - Tags: #Linux, #Assembly, #Compiler, #Struct, #Integer ## Analysis of Linux Atomic Operations Author: Lu Ran (Please cite the source for reproduction) This article provides a detailed example-based analysis of the `atomic_dec_and_test` atomic operation function provided by Linux, explaining the essential meaning of its atomicity. It also clarifies common misunderstandings about `volatile`. ### 1. Analysis of `atomic_dec_and_test` (1) First, let's look at the definition of `atomic_dec_and_test`: ```c 11 #ifdef CONFIG_SMP 12 #define LOCK "lock ; " 13 #else 14 #define LOCK "" 15 #endif 137 static __inline__ int atomic_dec_and_test(atomic_t _ v) 138 { 139 unsigned char c; 140 141 __asm__ __volatile__( 142 LOCK "decl %0; sete %1" 143 :"=m" (v->counter), "=qm" (c) 144 :"m" (v->counter) : "memory"); 145 return c ! = 0; 146 } ``` 11–15 this macro is used in the inline assembly part of some of the functions that follow. It means that the LOCK macro can always be used. But sometimes (the SMP case) it invokes the machine instruction to lock the --- ## What is "asmlinkage"? - URL: https://intl.sienovo.cn/blog/7324654 - Date: 2012-03-06 - Tags: #system, #assembly, #function, #optimization, #gcc, #compiler **What is "asmlinkage"?** I believe everyone who has looked at the Linux source code has noticed the `asmlinkage` macro. What is it used for? The asmlinkage tag is one other thing that we should observe about this simple function. This is a #define for some gcc magic that tells the compiler that the function should not expect to find any of its arguments in registers (a common optimization), but only on the CPU's stack. Recall our earlier assertion that system_call consumes its first argument, the system call number, and allows up to four more arguments that are passed along to the real system call. system_call achieves this feat simply by leaving its other arguments (which were passed to it in registers) on the stack. All system calls are marked with the asmlinkage tag, so they all look to the stack for arguments. Of course, in sys_ni_syscall's case, this doesn't make any difference, because sys_ni_syscall doesn't take any arguments, but it's an issue for most other system calls. --- ## IPC Message Queue System Call Source Code Entry Point: e.g., sys_msgsnd - URL: https://intl.sienovo.cn/blog/7309726 - Date: 2012-03-01 - Tags: #struct, #user, #null, #up Path: linux/ipc/syscall.c ```cpp /* 2 * sys_ipc() is the old de-multiplexer for the SysV IPC calls. 3 * 4 * This is really horribly ugly, and new architectures should just wire up 5 * the individual syscalls instead. 6 */ 7#include 8 9#ifdef __ARCH_WANT_SYS_IPC 10#include 11#include 12#include 13#include 14#include 15 16SYSCALL_DEFINE6(ipc, unsigned int, call, int, first, unsigned long, second, 17 unsigned long, third, void __user *, ptr, long, fifth) 18{ 19 int version, ret; 20 21 version = call >> 16; /* hack for backward compatibility */ 22 call &= 0xffff; 23 24 switch (call) { 25 case SEMOP: 26 return sys_semtimedop(first, (struct sembuf __user *)ptr, 27 second, NULL); 28 case SEMTIMEDOP: 29 return sys_semtimedop(first, (struct --- ## Meaning of SYSCALL_DEFINE - URL: https://intl.sienovo.cn/blog/7309692 - Date: 2012-03-01 - Tags: #Assembly, #User, #Table, #2010, #C CVE-2010-3301 is one such example. The root cause of this vulnerability is that when a 32-bit system call is executed on a 64-bit kernel, the higher 32 bits of %rax, which passes the system call number, are not cleared. Furthermore, %eax is used directly for comparison, causing the higher 32 bits to be ignored: ``` cmpl $(IA32_NR_syscalls-1),%eax ja ia32_badsys ia32_do_call: IA32_ARG_FIXUP call *ia32_sys_call_table(,%rax,8) ``` This way, a carefully crafted %rax can jump to the desired location! In [this exploit](http://blog.chinaunix.net/link.php?url=http://sota.gen.nz%2Fcompat2%2Frobert_you_suck.c), ptrace() is used to trace system calls, passing a calculated offset of the desired jump address into %rax, and then executing pre-placed code to escalate privileges! The fix is simple: either clear the higher bits of %rax, or use %rax for comparison. The commits that fixed this issue are: http://git.kernel.org/linus/36d001c70d8a0144ac1d038f6876c484849a74de http://git.kernel.org/linu --- ## Refactoring 1: Untangling and Decomposing a Messy Inheritance Hierarchy - URL: https://intl.sienovo.cn/blog/7308501 - Date: 2012-03-01 - Tags: #Life ## Refactoring 1: Untangling and Decomposing a Messy Inheritance Hierarchy In software development, particularly in object-oriented programming, managing inheritance hierarchies effectively is crucial for maintaining clean, efficient, and reusable code. This article delves into the challenges posed by messy inheritance hierarchies, the implications of duplicate code, and strategies for refactoring to create a more streamlined structure. By the end of this post, you will understand how to identify problematic inheritance patterns and simplify your codebase. ### The Problem with Messy Inheritance Hierarchies A messy inheritance hierarchy can lead to significant issues in software development. One of the most pressing concerns is the proliferation of duplicate code, which can complicate maintenance and increase the risk of bugs. When multiple classes share similar functionality but are implemented separately, it becomes challenging to ensure consistency across the codebase. This redund --- ## Meaning of `__read_mostly` Variables (LINUX) - URL: https://intl.sienovo.cn/blog/7307326 - Date: 2012-02-29 - Tags: #Linux, #LinuxKernel, #Cache, #Platform This macro utilizes the `__attribute__((__section__("section_name")))` GCC extension. This attribute instructs the compiler to place the variable into a user-defined section named `.data.read_mostly` instead of the default `.data` (for initialized data) or `.bss` (for uninitialized data) sections. ### The Purpose of `__read_mostly` The primary goal of defining data as `__read_mostly` is stated clearly: "From this, it can be seen that we can define frequently accessed data as `__read_mostly` type. When the Linux kernel is loaded, this data will automatically be stored in the Cache, thereby improving the overall system's execution efficiency." To understand this, consider the memory hierarchy in modern computing systems. CPUs operate at very high speeds, but accessing data from main system memory (DRAM) is significantly slower. To bridge this speed gap, CPUs employ multiple levels of cache (L1, L2, L3) that store frequently accessed data closer to the processor. A cache hit (finding d --- ## EXPORT_SYMBOL Meaning and Usage - URL: https://intl.sienovo.cn/blog/7307320 - Date: 2012-02-29 - Tags: #Module, #Shell Define a function `func1` in module `mod1`; define a function `func2` in another module `mod2`, where `func2` calls `func1`. In module `mod1`, use `EXPORT_SYMBOL(func1);` In module `mod2`, declare `extern int func1();` Then `func1` can be called from `mod2`. References: http://topic.csdn.net/u/20070910/09/ee2cff13-9179-41e3-9292-4fd73261f709.html http://www.dev-archive.com/msdn-archive/524/kernel-driver-5244619.shtm mod1.c ```c #include #include #include static int func1(void) {         printk("In Func: %s.../n",__func__);         return 0; } EXPORT_SYMBOL(func1); static int __init hello_init(void) {         printk("Module 1,Init!/n");         return 0; } static void __exit hello_exit(void) {         printk("Module 1,Exit!/n"); } module_init(hello_init); module_exit(hello_exit); ``` ############################################################# mod2.c ```c #include #include #include sta --- ## Defending Coupling, Vindicating Inheritance - URL: https://intl.sienovo.cn/blog/7301924 - Date: 2012-02-28 - Tags: #DataStructures, #Interface, #Language, #Windows, #Unix, #DOS Defending Coupling, Vindicating Inheritance Everyone has heard of a term called "object-based," used to describe languages that don't qualify for the "object-oriented" title but aspire to it. As far as I know, the disqualifying factor is usually the lack of inheritance support. One could say that support for inheritance is the watershed between "object-oriented" and "object-based." Inheritance, being so crucial, has been heavily utilized since its inception alongside "object-oriented" programming. However, an undercurrent has always been flowing, and recently it has even surfaced. These voices openly accuse inheritance of being closely related to coupling, and by slandering coupling as the root of all evil, they aim to defame inheritance, openly advocating for less use of inheritance, or even no inheritance at all. Is the situation truly as they describe? Is module independence really so precious, and low coupling so desirable, that it's worth abandoning inheritance and resorting t --- ## The Difference Between Aggregation and Composition - URL: https://intl.sienovo.cn/blog/7301881 - Date: 2012-02-28 - Tags: #class, #Language, #c The difference between aggregation and composition is that: aggregation is a "has-a" relationship, while composition is a "contains-a" relationship; the relationship between the whole and its parts is weaker in aggregation and stronger in composition; in an aggregation relationship, the lifecycle of the object representing the part is independent of the object representing the aggregate. Deleting the aggregate object does not necessarily delete the objects representing its parts. In composition, however, deleting the composite object simultaneously deletes the objects representing its parts. Let's use simple examples to illustrate the difference between aggregation and composition. Consider the phrase 'country destroyed, home ruined' (国破家亡). If the country is destroyed, the home naturally ceases to exist. 'Country' and 'home' clearly represent a composition relationship. Conversely, the relationship between a computer and its peripherals is an aggregation. Their relationship is relat --- ## Drafting: The Minimalist Approach - URL: https://intl.sienovo.cn/blog/7301278 - Date: 2012-02-28 - Tags: #SoftwareDev ## Drafting: The Minimalist Approach When it comes to software development, drafting is often seen as a crucial step in the creative process. It's the starting point for many ideas, a thought experiment that allows us to test and refine our concepts. In this article, we'll explore the concept of drafting in software development and compare it to the structure of a novel. ### Drafting as a Thought Experiment Drafting is similar to a conjecture, a hypothesis that we can test and refine through experimentation. It's an early stage in the process of forming a solid idea, and it's essential to approach it with a minimalist mindset. This means keeping our ideas simple, avoiding unnecessary complexity, and focusing on the core concept. ### Software Development vs. "Novel Structure" In software development, we often follow a structured approach, breaking down our project into manageable tasks and milestones. This is similar to the structure of a novel, where the author outlines the story, --- ## Benefits of Software Engineers' Agility - URL: https://intl.sienovo.cn/blog/7299021 - Date: 2012-02-27 - Tags: #idea, #敏捷, #算法, #优化, #工作 ## Benefits of Software Engineers' Agility — Fostering Rapid Idea Generation As software engineers, we often find ourselves in situations where we need to quickly come up with innovative solutions to complex problems. Agility is a crucial aspect of software engineering that enables us to think on our feet, make rapid decisions, and adapt to changing circumstances. In this article, we'll explore the benefits of software engineers' agility and how it can help us become more effective problem-solvers. ### 1. Rapid Idea Generation through Abundant Documentation With the abundance of documentation available today, software engineers can quickly pinpoint issues through skimming and scanning, laying the groundwork for rapid problem-solving. This approach avoids the slowness, high pressure, and low efficiency of reading everything thoroughly, freeing up and gaining time. By leveraging documentation, we can naturally allow ourselves to do many other things we want, such as learning and profe --- ## You are a Very Good Person - URL: https://intl.sienovo.cn/blog/7298897 - Date: 2012-02-27 - Tags: #Work ## The Value of Being a Good Person in the Workplace As a technical professional, it's easy to get caught up in the idea that success is solely dependent on one's technical skills. However, the truth is that being a good person can have a significant impact on one's career and overall well-being. In a recent conversation, someone asked if they were truly making a difference at their company, given their compensation package. The response was simple: "Because you are a very good person." This may seem like a superficial answer, but it highlights a crucial aspect of being a valuable team member. Being a good person in the workplace means being able to work effectively with others, communicate clearly, and contribute to a positive team dynamic. These skills are just as important as technical expertise, and can often make up for some technical shortcomings. In fact, being good at expression and writing are important conditions for career success, and a valuable life skill that will serv --- ## How Software Engineers Get Through a Difficult Afternoon (3:00 PM - 4:00 PM) - URL: https://intl.sienovo.cn/blog/7291351 - Date: 2012-02-24 - Tags: #Music, #Activity ## How Software Engineers Get Through a Difficult Afternoon (3:00 PM - 4:00 PM) As software engineers, we often find ourselves stuck in a rut, struggling to make progress on a particular problem. The afternoon slump, typically between 3:00 PM and 4:00 PM, can be particularly challenging. However, with a few simple strategies, you can break through the barrier and stay productive. In this article, we'll explore two essential techniques to help you navigate a difficult afternoon: alternate activities and nourishment. ### Alternate Activities When faced with a complex problem, it's easy to get stuck in a loop of continuous thinking. However, research has shown that our brains can only sustain focus for a limited period, typically around 4 hours. Prolonged concentration on a single problem can lead to mental fatigue, decreased productivity, and a higher likelihood of errors. To avoid this trap, alternate activities can be a game-changer. If you code in the morning, consider switching t --- ## Reflections on Use Case Granularity and Function Granularity - URL: https://intl.sienovo.cn/blog/7284506 - Date: 2012-02-22 - Tags: #actor, #FinanceSystem, #include, #Testing, #Work, #Telephony The issue of use case granularity has always been a common problem for requirements analysts. For this problem, I apologize, there is no silver bullet. I can only offer some basic principles to address it: Webmaster's Note: In my practical experience, I'm not pessimistic about this issue, because the definition of "one actor" and "one value" in a use case essentially determines its granularity. In this regard, I largely agree with Mr. Pan Jiayu of UMLchina's view that "use cases have no granularity." 1. **Control the total number of use cases**: Generally, the number of use cases for a fairly complex system might be between 30-50. If the number of use cases for a system significantly exceeds this range, it's worth checking if you've fallen into the trap of functional decomposition.          Webmaster's Note: To say that the number of use cases for a system is constant is certainly a misunderstanding! If one were to say that "the number of modules for a fairly complex system might b --- ## VXWORKS Kernel Analysis - URL: https://intl.sienovo.cn/blog/7272065 - Date: 2012-02-19 - Tags: #Task, #DataStructure, #Algorithm, #PerformanceOptimization, #Extension, #Unix **VXWORKS Kernel Analysis** 1. Structure of Real-time Operating Systems The most primitive structural form of operating systems developed in the early days of computing was a monolithic entity. In such systems, modules providing different functionalities, such as processor management, memory management, and input/output, were typically independent. However, they did not consider other modules in use during their execution, and each module ran with the same time granularity. As modern real-time environments require many different functionalities, and due to the asynchrony and non-determinism caused by concurrent activities in such environments, operating systems have become more complex. Therefore, the monolithic structure of early operating systems has been superseded by more precise internal structures. The Starting Point of Hierarchical Structure - The Kernel The best internal structural model for an operating system is a hierarchical one, with the kernel at th --- ## VxWorks Inter-task Communication Mechanisms - URL: https://intl.sienovo.cn/blog/7272055 - Date: 2012-02-19 - Tags: #Task, #Semaphore, #EmbeddedOS, #Server, #Embedded, #Socket ### VxWorks Inter-task Communication Mechanisms Author: Chen Junke **I. Introduction to VxWorks Operating System** 　　The VxWorks real-time operating system is a high-performance, scalable embedded real-time operating system launched by Wind River Systems of the United States, designed to run on target machines. At its core, VxWorks features the high-performance microkernel Wind, which boasts rapid task switching, interrupt support, and pre-emptive and time-slice round-robin scheduling mechanisms, ensuring quick responses to external events. Beyond the microkernel, VxWorks also includes modules such as an I/O system, file system, TCP/IP network system, graphics system, virtual memory management, and Board Support Packages (BSPs). The existence of the BSP layer allows VxWorks to be easily ported to various hardware platforms. In the current embedded operating system market, VxWorks holds over 80% market share and is widely applied in fields such as communications, consumer electronics --- ## VxWorks Message Queue Analysis and Application - URL: https://intl.sienovo.cn/blog/7272047 - Date: 2012-02-19 - Tags: #DataStructure, #Task, #API, #Work, #Struct, #Programming Abstract: This article provides a detailed introduction to the working principle of message queues in the VxWorks kernel, performs a flow analysis of the message queue's source code, and demonstrates the usage of message queue APIs with examples. Keywords: VxWorks, Message Queue, IPC Message queues are one of VxWorks' three inter-process communication (IPC) mechanisms. The other two are semaphores and shared memory. These IPC mechanisms use a common authorization method. A process can only access these resources after passing an identifier to the kernel via a system call. The control method used by these system IPC objects is very similar to that of file systems, using resource reference identifiers as indexes into a resource table. A message queue is essentially a linked list of messages. Messages are treated as records, and these records have a specific format and priority. Processes with write permission to the message queue can add new messages according to certain rules, and --- ## VxWorks Inter-Process Communication 0 -- Task Management - URL: https://intl.sienovo.cn/blog/7272015 - Date: 2012-02-19 - Tags: #Task, #TaskScheduling, #Delay, #DataStructure, #DevTools, #Algorithm ## VxWorks Inter-Process Communication 0 -- Task Management A task is an image of code execution. From a system perspective, a task is the smallest execution unit competing for system resources. Tasks can use or wait for system resources such as CPU, I/O devices, and memory space, and run concurrently with other tasks, independently of them (at a macroscopic level). The VxWorks kernel enables tasks to quickly share most system resources while having independent contexts to control the execution of individual threads. **1. Task Structure** Multitasking design allows for interrupting currently executing tasks at any time to respond to internal and external events within a deterministic timeframe. The VxWorks real-time kernel, Wind, provides a basic multitasking environment. Superficially, multiple tasks appear to execute simultaneously; in reality, the system kernel schedules them to run alternately according to a specific scheduling policy. The system scheduler uses a Task Control B --- ## VxWorks Inter-Process Communication 2 -- Semaphores - URL: https://intl.sienovo.cn/blog/7272008 - Date: 2012-02-19 - Tags: #semaphore, #Task, #Optimization, #delete, #Work ## VxWorks Inter-Process Communication 2 -- Semaphores ## I. Concept of Semaphores Semaphores are the primary mechanism for achieving task mutual exclusion and synchronization. The semaphores provided by VxWorks are highly optimized and are the fastest among all inter-task communication mechanisms. **II. Classification of Semaphores** **Binary Semaphores**: The optimal way to achieve mutual exclusion and synchronization; fastest and most commonly used. **Mutual Exclusion Semaphores**: A special type of binary semaphore, specifically optimized for mutual exclusion operations. **Counting Semaphores**: Similar to binary semaphores, they can record the number of times a semaphore has been released and can monitor multiple instances of the same resource. III. **Binary Semaphores** Tasks often wait for events or need to acquire resources. Polling is generally not allowed in Real-Time systems; it's best to use Pending to wait for events or resources. **State Diagram:** **![](https: --- ## VxWorks Inter-Process Communication 1 - Message Queues - URL: https://intl.sienovo.cn/blog/7272003 - Date: 2012-02-19 - Tags: #buffer, #Task ## VxWorks Inter-Process Communication 1 - Message Queues ## I. Concepts: 1. Message queues are used for passing information between tasks. 2. Multiple tasks can send or receive messages to/from the same message queue. 3. ISRs (Interrupt Service Routines) can send messages using the NO_WAIT option. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/7272003/01_0_1303094586oOvP.gif) ## II. Control Functions: ## **1. msgQCreate** **\[c-sharp\]** [view plain](http://write.blog.csdn.net/postedit# "view plain") [copy](http://write.blog.csdn.net/postedit# "copy") 1. MSG\_Q\_ID msgQCreate   2. (   3.     int maxMsgs, /\* Message queue length (maximum number of messages) \*/   5.     int maxMsgLength, /\* Maximum length of messages in the message queue\*/   7.     int options /\* FIFO/PRIORITY task queuing method\*/   8. )   **![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/7272003/02_0_13030945987Ino.gif)** **2. msgQSend** **\[c-sharp\]** [view plain --- ## VxWorks Message Queue Example - URL: https://intl.sienovo.cn/blog/7271926 - Date: 2012-02-19 - Tags: #Task, #Storage, #Null ### VxWorks Message Queue Example ### Inter-task communication methods in VxWorks include shared memory, semaphores, message queues, and pipes. Regarding semaphores, I published an article on the China Microcontroller World Forum. The link is: http://www.mcuw.com/bbs/dispbbs.asp?boardID=26&ID=5267&page=1 ▲ Comparison of Message Queues with Other Methods: 1. Semaphores are easy to use and can solve many inter-task coordination problems, but the information they convey is limited. Shared memory, while capable of conveying more information, is not standardized. Message queues serve as a compromise for information exchange between threads. 2. Message queues allow many messages to be queued, and each message can have a different length. In contrast, data in traditional pipes is merely a stream of bytes with no boundaries. Data in VxWorks pipes is composed of messages. ▲ Message Queue Usage Characteristics: Message queues are highly efficient when transferring sm --- ## VxWorks Inter-Task Message Queue Communication Example - URL: https://intl.sienovo.cn/blog/7271915 - Date: 2012-02-19 - Tags: #Task, #Structure, #Include, #Header, #Struct, #Function ```cpp /* VxWorks Inter-Task Message Queue Communication Example */ /* msgQDemo.h - Header for the msgQDemo *//* Copyright 1984-1997 Wind River Systems, Inc. */ /*modification history--------------------01b,06nov97,mm added copyright.01a,14dec93,ms written.*/#define CONSUMER_TASK_PRI 99 /* Priority of the consumer task */#define PRODUCER_TASK_PRI 98 /* Priority of the producer task */#define TASK_STACK_SIZE 5000 /* stack size for spawned tasks */struct msg { /* data structure for msg passing */int tid; /* task id */ int value; /* msg value */};LOCAL MSG_Q_ID msgQId; /* message queue id */LOCAL int numMsg = 8; /* number of messages */LOCAL BOOL notDone; /* Flag to indicate the completion of this demo */============================================================================ /* msgQDemo.c - Demonstrates intertask communication using Message Queues *//* Copyright 1984-1997 Wind River Systems, Inc. *//*modification history--------------------01c,06nov97,mm added copyright. --- ## The Art of Rest - URL: https://intl.sienovo.cn/blog/7268060 - Date: 2012-02-17 - Tags: #Work, #Life, #Activities, #Sports, #Biology, #Tasks After ancient people had fully enjoyed the abundant wild fruits they gathered or the meat they hunted, their remaining tasks were sleep and play – this was the rest of primitive humans. In modern life, rest is no longer merely physical recovery after labor. Modern people believe that the ability to reasonably arrange work and achieve more with less effort during work also falls within the scope of the art of rest. I remember a story my parents told me when I was a child: There were two woodcutters in the mountains chopping wood. Woodcutter A saw Woodcutter B diligently chopping away at a small tree, but the tree still wouldn't fall. A walked over and advised him, "I think your axe is a bit dull. You'd better stop and rest for a bit, and sharpen it while you're at it." B looked up, wiping sweat from his face, and said angrily, "It's almost dark, and I've only chopped half a load of wood. How can I possibly have time to rest and sharpen my axe?" After reading this story, many would t --- ## (Reprint) How Men Can Rest Better - URL: https://intl.sienovo.cn/blog/7268041 - Date: 2012-02-17 - Tags: #Life, #Work, #Activities, #Sports, #Biology, #Entertainment For male intellectual workers, what are the best principles for rest? Passive rest often easily replaces active rest. Experts from Shanghai Wanzhong Andrology Hospital offer some advice to men who only focus on smoking and drinking after work to pass the time. 1. Approach life with a positive and optimistic attitude. This greatly helps maintain the stability of the nervous system. For men living in an era of information overload, approaching life with a positive and optimistic attitude is undoubtedly very beneficial in overcoming frequent nervous tension. Engaging in sports activities, establishing a reasonable work-rest schedule, practicing personal hygiene, and regularly immersing oneself in nature to cultivate one's temperament — these activities indirectly reflect a person's level of optimism towards life. Optimism itself is a great form of rest. 2. Overcome inertia and rest actively. Rest does not mean loose, uninteresting idleness. Rest should be vibrant and engaging. It's imp --- ## How Knowledge Workers Can Rest Better - URL: https://intl.sienovo.cn/blog/7268010 - Date: 2012-02-17 - Tags: #Activities, #Life, #Work, #Testing ■ Knowledge Workers: Catching Up on Sleep Won't Help Much You've spent a day writing copy, hosting meetings, and when it's all over, you sigh: "I'm so tired, I need a good night's sleep tonight." Our common sense tells us that our first reaction to fatigue is "go lie down." But this is a trap. Sleep is indeed an effective form of rest, but it's primarily suitable for those with sleep deprivation or for manual laborers. For manual laborers, "fatigue" is mainly caused by the accumulation of acidic substances in the body. If extremely tired, a static resting method should be adopted. Through sleep, lost energy can be replenished, and accumulated waste can be eliminated. If not too tired, one can also lie down in bed, close their eyes and rest quietly, allowing all muscles and nerves to fully relax before getting up and moving around. However, if you work in an office, your cerebral cortex is highly active while your body is in a low state of arousal. For this type of fatigue, sleep has --- ## Virtual Functions in C++ - URL: https://intl.sienovo.cn/blog/7233742 - Date: 2012-02-04 - Tags: #Function, #C++, #Class, #Compiler, #Delete, #DesignPatterns ## Virtual Functions in C++ (1) Virtual functions are a mechanism in C++ used to achieve polymorphism. The core idea is to access functions defined in derived classes through a base class. **I. Introduction** Virtual functions are a mechanism in C++ used to achieve polymorphism. The core idea is to access functions defined in derived classes through a base class. Suppose we have the following class hierarchy: ```cpp class A { public: virtual void foo() { cout << "A::foo() is called" << endl;} }; class B: public A { public: virtual void foo() { cout << "B::foo() is called" << endl;} }; ``` Then, when using it, we can: ```cpp A * a = new B(); a->foo(); // Here, although 'a' is a pointer to A, the function called (foo) is B's! ``` This example is a typical application of virtual functions, and through it, you might already have some concept of what they are. Their "virtual" nature lies in what's called "deferred binding" or "dynamic binding," where the call to a class function is not d --- ## C Implementation of Bitmap - URL: https://intl.sienovo.cn/blog/7233628 - Date: 2012-02-04 - Tags: #C, #Null, #File, #INI, #Test In fact, we use each element to represent a 32-bit binary string, so this element can store information about the presence of 32 adjacent numbers, and the array size is reduced to 10,000,000 / 32. For example, for the number 89256, since 89256 mod 32 = 2789 with a remainder of 8, we should set the 8th bit (starting from the least significant bit) of the 32-bit string in `a[2789]` to 1. Basic Operations: **[cpp]**  [view plain](http://blog.csdn.net/qibaoyuan/article/details/5914662# "view plain") [copy](http://blog.csdn.net/qibaoyuan/article/details/5914662# "copy") 1. #define WORD 32   2. #define SHIFT 5 //// Shift 5 bits. Left shift is equivalent to multiplying by 32, right shift is equivalent to integer division by 32.   3. #define MASK 0x1F // 31 in hexadecimal   4. #define N 10000000   5. int bitmap\[1 + N / WORD\];   6. /\*  7.  \* Set bit function - uses "|" operator. i & MASK is equivalent to modulo operation.  8.  \* For m mod n, when n is a power of 2, m mod n = m --- ## Common VxWorks Commands - URL: https://intl.sienovo.cn/blog/7233501 - Date: 2012-02-04 - Tags: #Statistics, #Task, #Function, #Network, #String, #Internet 1. Task-Related Commands sp function,[arg1],...,[arg9] - Starts a task, accepts up to 9 arguments, default priority 100, stack 20000 bytes. period n,function,[arg1],...,[arg8] - Creates a task that periodically calls 'function' every 'n' seconds, accepts up to 8 arguments. repeat m,function,[arg1],...,[arg8] - Creates a task that repeatedly calls 'function' 'm' times. If m=0, it calls indefinitely. Accepts up to 8 arguments. ts tidX - Suspends a task tr tidX - Resumes a suspended task td tidX - Deletes a task i tidX - Displays basic task information. If the parameter is 0, displays all tasks. ti tidX - Displays detailed task information, including registers, stack, etc. tt tidX - Displays the task's function call relationships. checkStack tidX - Displays historical statistics of task stack usage. If the parameter is 0, displays all tasks. [tidX can be either the task ID or the task name] 2. System Information lkup ["string"] - Searches and lists functions and global variables con --- ## Summary of the Pigeonhole Principle - URL: https://intl.sienovo.cn/blog/7172567 - Date: 2012-01-03 - Tags: none ## A Summary of the Pigeonhole Principle: Scope of Application and Usage Tips The Pigeonhole Principle is a fundamental concept in mathematics and computer science that states that if n items are put into m containers, with n > m, then at least one container must contain more than one item. This principle has far-reaching implications in various fields, including computer science, data analysis, and problem-solving. ### What is the Pigeonhole Principle? The Pigeonhole Principle is often used to prove the existence of a certain property or condition in a system. It is based on the idea that when you have more items than containers, it is impossible to distribute the items evenly among the containers, resulting in at least one container containing more than one item. ### Scope of Application The Pigeonhole Principle has numerous applications in computer science, including: * **Hashing**: When using hash tables to store data, the Pigeonhole Principle can be used to show that collisi --- ## Question: Given positive integers a1, a2, ..., an. If (a1 + a2 + ... + an) - n + 1 pigeons are placed into n pigeonholes, then it is guaranteed that for some i, the i-th pigeonhole contains at least ai pigeons. - URL: https://intl.sienovo.cn/blog/7169953 - Date: 2012-01-01 - Tags: none ## Pigeonhole Principle in Action: A Mathematical Proof The pigeonhole principle is a fundamental concept in mathematics that states that if n items are put into m containers, with n > m, then at least one container must contain more than one item. However, the given problem takes this principle to the next level by introducing a new condition: if (a1 + a2 + ... + an) - n + 1 pigeons are placed into n pigeonholes, then it is guaranteed that for some i, the i-th pigeonhole contains at least ai pigeons. In this article, we will explore how to prove this mathematical statement. To begin with, let's understand the given condition. We have n pigeonholes and a total of (a1 + a2 + ... + an) - n + 1 pigeons. The key here is to recognize that the number of pigeons is not just a simple sum of the individual values ai, but rather a modified sum that takes into account the number of pigeonholes. The expression (a1 + a2 + ... + an) - n + 1 can be seen as a way to "normalize" the sum of the indivi --- ## Prove that among any n+2 positive integers, there exist two positive integers whose difference is divisible by 2n or whose sum is divisible by 2n - URL: https://intl.sienovo.cn/blog/7169947 - Date: 2012-01-01 - Tags: #n2 ## Proving a Divisibility Property Using the Pigeonhole Principle In number theory, the Pigeonhole Principle is a fundamental concept that helps us establish the existence of certain relationships between objects. In this article, we will explore a specific application of this principle to prove a divisibility property among positive integers. The problem statement claims that among any n+2 positive integers, there exist two positive integers whose difference is divisible by 2n or whose sum is divisible by 2n. To tackle this problem, we will use the Pigeonhole Principle, which states that if n items are put into m containers, with n > m, then at least one container must contain more than one item. ## Applying the Pigeonhole Principle Let's consider n+2 positive integers. We want to show that there exist two numbers among these integers whose sum or difference is divisible by 2n. To do this, we will construct n+1 pigeonholes based on the residue classes modulo 2n. The pigeonholes ar --- ## break can exit while(1) and do...while() loops - URL: https://intl.sienovo.cn/blog/7164079 - Date: 2011-12-30 - Tags: none 1) break can exit while(1) and do...while() loops --- ## The Relationship Between GPRS and TBF - URL: https://intl.sienovo.cn/blog/7109375 - Date: 2011-12-28 - Tags: #Session, #Algorithm, #Network, #Mobile, #Optimization TBF (Temporary Block Flow) marks the beginning and end of a user's session. When analyzing GPRS traffic, we often focus on PDCH traffic and the conversion between TCH and PDCH (if the device supports it), using these metrics to assess whether a cell is busy or idle. While this macro-level analysis can reflect the overall load of a cell, it does not accurately represent the actual user experience with GPRS. For example, consider one user accessing the internet via a laptop, occupying four PDCH channels. This user's session corresponds to a single TBF. In this case, although the PDCH channels are heavily loaded, the user experience is excellent because the user exclusively occupies four channels. The RLC-layer bandwidth is roughly 50 Kb/s, and with coding schemes CS3 or CS4, it can be even higher. In contrast, if 100 users share these same four channels—meaning 100 concurrent sessions (i.e., approximately 100 TBFs, though in practice the number is limited by the maximum TBFs per PDCH)—e --- ## IoT and TD Achieve a Win-Win - URL: https://intl.sienovo.cn/blog/7107993 - Date: 2011-12-28 - Tags: #Network, #ChinaMobile, #Terminal, #SinaWeibo, #Telecom, #Product The speed of TD-SCDMA (hereinafter referred to as "TD") construction in our country has astonished its global counterparts. Starting from the issuance of 3G licenses in 2009, nationwide network coverage was achieved in just one year. Currently, meticulous network planning and optimization have brought TD network's core indicators close to 2G levels, and terminal and application development continues to achieve new breakthroughs. However, while TD network construction has achieved impressive results, the revenue it brings to telecom operators remains very limited. "High investment, low return" will hinder the healthy development of TD. Against the backdrop of the "Two Industrializations" integration, the development of the Internet of Things (IoT) has received widespread attention and strong support from the state and society. IoT can be implemented based on TD, and at the same time, TD can leverage the momentum of IoT development to continuously expand its market and achieve large-sca --- ## TD Technology Forum - URL: https://intl.sienovo.cn/blog/7107904 - Date: 2011-12-28 - Tags: none ## Introduction to TD-SCDMA Forum and its Significance The TD-SCDMA (Time Division Synchronous Code Division Multiple Access) technology forum is a platform for discussing and sharing knowledge on TD-SCDMA technology. In this article, we will explore the TD-SCDMA forum and its significance in the telecommunications industry. ## What is TD-SCDMA? TD-SCDMA is a 3G wireless communication technology that uses a combination of time division and code division multiple access to provide high-speed data transfer rates and low latency. It was developed by a consortium of Chinese companies, including Datang Telecom Technology and Science Company Limited, and has been widely adopted in China and other parts of Asia. ## TD-SCDMA Forum Overview The TD-SCDMA forum is a online platform that provides a space for industry experts, researchers, and developers to share knowledge, discuss technical issues, and collaborate on projects related to TD-SCDMA technology. The forum is hosted by the TD-SCDMA --- ## How to Read Materials for Shenlun - URL: https://intl.sienovo.cn/blog/7107880 - Date: 2011-12-28 - Tags: #360, #c ## How to Read Materials for Shenlun As a technical writer for Sienovo, an edge-AI/industrial computing company, I've come across various documents and materials that require careful reading and comprehension. One such material is the Shenlun, a Chinese-language document that requires a deep understanding of its contents. In this article, we'll explore how to read materials like Shenlun effectively, highlighting key strategies and techniques to help you grasp its meaning. ### Understanding Shenlun Before diving into the reading process, it's essential to understand what Shenlun is. Shenlun is a Chinese-language document that typically consists of essays, articles, or other written content. It's often used in educational settings, such as in Chinese-language exams or assessments. To read Shenlun effectively, you need to be familiar with Chinese language and culture. ### Pre-Reading Preparation Before starting to read Shenlun, prepare yourself by: * Familiarizing yourself with the --- ## CNCC China National Computer Conference - URL: https://intl.sienovo.cn/blog/7107775 - Date: 2011-12-28 - Tags: #Microsoft, #Phone, #Event [http://cncc.ccf.org.cn/information/111104.aspx](http://cncc.ccf.org.cn/information/111104.aspx) ## CNCC2011 - Microsoft Research Asia "Mobile Computing" Technical Reception **2011 China National Computer Conference – Microsoft Research Asia "Mobile Computing" Technical Reception** **Event Introduction:** The China National Computer Conference (CNCC), hosted by the China Computer Federation (CCF), is the largest and highest-level academic, technical, and industrial conference in China's computing field. CNCC2011 will be held in Shenzhen from November 24 to 26. In conjunction with the conference, Microsoft Research Asia will host a technical reception on the evening of November 24, focusing on "Mobile Computing." We will invite speakers from academia and Microsoft Research Asia to share their ongoing research in mobile computing. The event will also include a buffet dinner, providing a relaxed environment for technical discussions. All interested conference attendees are welcome --- ## Illustrated Explanation of Recursive Binary Tree Traversal - URL: https://intl.sienovo.cn/blog/7069497 - Date: 2011-12-14 - Tags: #Algorithm ## Illustrated Explanation of Recursive Binary Tree Traversal Binary tree traversal is a fundamental operation in computer science, serving as the basis for various binary tree operations. Understanding the implementation process of binary tree traversal is essential to grasp the concepts of binary trees. In this article, we will delve into the recursive implementation of binary tree traversal, using the in-order traversal algorithm as an example. ### Introduction to Binary Trees A binary tree is a data structure in which each node has at most two children, referred to as the left child and the right child. This structure allows for efficient storage and retrieval of data. Binary trees are commonly used in algorithms, data storage, and database systems. ### In-Order Traversal Algorithm The in-order traversal algorithm visits the left subtree, the current node, and then the right subtree. This process is recursive, meaning that the algorithm calls itself for each subtree. The in-or --- ## What Role Does an Iterator Play in Programming? — A Summary - URL: https://intl.sienovo.cn/blog/7069044 - Date: 2011-12-14 - Tags: #iterator, #class, #algorithm, #null, #delete, #C++ 1. Similar to a pointer, but not actually a pointer. 2. Within a container, an iterator acts like a pointer to an element, but its implementation is not a pointer—it is an object. 3. On a broader level, iterators serve as a glue between containers and algorithms. On a more granular level, they resemble smart pointers. Try using the `copy` algorithm to deepen your understanding. :) 4. An iterator is essentially a pointer type for a container, allowing you to define an object that sequentially accesses each element within the container. 5. You'll quickly understand by looking at the source code. I was confused for a while too, but in practice, it's essentially a pointer implemented via `typedef`. ```cpp template class XXX { ... ... typedef T* iterator; typedef const T* const_iterator; }; ``` Suggestion: Refer to *C++ Primer* for deeper understanding. Source code reference: ```cpp Implementation: 1) Iterator.h #ifndef ITERATOR_H #define ITE --- ## Stack vs. Heap Differences - URL: https://intl.sienovo.cn/blog/7065849 - Date: 2011-12-13 - Tags: #DataStructures, #Windows, #Expansion, #Compiler, #Memory, #OS ## Stack vs. Heap Differences In this post, we will explore the fundamental differences between stack and heap memory in programs compiled with C/C++. Understanding these differences is crucial for effective memory management and can help prevent common programming errors such as memory leaks and stack overflows. ### Memory Allocation in C/C++ When a program is compiled using C or C++, it utilizes two primary types of memory allocation: stack and heap. Each serves a distinct purpose and has its own characteristics. 1. **Stack Memory** - The stack is automatically allocated and deallocated by the compiler. It is primarily used to store function parameters, local variable values, and return addresses. The stack operates similarly to a stack data structure, following the Last In First Out (LIFO) principle. - In Windows, the stack is a contiguous memory region that expands towards lower memory addresses. The maximum stack size is predetermined by the system, typically set to 2MB --- ## C++ Type Casting - URL: https://intl.sienovo.cn/blog/7053292 - Date: 2011-12-08 - Tags: #C++, #Class, #Compiler, #Programming, #Null, #Work dynamic_cast:      Typically used for conversions between base and derived classes, run-time cast. 　　const_cast:          Mainly used for conversions involving const and volatile qualifiers. 　　static_cast:          General-purpose conversion, no run-time check. Usually, if you're unsure which to use, go with this one. 　　reinterpret_cast: Used for conversions between unrelated types, such as converting a character pointer to an integer. 　　1) static_cast(a) 　　Handled by the compiler at compile time. 　　Converts address a to type T. T and a must be pointers, references, arithmetic types, or enumeration types. 　　In the expression static_cast(a), the value of a is converted to the type T specified in the template. During runtime, no type checking is performed to ensure the safety of the conversion. 　　static_cast can convert between built-in data types and only between related pointer types for classes. It allows pointer conversions up and down an inheritance hierarchy, but c --- ## Summary of const Usage in C/C++ - URL: https://intl.sienovo.cn/blog/6987091 - Date: 2011-11-18 - Tags: #Compiler, #file, #Storage, #Assembly, #fun Definition of const type: It indicates that the value of a variable or object cannot be updated. Its introduction aims to replace preprocessor directives. ********************Constants must be initialized******************** Purpose of const (1) Can define const constants. For example: ```cpp const int Max=100; int Array[Max]; ``` (2) Facilitates type checking. For example: ```cpp void f(const int i) { .........} ``` The compiler will know that `i` is a constant and cannot be modified. (3) Can protect the modified entity, preventing accidental modification and enhancing program robustness. Continuing with the previous example, if `i` is modified within the function body, the compiler will report an error. For example: ```cpp void f(const int i) { i=10;//error! } ``` (5) Provides a basis for function overloading. ```cpp class A { ...... void f(int i) {......} // A function void f(int i) const {......} // Overload of the previous function ...... }; ``` (6) Can save space --- ## Understanding (int *)&i and int increment(int * &i) - URL: https://intl.sienovo.cn/blog/6969352 - Date: 2011-11-14 - Tags: #null, #C Q1: #include "stdio.h" void main() { int i[] = {2, 3}; int *j = i; int **k = &j; // Double pointer, correct; int *p = NULL; // k = &i; // 'i' represents the array address, and '&i' also seems like a double pointer—why does this fail? // Error: cannot convert from 'int (*)[2]' to 'int **' // Isn't 'int (*)[2]' an array pointer? For example, int (*c)[2]; c = arry[3][2]. Here, 'c' is also used like a double pointer~ // i = (int *)&i; // Error: cannot convert from 'int *' to 'int [2]' // k = (int *)&i; // Error: cannot convert from 'int *' to 'int **' // k = (int *)i; // Error: cannot convert from 'int *' to 'int **' p = (int *)i; p = (int *)&i; // Both of these casts work. What's the actual difference between &i and i? Is & meaningless here? } A1: i = (int *)&i; // Error: cannot convert from 'int *' to 'int [2]' This line is definitely wrong because 'i', as an array name, is a pointer—but a constant pointer—and cannot be ass --- ## Pointers, References, and Handles - URL: https://intl.sienovo.cn/blog/6969277 - Date: 2011-11-14 - Tags: #Windows, #Null, #Storage, #Language, #C ## [Pointers, References, and Handles](http://www.cnblogs.com/cjyang/archive/2010/06/14/1758339.html) (1) A pointer is the memory address of an object; (2) A reference is an alias for an object, essentially a pointer with restricted functionality but higher safety; (3) A handle is a pointer to a pointer. A handle is essentially a piece of data, a Long (long integer) type of data. A handle is an identifier used to identify objects or items, much like our names. Windows is an operating system based on virtual memory. In such an environment, the Windows memory manager frequently moves objects around in memory to satisfy the memory needs of various applications. When an object is moved, its address changes. If addresses are constantly changing, how do we find the object? To solve this problem, the Windows operating system reserves some memory addresses for applications, specifically to record changes in the memory addresses of application objects. This reserved address (the location of --- ## Getting Started with Regular Expressions - URL: https://intl.sienovo.cn/blog/6870207 - Date: 2011-10-13 - Tags: #Regex, #TextEditing, #Microsoft, #Tools, #Regex, #Perl In computer science, a regular expression is a single string that describes or matches a sequence of strings conforming to a particular syntactic rule. In many text editors or other tools, regular expressions are commonly used to search for and/or replace text content that matches a specific pattern. Numerous programming languages support string manipulation using regular expressions. For example, Perl has a powerful regular expression engine built in. The concept of regular expressions was originally popularized by Unix utilities such as sed and grep. Regular expressions are often abbreviated as "regex", with singular forms like regexp or regex, and plural forms such as regexps, regexes, or regexen. A regular expression is essentially a formula for matching a class of strings based on a certain pattern. Many people avoid using them because they appear strange and complex—unfortunately, this article won't change that impression. However, with a bit of practice, you may find that writ --- ## What is Orthogonality - URL: https://intl.sienovo.cn/blog/6870204 - Date: 2011-10-13 - Tags: #Database ## Understanding Orthogonality in Computing “**Orthogonality**” is a term borrowed from geometry, where it describes the relationship between two lines that intersect at a right angle. In this context, orthogonal lines, like the coordinate axes, are independent of each other. This independence means that moving along one line does not affect your position projected onto the other line. This concept is crucial in various fields, including computing, where it signifies a form of independence or decoupling among components. ### The Concept of Orthogonality in Computing In computing, orthogonality refers to the design principle where changes in one component do not impact others. This principle is essential for creating systems that are modular, maintainable, and scalable. When components are orthogonal, it allows for easier updates and modifications without the risk of unintended consequences in other parts of the system. For example, consider a well-designed software application that --- ## Structure and Representation of Positive Integer Solutions to the Diophantine Equation x² + y² + z² = w² - URL: https://intl.sienovo.cn/blog/6869936 - Date: 2011-10-13 - Tags: none ## Structure and Representation of Positive Integer Solutions to the Diophantine Equation x² + y² + z² = w² The Diophantine equation x² + y² + z² = w² is a well-known problem in number theory, where we seek to find positive integer solutions to this equation. In this article, we will explore the structure and representation of such solutions. ### Introduction The Diophantine equation x² + y² + z² = w² is a classic example of a problem that has been studied extensively in number theory. It is a type of quadratic equation, where we seek to find integer solutions to the equation. In this article, we will focus on the structure and representation of positive integer solutions to this equation. ### Background To understand the Diophantine equation x² + y² + z² = w², we need to have a basic understanding of number theory and quadratic equations. The equation is a quadratic equation in four variables, x, y, z, and w. We are seeking to find integer values of x, y, z, and w that satisfy th --- ## Study Notes on Descartes' Guiding Principles of Thought 10 - URL: https://intl.sienovo.cn/blog/6868779 - Date: 2011-10-13 - Tags: none ==================       Principle Ten ================== If the mind is to become skillful, it must seek out (and enjoy seeking out, be eager to seek out) what others have already discovered. It must also systematically survey even the most minute results of human art, but primarily those results that presuppose a certain order. I confess that I was born with a mind that has always found its greatest pleasure in research not by listening to others' explanations, but by discovering these truths through my own diligent efforts. This alone led me to study science when I was still young, so whenever the title of a book suggested new revelations, I would, without delving deeply into it, immediately try to see if, by virtue of some natural ingenuity given to me, I could perhaps achieve a similar result. I was careful not to rush through it, lest I spoil my innocent pleasure. This approach often succeeded, so much so that I eventually discovered that, by relying on confused and blind inqu --- ## Unix + The Art of Programming Study Notes 13 + Complexity: As Simple as Possible, but Not Simpler - URL: https://intl.sienovo.cn/blog/6867054 - Date: 2011-10-12 - Tags: #Unix, #Programming, #Lisp, #Documentation, #Work, #Assembly \============================== Complexity As Simple as Possible, but Not Simpler \============================== Several core issues that triggered over a decade of internal conflicts in the Unix world will be discussed in this chapter. We begin with established Unix practices and professional terminology, then delve slightly deeper than the rest of this book. Rather than attempting to simply provide answers to these questions—because definitive answers do not exist—we aim to offer conceptual insights that help you discover your own solutions. 13.1 On Complexity 13.1.1 Three Sources of Complexity The Unix world has invested tremendous passion into questions about simplicity, complexity, and the optimal scale of software. Unix programmers have adopted a worldview in which simplicity is beautiful, elegant, and good, while complexity is ugly, bizarre, and evil. This passion for simplicity stems from practical experience: complexity is cost. Preliminary definition of complexi --- ## Learning Notes on The Art of Unix Programming 12 - On Optimization Timing and Techniques - URL: https://intl.sienovo.cn/blog/6866658 - Date: 2011-10-12 - Tags: #Optimization, #Unix, #Programming, #Profiler, #Database, #DataStructures \===============      Optimization =============== Regarding optimization, the first question in Unix is when *not* to optimize, and only then how to optimize. The most effective optimizations are often things *other* than optimization itself, such as a clear and clean design. 12.1 Don't Just Do Something, Stand There The programmer's toolkit. Reasons not to optimize include waiting for hardware to upgrade itself in a few months, freeing up time for more meaningful tasks such as algorithm complexity, clean and clear design, structured design, and transparent, visible design. 12.2 Estimate First, Then Optimize If there is concrete evidence that an application is running slowly, then (and only then) should you consider optimizing the code. But before implementing, estimate first. Unix has profilers: make good use of them. Interpreting profiler diagnostics is an art. 12.3 The Perils of Non-Locality The most effective way to optimize code is to keep it short and simple. Never throw --- ## Exploring the Definition of Software Architecture - URL: https://intl.sienovo.cn/blog/6866024 - Date: 2011-10-12 - Tags: #DataStructures, #Internet, #Servers, #Algorithms, #WebServices, #Communications Although software architecture has been widely applied in the field of [software engineering](http://baike.baidu.com/view/1659.htm), to date there is still no universally accepted software architecture definition. Numerous experts and scholars have characterized [software](http://baike.baidu.com/view/37.htm) [architecture](http://baike.baidu.com/view/1188494.htm) from different perspectives and angles. Some representative definitions include: 　　(1) Dewayne Perry and Alex Wolf defined it as follows: software architecture is a structured collection of elements in a certain form—specifically, components—including processing components, data components, and connecting components. Processing components handle data manipulation, data components represent the information being processed, and connecting components link and integrate different parts of the architecture. This definition emphasizes the distinction among processing, data, and connecting components—a distinction largely preserv --- ## Overview of Search Engine Technology - URL: https://intl.sienovo.cn/blog/6859989 - Date: 2011-10-10 - Tags: #SearchEngine, #FullTextSearch, #Lucene, #Google, #Internet, #Database ## Overview of Search Engine Technology #### Foreword Recently, I've been quietly reviewing my studies and organizing my thoughts at school (job hunting is on hold for now). In my spare time, I often read articles related to search engine technologies, encountering many concepts and techniques I hadn't touched before, such as web crawling, page fetching, word segmentation, indexing, querying, ranking, and so on. I was particularly amazed by each brilliant architectural diagram, which sparked an urge to document them for future reference. This article begins with the most basic concept of a search engine, moves to the concept of full-text search, explains web spiders, word segmentation technology, system architecture, and ranking (incorporating Google search engine's technical principles), then delves into the principles of image search, and finally concludes with an introduction to several open-source search engine software. As this article is my first foray into search engine tech --- ## Writing a Simple Shell Command Parser - URL: https://intl.sienovo.cn/blog/6858230 - Date: 2011-10-10 - Tags: #Shell, #Testing, #Redirect, #Jobs, #Input, #RedHat Writing a Simple Shell Command Parser Environment: RedHat 9.0    Kernel 2.4.20 vi text editor  6.1.320 gcc  3.2.2-5 Implementation Steps: Step 0: Write the simplest shell command interpreter. This program is adapted from APUE Example 1-5, and does not support commands with arguments. The following tasks need to be completed: 1. The command interpreter starts as an infinite loop. 2. Print a command prompt. 3. Read the command line input into an array. Commands do not need to support arguments. You may use functions such as getc(), fgets(), or scanf(). 4. If using fgets(), the resulting string includes the trailing newline character, so you must replace the final "\n" in the command string with "\0". 5. Create a child process and use exec to execute the command. 6. The parent process calls waitpid() to wait for the child process to exit, then continues to the next loop iteration. Step 1: Write a shell command interpreter that can handle commands w --- ## What is the Working Principle of Shell in Linux? - URL: https://intl.sienovo.cn/blog/6858062 - Date: 2011-10-10 - Tags: #shell, #linux, #Operation, #LinuxKernel, #Terminal, #Language The most important system program that the Linux system provides to users is the Shell command language [interpreter](http://wenwen.soso.com/z/Search.e?sp=S%E8%A7%A3%E9%87%8A%E7%A8%8B%E5%BA%8F&ch=w.search.yjjlink&cid=w.search.yjjlink). It is not part of the kernel but runs outside the kernel in user mode. Its basic function is to interpret and execute various commands entered by the user, providing an interface between the user and the Linux kernel. After system startup, the kernel creates a process for each [terminal user](http://wenwen.soso.com/z/Search.e?sp=S%E7%BB%88%E7%AB%AF%E7%94%A8%E6%88%B7&ch=w.search.yjjlink&cid=w.search.yjjlink) to execute the Shell interpreter. Its execution process generally follows these steps: (1) Reads the command line entered by the user from the [keyboard](http://wenwen.soso.com/z/Search.e?sp=S%E9%94%AE%E7%9B%98&ch=w.search.yjjlink&cid=w.search.yjjlink). (2) Analyzes the command, using the command name as the filename, and transforms other parameters --- ## Anti-Mac Interface (GUI vs. CLI): When to Use Command Line Interfaces - URL: https://intl.sienovo.cn/blog/6856084 - Date: 2011-10-09 - Tags: #Task, #Work ## Anti-Mac Interface (GUI vs. CLI): When to Use Command Line Interfaces In this article, we will explore the differences between Graphical User Interfaces (GUIs) and Command Line Interfaces (CLIs), discussing when it is more effective to use each type of interface. Understanding the strengths and weaknesses of both can help you choose the right tool for your tasks, especially as complexity increases. ### The Strengths of Visual Interfaces Visual interfaces, or GUIs, are designed to be intuitive and user-friendly. They excel in scenarios where users are dealing with a small number of objects and simple behaviors. For example, tasks like opening a file, dragging and dropping items, or adjusting settings can be easily accomplished through a visual interface. The immediate feedback and visual representation of actions can make GUIs appealing for everyday tasks. ### The Limitations of GUIs However, as the number of objects or the complexity of tasks increases, the limitations of GUIs --- ## A Small Handbook on How to Join Open Source Projects - URL: https://intl.sienovo.cn/blog/6854840 - Date: 2011-10-09 - Tags: #ProjectManagement, #Patch, #Tools, #Comments, #Git, #Merge ## [A Small Handbook on How to Join Open Source Projects](http://www.linuxfans.org/archives/346 "Read the full article 'A Small Handbook on How to Join Open Source Projects'") 2011-04-13 npcomet Posted in [Open Source Development](http://www.linuxfans.org/archives/category/%e5%bc%80%e6%ba%90%e5%bb%ba%e8%ae%be "View all articles in Open Source Development") | [3 Comments »](http://www.linuxfans.org/archives/346#comments "Comments on 'A Small Handbook on How to Join Open Source Projects'") Participating in open source projects can quickly improve your technical skills and teach you many valuable techniques that are not taught in school but are extremely helpful in the workplace. A resume that includes open source project contributions is also increasingly valued by employers. Therefore, in recent years, tech enthusiasts have been paying more and more attention to open source projects. However, many students who are interested and passionate about open source projects still use incorre --- ## How to Contribute to Linux Open Source Projects – GNOME Project Listing - URL: https://intl.sienovo.cn/blog/6854630 - Date: 2011-10-09 - Tags: #linux, #applet, #documentation, #extension, #character, #manager ## GNOME Project Listing Locate the project's official website and find the project founder. Contact them via email — although in most cases, direct contact can be made through the website. Then submit your work, or contribute by reporting bugs and submitting patches. [http://vsftpd.beasts.org/](http://vsftpd.beasts.org/) [http://gftp.seul.org/](http://gftp.seul.org/) There are many projects under GNOME: [http://projects.gnome.org/](http://projects.gnome.org/) **（一）Example One** This page is a listing of GNOME-related projects and their related web pages. For a more complete, searchable list of applications, check out [the GNOME Software Map](http://www.gnome.org/softwaremap/). ### A * [a11y](http://projects.gnome.org/accessibility), GNOME Accessibility for people with disabilities * [Abiword](http://www.abisource.com/), Word Processor * [Accerciser](http://live.gnome.org/Accerciser), Interactive accessibility explorer * [Agnubis](http://projects.gnome.o --- ## Linux 2.6.36 Kernel Optimization Guide - URL: https://intl.sienovo.cn/blog/6854573 - Date: 2011-10-09 - Tags: #Linux, #Debugging, #Deprecated, #Attributes, #Transformation, #Filesystems Linux 2.6.36 Kernel Optimization Guide Author: [Ken Wu](http://kenwublog.com/about) Email: ken.wug@gmail.com Please credit the original link when reposting this document: [http://kenwublog.com/docs/linux-kernel-2-6-36-optimization.htm](http://kenwublog.com/docs/linux-kernel-2-6-36-optimization.htm)! **Introduction** This document is a minimal optimization guide for Linux Kernel 2.6.36. The author aims to compile a kernel with optimal performance suitable for application development (with a GNOME graphical interface). The kernel tuning described here is primarily achieved by selecting optimal compilation options, removing unnecessary drivers, reducing kernel size, and disabling certain security features. The optimization results are mainly reflected in OS boot time, memory usage after boot, and application runtime performance. Due to the author's limited expertise, please feel free to provide corrections if any inaccuracies are found. **Runtime Environment** Virtual Machine --- ## What is the Linux Kernel - URL: https://intl.sienovo.cn/blog/6854563 - Date: 2011-10-09 - Tags: #LinuxKernel, #Linux, #Debian, #Ubuntu, #Sun, #Task The kernel is the most important feature of what we commonly refer to as the 'Linux technological marvel'. In IT terms, the kernel is both the heart and brain of an operating system, as it controls the fundamental hardware. The kernel is the core of the operating system, possessing many essential functions such as virtual memory, multitasking, shared libraries, demand loading, shared copy-on-write executables, and TCP/IP networking capabilities. The origin of the Linux kernel can be traced back to 1991, when Finnish university student Linus Torvalds wrote and first released Linux. Although the Linux ecosystem has since grown far beyond Torvalds himself, he still maintains control over the Linux kernel and is the sole copyright holder of the Linux name. Since the release of Linux version 0.12, Linux has been licensed under the GPL (General Public License) free software license. The Linux kernel itself is not an operating system; it is a component of a complete operating system. Linu --- ## The Tale of the Clever Unix Programmer - URL: https://intl.sienovo.cn/blog/6853101 - Date: 2011-10-08 - Tags: #Unix ## The Tale of the Clever Unix Programmer This article delves into the world of Unix programming, focusing on a particular technique employed by experienced programmers to overcome a common challenge. You will learn how to use a clever trick to simplify your Unix programming tasks and improve your overall productivity. ### Introduction The Unix operating system has been a cornerstone of the computing world for decades, offering a powerful and flexible platform for developers to build upon. One of the key features of Unix is its rich set of tools and utilities, which can be combined in various ways to achieve complex tasks. However, as with any complex system, there are often multiple ways to accomplish a task, and not all of them are equally efficient or effective. ### The Problem Imagine you have a large dataset that needs to be processed in batches, with each batch being a subset of the original data. You want to write a Unix script that reads the data, processes each batch, and --- ## The Role of dup and dup2 - URL: https://intl.sienovo.cn/blog/6852682 - Date: 2011-10-08 - Tags: #CGI, #Terminal, #DataStructures, #Scripting, #Server, #SoftwareDev #### The Role of dup and dup2 dup and dup2 are two very useful system calls, both used to duplicate a file descriptor. They are often used to redirect a process's stdin, stdout, and stderr. The prototypes for these two functions are as follows: #include     int dup( int oldfd );     int dup2( int oldfd, int targetfd )     Using the dup function, we can duplicate a descriptor. When passed an existing descriptor, it returns a new descriptor, which is a copy of the one passed to it. This means that these two descriptors share the same \[url=http://www.pcdog.com/special/1002/index.html\]data structure\[/url\] . For example, if we perform an lseek operation on one file descriptor, the position of the first file will be the same as the second. Below is a code snippet illustrating the use of the dup function:     int fd1, fd2;     ... fd2 = dup( fd1 );     It's important to note that we can establish a descriptor before calling fork, which has the same effect as establishing a de --- ## Linux Standard Input and Standard Output Files - URL: https://intl.sienovo.cn/blog/6852611 - Date: 2011-10-08 - Tags: #linux, #terminal, #shell ## Understanding Linux Standard Input and Standard Output Files In Unix, Linux, and BSD systems, there are three special files that play a crucial role in handling input and output operations. These files are known as Standard Input (STDIN), Standard Output (STDOUT), and Standard Error (STDERR). In this article, we will explore the purpose and behavior of these special files, and how they are represented in the shell. ### Standard Input (STDIN) Standard Input, located at `/dev/stdin`, typically refers to keyboard input. When you type commands in the terminal, the input is directed to STDIN, which is represented by file descriptor 0 in the shell. This means that any input you provide to the shell, such as typing a command or entering data, is considered STDIN. ### Standard Output (STDOUT) Standard Output, located at `/dev/stdout`, usually refers to the terminal, i.e., the display. When you run a command, the output is directed to STDOUT, which is represented by file descriptor 1 in --- ## sng, png, Text Format Conversion - URL: https://intl.sienovo.cn/blog/6852411 - Date: 2011-10-08 - Tags: #Tools, #Encryption, #Terminal ## sng, png, Text Format Conversion In this blog post, we will explore the functionality of the `sng` tool, which offers a unique method for converting PNG images into text files and vice versa. You'll learn how to manipulate image data in a text format, enabling creative applications such as image processing and even encryption. ### What is sng? [sng](http://sng.sourceforge.net/) is an intriguing tool that allows users to convert PNG format images into a corresponding text file that records the image's information. This two-way conversion capability means that not only can you generate a text representation of an image, but you can also take a formatted text file and convert it back into a PNG image. This functionality opens up various possibilities for image manipulation and processing. ### Practical Use Cases You might wonder about the practical applications of this tool. While it may seem like a novelty at first, the ability to convert binary files into formatted text files ca --- ## Why Unix Prefers Processes Over Threads - URL: https://intl.sienovo.cn/blog/6852269 - Date: 2011-10-08 - Tags: #Unix, #Task, #Programming, #API, #Storage Threads — Intimidation or Threat? Although Unix developers have long been accustomed to computation through multiple cooperating processes, they have never developed a spontaneous tradition of using threads. The fact that threads were only recently imported from other systems is no accident — Unix developers' aversion to threads is by no means a mere historical coincidence. From the perspective of complexity control, threads are a poor alternative compared to lightweight processes with independent address spaces: threads are a concept native to operating systems where process creation is expensive and IPC (Inter-Process Communication) capabilities are weak. By definition, while sub-threads within a process typically have their own private stack for local variables, they share the same global memory space. Managing race conditions and critical sections within this shared address space is notoriously difficult and becomes a breeding ground for increased complexity and bugs. It's --- ## Comprehensive Guide to Linux Processes, Signals, IPC, and gprof Usage (Reprinted) - URL: https://intl.sienovo.cn/blog/6852194 - Date: 2011-10-08 - Tags: #Linux, #Struct, #Buffer, #String, #Server, #GCC Comprehensive Guide to Linux Processes, Signals, IPC, and gprof Usage (Reprinted) Source: ChinaUnix Blog　Date: 2008.03.14 15:48　(Comments: ) [Comment here](http://linux.chinaunix.net/bbs/thread-983262-1-1.html) Thanks to 007xiong, Hoyt, and others. This article is excellent. Concerned that the original link might disappear someday, I'm making a backup here. Original link: [http://www.mwjx.com/aboutfish/private/book/linux_c.txt](http://www.mwjx.com/aboutfish/private/book/linux_c.txt) Introduction to C Programming under Linux Compiled and written by: 007xiong Original: Hoyt et al. (1) Table of Contents 1) Introduction to Linux Program Design -- Basics 2) Introduction to Linux Program Design -- Processes 3) Introduction to Linux Program Design -- File Operations 4) Introduction to Linux Program Design -- Time Concepts 5) Introduction to Linux Program Design -- Signal Handling 6) Introduction to Linux Program Design -- Message Management 7) Introduction to Linux P --- ## What Kind of Talent Does Microsoft Engineering Academy Seek? - URL: https://intl.sienovo.cn/blog/6851653 - Date: 2011-10-08 - Tags: #Microsoft, #Testing, #Product, #SoftwareTesting, #ProjectManagement, #Career **What Kind of Talent Does Microsoft Engineering Academy Seek?** "Programmer" magazine Recently, a news report about Microsoft Asia Engineering Academy struggling to recruit suitable developers sparked a significant reaction. After the report was published online, many people viewed it as a sign of Microsoft's arrogance. In fact, as a reporter who happened to be at the interview site, I can say that beyond the author of that news piece overly embellishing figures, its mass media positioning also prevented it from delving deeper into the reasons that President Zhang Hongjiang valued more. As a newly established Microsoft Asia Engineering Academy, more than a dozen new projects and product developments have already been put on the agenda, requiring a rapid expansion of personnel to over a hundred within a short period. Zhang Hongjiang stated: "Over the past five months, our management team has spent most of its time on recruitment, hoping to attract more outstanding software talent t --- ## Herd Shot: Group Photo from the Linux Kernel Developer Summit - URL: https://intl.sienovo.cn/blog/6837879 - Date: 2011-09-30 - Tags: #LinuxKernel, #Linux, #IBM, #Networking I just came across a [group photo from the Linux Kernel Developers Summit](http://lwn.net/images/conf/lce2007/ks-annot.jpg) that has historical value—sharing it with you all. It features Torvalds (roughly in the center), Andrew Morton (current primary kernel maintainer, second row, second from the right), Alan Cox (one of Linux's top contributors and foreword writer for *Linux Application Development*—short, bearded, between two pillars), Jonathan Corbet (author of *Linux Device Drivers*, first row, first from the left), and his co-author Greg Kroah-Hartman (to the left of the central pillar), Tso speaking at the podium (to the right of the central pillar—check out his [resume](http://thunk.org/tytso/), he's a heavyweight too, from IBM), Olaf Kirch (author of *The Linux Network Administrators' Guide*), and others. There's a Chinese developer, [Yang Li](http://wiki.zh-kernel.org/intro/li_yang) from Freescale. [Herbert Xu](http://gondor.apana.org.au/~herbert/) is from Australia, and the --- ## Linux Creator Slams C++: A Garbage Language for Bad Programmers - URL: https://intl.sienovo.cn/blog/6837754 - Date: 2011-09-30 - Tags: #Linux, #C++, #Language, #Programming, #C, #Git ## Linux Creator Slams C++: A Garbage Language for Bad Programmers In a recent debate, Linux creator Linus Torvalds expressed his strong disapproval of the C++ programming language, calling it a "garbage language" that is only suitable for bad programmers. This article delves into the controversy surrounding C++ and its suitability for large-scale software development. ## Background C++ is a high-level, object-oriented programming language that was designed to build upon the success of C. It was created by Bjarne Stroustrup in the 1980s and has since become one of the most popular programming languages in the world. However, C++ has also been criticized for its complexity, verbosity, and lack of portability. ## The Debate The debate between Torvalds and Dmitry Kakurin, a Microsoft developer, started when Kakurin criticized the use of C in the Git version control system. Git is a popular open-source project that was created by Torvalds, and it is written primarily in C. Kakurin arg --- ## Embedded Linux Keyboard Driver Development (Part 1): Task - URL: https://intl.sienovo.cn/blog/6837464 - Date: 2011-09-30 - Tags: #Linux, #Embedded, #Task ## Embedded Linux Keyboard Driver Development (Part 1): Task In this blog post, we will explore the development of a Linux keyboard driver for the 2416 board, focusing on integrating the driver with a user-space application. This project aims to create a functional driver for the three side keys on the board, allowing for dynamic loading into the Linux kernel and providing an interface to control on-screen menu navigation. By the end of this post, you will have a clear understanding of the objectives and initial implementation steps for this project. ### 1. Objective Description The primary goal of this project is to develop a Linux driver that interfaces with the three side keys on the 2416 board. This driver will be dynamically loaded into the Linux kernel, enabling it to interact with user-space applications. The specific functionalities we aim to achieve include: - **Menu Navigation**: Users will be able to move up and down through a menu displayed on the screen using the side --- ## How to Maintain a Good Mood? - URL: https://intl.sienovo.cn/blog/6837428 - Date: 2011-09-30 - Tags: none To be written. Recommended Harvard Open Course Video "Positive Psychology": [http://v.163.com/special/sp/positivepsychology.html](http://v.163.com/special/sp/positivepsychology.html) --- ## Ten Good Habits of Excellent Programmers, Summarized from "The Art of Unix Programming" - URL: https://intl.sienovo.cn/blog/6837279 - Date: 2011-09-30 - Tags: #Unix, #Programming, #API, #DataStructures, #Algorithms, #Documentation Reviewing the ten good habits of excellent programmers, as summarized from *The Art of Unix Programming*. 1) Easy to understand and composable. 2) "Do one thing well." 3) Think carefully about code composition and how to build your own set of APIs. (Gain a deeper understanding of real-world system states. Refactor.) 4) [Currently in short supply]: The ability to formally and clearly describe and understand systems, and to express them in flowcharts or pseudocode. (Once you reach this stage, writing code becomes a technical task—something you can accomplish by consulting references, experimenting, trying, and asking others.) 1) Modules, encapsulation, and optimal module size Strong cohesion and loose coupling: Minimize dependencies on other components when solving small problems. Modules shouldn't be too large: Modules shouldn't be too small: Otherwise, you'll need to write many interfaces and pass numerous parameters, increasing cognitive load and code volume. 2) First --- ## The Ultimate Dietary Guide for Computer Users - URL: https://intl.sienovo.cn/blog/6836885 - Date: 2011-09-30 - Tags: #Activity, #Work, #Biology, #C ### Radiation Protection To prevent damage from electromagnetic radiation, increase intake of goji berry products and pollen products. Goji berries nourish the liver and improve eyesight, offering protection to the retina from light damage, scavenging free radicals, and resisting X-ray radiation. Pollen contains abundant biological nutrients such as nucleic acids, amino acids, vitamins, niacin, and folic acid. The amino acids in pollen can enhance the vitality of peripheral blood granulocytes in irradiated animals, protect tissue structures like bone marrow, spleen, and thymus, increase SOD content and activity in the blood, and reduce lipid peroxide levels, making it suitable for developing anti-radiation foods. ### Calorie Control Computer users often sit for long periods, leading to reduced energy expenditure. If daily dietary intake provides excessive calories that the body cannot utilize, they will be converted into fat, leading to obesity. Therefore, calorie intake should be --- ## How Programmers Can Prevent Mental Fatigue: Snack on Some Nuts in the Afternoon - URL: https://intl.sienovo.cn/blog/6836870 - Date: 2011-09-30 - Tags: #Work, #Activity, #Fitness, #VitaminB, #Healthcare, #Music [How Programmers Can Prevent Mental Fatigue: Snack on Some Nuts in the Afternoon](http://blog.csdn.net/hustbill/archive/2005/04/14/347962.aspx) A doctor friend offered some advice to help combat afternoon drowsiness and prevent mental fatigue. The key lies in balancing the body's acid-alkaline levels. Overuse of the brain or physical exhaustion can make bodily fluids more acidic. Prolonged acidity in the blood may lead to degeneration of brain nerve functions. Therefore, it's recommended to consume more alkaline foods such as kelp, leafy greens, citrus fruits, legumes, and tea, while reducing intake of acidic foods like meat and sugar. 　　To restore energy and vitality, programmers are advised to snack on dried nuts during afternoon tea—such as peanuts, cashews, almonds, and walnuts. These are rich in vitamin B, vitamin E, protein, essential fatty acids, and minerals. Also beneficial are fruits high in vitamin C. At breakfast, lunch, and dinner, increase intake of vegetables like to --- ## How Programmers Can Effectively Manage Their Thinking - URL: https://intl.sienovo.cn/blog/6836853 - Date: 2011-09-30 - Tags: #Work, #Task, #Tool, #Phone, #Activity, #Music Abstract: Undoubtedly, we live in an information-rich era. But too much of a good thing can be harmful—excessive information often leads to a scarcity of knowledge and attention. Amid an overwhelming flood of data, it's easy to lose focus. Instead of drifting along the information superhighway, it's better to actively manage your thinking. 　　— Excerpted from *Pragmatic Thinking and Learning: Refactor Your Wetware*, published by Turing Education 　　A good question has no answer. It is not a bolt to be tightened, but a seed to be planted—one that can grow into an oasis of thought. 　　— John Anthony Ciardi (1916–1986), American poet and critic 　　Undoubtedly, we live in an information-rich era. But too much of a good thing can be harmful—excessive information often leads to a scarcity of knowledge and attention. Amid an overwhelming flood of data, it's easy to lose focus. Instead of drifting along the information superhighway, it's better to actively manage your thinking. 　　As in Chapt --- ## How to Install MySQL 5.0 on Linux - URL: https://intl.sienovo.cn/blog/6834148 - Date: 2011-09-29 - Tags: #MySQL, #Linux, #Database, #Debian, #User For the clearest guide, refer to Baidu Wenku: [http://wenku.baidu.com/view/571968976bec0975f465e25b.html](http://wenku.baidu.com/view/571968976bec0975f465e25b.html) \============================================= **(I) How to Install MySQL Database on Linux** \============================================= My first setback was with RPM installation. It reported a MySQL version conflict, preventing the installation from proceeding. After querying with `rpm -q`, I attempted to remove the system's pre-installed version (3.x.x) using `rpm -e`. However, RPM mercilessly returned a slew of other errors. Due to dependencies with other software, version 3.x.x could not be removed. My initial positive impression of RPM vanished in an instant. As the saying goes, "Among three people, there must be one who can be my teacher." I immediately found Alin on MSN. When I asked him how to uninstall or upgrade MySQL using RPM, he gleefully told me that he upgraded it in just one minute using "Debian." --- ## Exploring the Essence of Modular Programming - URL: https://intl.sienovo.cn/blog/6834033 - Date: 2011-09-29 - Tags: #Programming, #DLL, #Windows, #OO, #API, #Tools Exploring the Essence of Modular Programming **[Opening]** The concept of a "module" is widely used and highly context-dependent. For example:                           An ant says to a toad: "Wow, you're huge!"                           An elephant says to a toad: "Wow, you're tiny!"                           (The toad asks: "Am I big or small?") From the elephant's perspective, the toad is small. From the ant's perspective, the toad is large. You don't know the true size of the toad because you're standing from the toad’s own point of view. (Just a joke.) A module represents the granularity with which we divide a larger entity. For a class as a large entity, modules might be individual member functions; for an executable program, modules could be DLLs; for a Windows operating system, modules might include subsystems like the file system. To understand what a module is, you must first understand what that larger entity is in your mind. **[Introduction]** 1) Modules --- ## Understanding `static` and `extern` Qualifiers for Variables and Functions - URL: https://intl.sienovo.cn/blog/6833971 - Date: 2011-09-29 - Tags: none ## Understanding `static` and `extern` Qualifiers for Variables and Functions In C and C++ programming, the `static` and `extern` qualifiers play crucial roles in managing variable and function scope and linkage. This article will delve into the distinctions between these qualifiers, their usage, and how they can be applied to enhance the organization and functionality of your code. ### Global Variables and Functions Global variables and functions are accessible throughout the entire program. However, their scope can be modified using the `static` and `extern` qualifiers. #### `static` Qualifier The `static` qualifier is used to limit the visibility of a variable or function to the file in which it is declared. This means that a `static` variable or function cannot be accessed from other files, which helps prevent naming conflicts and unintended interactions between different parts of a program. - **Static Variables**: When a variable is declared as `static` within a function, it --- ## tar Compression and Decompression Commands - URL: https://intl.sienovo.cn/blog/6833718 - Date: 2011-09-29 - Tags: #Linux [tar Compression and Decompression Commands](http://www.cnblogs.com/siylz/articles/1674984.html) tar \-c: Create a compressed archive \-x: Extract \-t: View contents \-r: Append files to the end of an archive \-u: Update files in the original archive These five options are standalone commands; one of them must be used for either compression or extraction. They can be combined with other options, but only one of these five may be used at a time. The following options are optional, depending on your needs during compression or extraction. \-z: Use gzip compression \-j: Use bzip2 compression \-Z: Use compress compression \-v: Display progress \-O: Extract files to standard output The following option, -f, is required: \-f: Specify the archive file name. Remember, this option must be the last one in the command, and only the archive filename should follow it. \# tar -cf all.tar \*.jpg This command packages all .jpg files into an archive named all.tar. -c indicates --- ## Exploring the Reasons for Controllable Complexity in Linux - URL: https://intl.sienovo.cn/blog/6833617 - Date: 2011-09-29 - Tags: #Linux, #Makefile, #DataStructures, #Programming, #Optimization, #API ## Exploring the Reasons for Controllable Complexity in Linux In this article, we will delve into the factors that influence complexity control in software development, particularly in the context of Linux systems. We will also explore methods to reduce program design complexity, which is crucial for creating robust and maintainable software. ## I. Summary of Factors Affecting Complexity Control ### 1) Architecture A solid architecture is foundational to any complex software system, including operating systems like Linux. Without a well-thought-out architecture, the software can become unstable and prone to failure. Just as a poorly constructed building may collapse, a weak architectural design can lead to significant issues in software functionality and reliability. Therefore, investing time in designing a robust architecture is essential for long-term success. ### 2) Modularity The principle of modularity is vital in managing complexity. The mantra of "keeping it clean, keeping i --- ## Linux Command Cheat Sheet - URL: https://intl.sienovo.cn/blog/6833300 - Date: 2011-09-29 - Tags: #Linux, #Windows, #Graphics, #VirtualMachine, #Terminal ## Switching Modes in Linux: A Quick Reference Guide When working with Linux in a virtual machine or on a physical machine, it's essential to know how to switch between different modes, such as GUI (Graphical User Interface) and command-line mode. In this article, we'll explore the various methods to switch between these modes, troubleshoot common issues, and learn how to handle program crashes. ## Switching from GUI Mode to Command-Line Mode When working in a virtual machine, it's often necessary to switch from GUI mode to command-line mode. In Linux, you can achieve this by running the command `init 3`. However, in Windows virtual machine environments, the default keyboard shortcuts for switching between modes (Ctrl+Alt+F1~F7) are usually disabled. Fortunately, there's a workaround that consistently works: press `Ctrl+Alt+Space+F1` to switch from GUI/Terminal mode to command-line mode, and `Ctrl+Alt+Space+F7` to switch back. ## Switching from Command-Line Mode to GUI Mode To sw --- ## Detailed Explanation of ANSI C Standard File I/O Functions - URL: https://intl.sienovo.cn/blog/6830811 - Date: 2011-09-28 - Tags: #Language, #C, #IO, #Stream, #File, #FP ## I. Overview 1. The ANSI C file system is built upon the buffered file system of earlier C versions (also known as formatted or high-level file systems). 2. **Difference between Streams and Files:** The level of abstraction provided by C's I/O system between the programmer and the device being used is called a stream, while the physical device is called a file. The C file system can operate on various devices such as terminals, disk drives, and tape drives. Regardless of how different these devices are, the ANSI file system converts them into logical devices called "streams," providing great device independence. In C, the logical concept of a file refers to anything from a disk file to a terminal printer. A stream is associated with a file by performing an open operation. Once a file is opened, information can be exchanged between the program and that file. Not all files have the same capabilities; for example, disk files support random access, but terminals do not. This illustra --- ## What Type of Pointer is FILE *p? - URL: https://intl.sienovo.cn/blog/6830757 - Date: 2011-09-28 - Tags: #File, #Stream, #Character, #Struct, #Token The `FILE` structure includes several fields, such as: - `level`: Indicates how full or empty the buffer is. - `flags`: Contains the status flags for the file. - `fd`: Represents the file descriptor. - `hold`: A temporary storage for characters. - `bsize`: Specifies the size of the buffer. - `buffer`: A pointer to the data buffer. - `curp`: Points to the current position for reading or writing. - `istemp`: Indicates if the file is temporary. - `token`: Used for various internal purposes. Overall, the `FILE` pointer serves as a handle for file operations, encapsulating all necessary information about the file. ## Initialization of FILE Pointer Before you can perform any operations on a file, you must first declare and initialize a `FILE` pointer. This is done using the `fopen` function, which opens a file and returns a pointer to the `FILE` structure associated with that file. Here’s how you can initialize a `FILE` pointer: --- ## 【Practice & Reflection】Qualities of a Programmer - URL: https://intl.sienovo.cn/blog/6828699 - Date: 2011-09-28 - Tags: #Compiler, #Programming, #UnitTest, #Work, #Agile The blueprint must be clear; Be brave in your attempts; Be meticulous when writing code; If it's not clear enough, don't write code. Redraw the sketch and flowcharts;         How to improve the efficiency of trying out ideas? Be thoughtful in your approach. Often, modifying one variable in a program can affect other variables and structures that reference or depend on it. Therefore, before making any changes, you must first consider all the places that need modification, including header files, functions, and so on. This preparation ensures you stay organized and maintain a good state of mind.         In contrast, acting like a headless chicken, making a small change, then trying to compile to see what errors the compiler produces, and then fixing each compiler error one by one. This method has the following disadvantages: 1) Your thinking ability doesn't improve, it's difficult to control complexity, and you can't manage moderately large programs; 2) It's prone to hidden danger --- ## Understanding the Differences and Relationships Between continue, break, return, and switch - URL: https://intl.sienovo.cn/blog/6828574 - Date: 2011-09-28 - Tags: #Programming, #Algorithms, #Languages, #C **_Question: In a switch statement, must there be a break statement after the case statement sequence?_** **Answer:** 1) Using a `break` statement in a `switch` statement terminates the sequence of statements. When a `break` is encountered, the program continues execution from the line of code immediately following the entire `switch` statement, effectively "exiting" the `switch`. The `break` statement is optional. If you omit the `break`, the program will fall through and execute the next `case`. If you intend to have multiple cases share the same logic (fall-through behavior), you can intentionally omit the `break` statement. The `switch` statement is generally more efficient than `if-else` chains when handling multiple selection conditions. 2) Do you understand what `break` does? Without `break`, the program will continue executing the subsequent case statements. \========================================================================================== Typically, in C lan --- ## Debugging Summary for Chat Program File Transfer - URL: https://intl.sienovo.cn/blog/6826190 - Date: 2011-09-27 - Tags: #Chat <<<<<<< HEAD will either fail to compile (if the compiler enforces strict type checking) or, in some permissive environments, silently copy only the pointer value, leaving `dest` pointing to the same memory as `src`. This breaks the expectation that `dest` holds its own copy of the string, which is essential when the source buffer may be reused or overwritten later in the file‑transfer routine. ### Why `strcpy()` Is the Correct Choice The standard library function `strcpy()` copies the contents of one null‑terminated string into another buffer, ensuring that each buffer owns its own copy of the data: ======= ## Debugging Summary for Chat Program File Transfer In this article, we will explore a critical debugging note for file transfer functionality in chat programs, particularly focusing on string handling in C programming. The note emphasizes the importance of proper string assignment techniques to avoid common pitfalls. ### Understanding String Assignment in C When working wit --- ## Overview of Protocol Layers - URL: https://intl.sienovo.cn/blog/6825844 - Date: 2011-09-27 - Tags: #Network, #Interface, #Network, #Algorithm ## Overview of Protocol Layers In this article, we will delve into the concept of protocol layers in network design, exploring how they function, their importance, and how they contribute to the overall architecture of a network. Understanding these layers is crucial for designing efficient and scalable networks, as they help manage complexity and ensure smooth communication between different systems. To reduce the complexity of network design, most networks adopt a stack of overlapping layers. Each layer is built upon the one below it and serves the layer above, while hiding its internal implementation details from higher layers. This layered approach allows for modular design, where changes in one layer do not necessarily impact others, thus simplifying troubleshooting and development. ### The Concept of Layers and Protocols The fundamental idea is that a specific piece of software (or hardware) provides a service to users while concealing the internal state and algorithmic detai --- ## GDB Debugging in Linux - URL: https://intl.sienovo.cn/blog/6825542 - Date: 2011-09-27 - Tags: #Linux, #Assembly, #DebuggingTools, #File, #Compiler This article is written for programmer friends who primarily work on Windows operating systems but need to develop cross-platform software, as well as programming enthusiasts. GDB is a powerful, command-line based program debugging tool released by the GNU open-source organization, running on UNIX/LINUX operating systems. While GDB has many commands, we only need to master about ten of them to largely complete daily basic program debugging tasks. | Command | Explanation | Example | |---|---|---| | `file ` | Loads the executable program file to be debugged. Since GDB is usually executed in the same directory as the program being debugged, the filename does not need a path. | `(gdb) file gdb-sample` | | `r` | Short for Run, executes the program being debugged. If no breakpoints were set previously, the entire program will execute; if breakpoints exist, the program will pause at the first available breakpoint. | `(gdb) r` | | `c` | Short for Continue, resumes execution of th --- ## A Detailed Introduction and Usage of Linux Core Dumps - URL: https://intl.sienovo.cn/blog/6825413 - Date: 2011-09-27 - Tags: #Linux, #Function, #Unix, #File, #Work, #Storage =============================================================== **A Detailed Introduction and Usage of Linux Core Dumps** =============================================================== When developing (or using) a program, the most frustrating situation is when it crashes unexpectedly. Although the system itself remains unaffected, we might encounter the same issue again later. At such times, the operating system dumps the memory contents of the crashed program, providing valuable information for us or a debugger to analyze. This process is known as a *core dump*. 1. What is "core"? Before semiconductors were used as memory materials, humans used magnetic coils for memory storage (invented by An Wang). These coils were called "core," and memory built from them was known as *core memory*. Today, with the rapid development of the semiconductor industry, core memory is obsolete. However, in many contexts, people still refer to memory as "core." 2. What i --- ## Structure Definition and Initialization - URL: https://intl.sienovo.cn/blog/6822378 - Date: 2011-09-26 - Tags: #struct, #Storage, #date, #Language, #c Objective: Understand structure types, structure variables, and structure initialization, and the relationships between these three concepts. **Structure Definition** The general form for defining a structure is: **struct StructureName** **{** **MemberList** **}** The member list consists of several members, each of which is a component of the structure. Each member must also have a type declaration. For example: ```c struct stu { int num; char name[20]; int age; } ``` **Declaration of Structure Type Variables** A structure definition does not define a variable; rather, it defines a **data type**. This type is user-defined and can be used just like the simple data types inherent to the language (e.g., `int`). The structure itself does not allocate memory as data. What is actually stored in memory as data are the **variables** defined using this structure type. How much memory space does a structure variable occupy? This is determined by the definition of the structure ty --- ## Causes and Debugging Methods for Segmentation Faults in Linux - URL: https://intl.sienovo.cn/blog/6822004 - Date: 2011-09-26 - Tags: #Linux, #Signal, #Function, #Library, #Cmd, #Compiler In short, a segmentation fault occurs when a program accesses an invalid memory segment—typically one it has no permission to access, or that does not even have corresponding physical memory. The most common case is accessing address 0. Generally, a segmentation fault happens when memory access exceeds the memory space allocated by the system to the process. This limit is usually stored in the GDTR register, a 48-bit register where 32 bits hold a pointer to the GDT (Global Descriptor Table), 13 bits store the GDT index, and the final 3 bits indicate whether the program is loaded in memory and its CPU execution privilege level. The GDT itself consists of 64-bit entries, each storing information such as the starting address and segment limit of code and data segments, page swapping settings, execution privilege level, and memory granularity. When a program attempts to access memory beyond its permitted bounds, the CPU triggers a protection exception, resulting in a segmentation fault. --- ## Summary of Linux Chatroom Debugging Experience - URL: https://intl.sienovo.cn/blog/6804482 - Date: 2011-09-23 - Tags: #Linux, #Chat ## Summary of Linux Chatroom Debugging Experience Debugging can be a frustrating experience, especially when working with complex systems like Linux. In this article, we'll share a critical lesson learned from a Linux chatroom debugging experience that can save you hours of headaches in the future. ### The Importance of `memset()` When working with memory in Linux, it's essential to clear it before writing to it. This is where `memset()` comes in. This function fills a block of memory with a specified value. In the context of debugging, `memset()` is crucial for ensuring that memory is properly initialized before use. `memset()` is very important. Develop the habit of clearing memory before writing to it. Otherwise, strange situations may sometimes occur, perhaps because the buffer contains data that wasn't fully overwritten. To illustrate this point, consider a scenario where you're working with a buffer and you're not clearing it before writing to it. If the buffer contains resi --- ## How Does a Server Manage Thousands of Client Socket Connections? - URL: https://intl.sienovo.cn/blog/6801207 - Date: 2011-09-22 - Tags: #Server, #Socket, #Communication ## How Does a Server Manage Thousands of Client Socket Connections? In today's digital landscape, servers often face the challenge of managing thousands of client connections simultaneously. This article explores effective strategies for handling these connections without overwhelming system resources, ensuring efficient communication between the server and its clients. ### Understanding the Challenge When a server is tasked with managing a vast number of socket connections, one might wonder about the feasibility of creating a separate thread for each client. For instance, if a server needs to handle 10,000 clients, would it really create 10,000 threads? The answer is a resounding no. This approach would lead to significant inefficiencies and potential system slowdowns due to the overhead associated with managing such a high number of threads. ### Key Strategies for Managing Client Connections 1. **Use I/O Completion Ports** One of the most effective methods for managing multi --- ## Difference Between .c and .h Files (The Relationship Between Header Files and Implementation Files) - URL: https://intl.sienovo.cn/blog/6800672 - Date: 2011-09-22 - Tags: #Compiler, #Include, #C, #Language, #Work, #Makefile [**Difference Between .c and .h Files**](http://blog.163.com/xiaotu_sh2008/blog/static/683125962009103045557443) A simple question: What is the difference between .c and .h files? After studying C for several months, I feel more and more confused. Subroutines can be defined either in a .c file or in a .h file — so what exactly is the difference in usage between these two? Reply #2: Do not define subroutines in .h files. Function definitions should be placed in .c files, while .h files should only contain declarations. Otherwise, if included multiple times, it will lead to errors due to duplicate function definitions. Reply #3: .h files are for declarations only and do not generate code after compilation. Reply #4: The purpose is to achieve software modularity, making the software structure clear and also easier for others to use your code. From a pure C language syntax perspective, you can technically place anything in a .h file, because `#include` is completely equiv --- ## Usage of extern in C Language - URL: https://intl.sienovo.cn/blog/6800525 - Date: 2011-09-22 - Tags: #Language, #C, #Fun In the C language, the `extern` specifier is used before the declaration of a variable or function to indicate that "this variable/function is defined elsewhere and needs to be referenced here." 1. `extern` for variable declarations. For example, if file `a.c` needs to reference the variable `int v` from `b.c`, you can declare `extern int v` in `a.c`, and then you can reference `v`. It's important to note that the linkage property of the referenced variable `v` must be external. This means that for `a.c` to reference `v`, it doesn't just depend on declaring `extern int v` in `a.c`, but also on `v` itself being accessible. This touches upon another topic in C language — variable scope. Variables that can be referenced by other modules using the `extern` specifier are usually global variables. Another very important point is that `extern int v` can be placed anywhere in `a.c`. For instance, you can declare `extern int v` at the beginning of the `fun` function definition in `a.c`, and t --- ## Important Data Structures in Linux C Development — Structures - URL: https://intl.sienovo.cn/blog/6800443 - Date: 2011-09-22 - Tags: #DataStructures, #Linux, #C, #Struct ## Important Data Structures in Linux C Development — Structures In Linux driver development, understanding data structures is crucial, and among these, the `struct` (structure) is the most commonly used and significant. However, its usage can often lead to confusion due to operator precedence and the way expressions are evaluated. This article will clarify the operator precedence related to structures and provide examples to illustrate how to correctly interpret and use them in C programming. ### Understanding Operator Precedence To effectively work with structures in C, it is essential to grasp the concept of operator precedence. In C, the following four operators have the highest precedence: 1. The structure member access operator: `.` 2. The structure pointer member access operator: `->` 3. The function call operator: `()` 4. The subscript operator: `[]` These operators bind most tightly to their operands, which means that expressions involving these operators must be carefull --- ## Why does Linux extensively use the `static` keyword to modify function and struct definitions? - URL: https://intl.sienovo.cn/blog/6800410 - Date: 2011-09-22 - Tags: #Linux, #Language, #Multithreading, #Struct, #C, #2010 Q: Why does Linux extensively use the `static` keyword to modify function and struct definitions? The Linux kernel code heavily uses the `static` keyword; it's seen everywhere, whether for functions or struct definitions. What is the purpose of doing this? And how should multi-threaded data sharing and thread-specific data content be considered? A: 1. I personally believe it's because Linux is written in C, and its codebase is enormous, making name conflicts prone to occur. Therefore, `static` is used to reduce the incidence of such conflicts. Using `static` reduces the scope of functions or variables. The access scope for `static` functions is file-level, whereas ordinary functions have project-level scope. The C language doesn't have namespaces, so `static` is probably used to mitigate conflicts. 2. Similar to the two previous points, `static` can reduce the usage of functions, thereby facilitating maintenance (avoiding modifications in multiple places simultaneously). However, t --- ## Understanding the Essence Through Questions: What Exactly Is a Socket? - URL: https://intl.sienovo.cn/blog/6799575 - Date: 2011-09-22 - Tags: #Socket, #DataStructure, #Server, #Networking, #Server, #Unix **I. Introduction — The Purpose of Sockets: Solving Inter-Process Communication Between Computers** **_1. Relationship Between Socket and Process_** 1). Relationship between socket and process: Sockets enable communication between processes (IPC), and the socket interface consists of API functions for the TCP/IP network. 2). Inter-process communication (on the same machine) Inter-process communication (across different computers, requiring network connectivity) **_2. Relationship Between Socket and File — How to Understand That a Socket Is a Special Type of I/O?_** 1) Sockets were first introduced in Unix operating systems. If you understand Unix I/O, understanding sockets becomes much easier, because socket data transmission is essentially a special form of I/O. 2) File operations can be performed on sockets. 3) Sockets have file descriptors. A file descriptor is fundamentally a non-negative integer used for identification. Similar concepts include process IDs. **_3. Rel --- ## Socket, Ports, and Processes Q&A (Collected and Organized) - URL: https://intl.sienovo.cn/blog/6799417 - Date: 2011-09-22 - Tags: #Socket, #Attributes, #File, #Networking, #Struct, #Windows **1. How many ports does a computer have, what are they, and what are their purposes?** Ports are divided into three main categories: 1) **Well-known Ports (0–1023):** These are tightly bound to specific services. Communications on these ports typically indicate a specific protocol. For example, port 80 is always used for HTTP traffic. 2) **Registered Ports (1024–49151):** These are loosely associated with specific services. Many services use these ports, and they may also serve other purposes. For instance, systems often begin assigning dynamic ports around 1024. 3) **Dynamic and/or Private Ports (49152–65535):** These should theoretically not be assigned to services. In practice, most systems assign dynamic ports starting from 1024, though exceptions exist—such as SUN's RPC ports, which start from 32768. \---------------------------------------------------------------------------------------------------------------------------------- **2. A computer has only one IP address but --- ## Troubleshooting Compilation Errors for 《Advanced Programming in the UNIX Environment》(APUE2) Source Code on Linux - URL: https://intl.sienovo.cn/blog/6797596 - Date: 2011-09-21 - Tags: #Unix, #Linux, #Programming, #FreeBSD, #Function, #Reference ## Troubleshooting Compilation Errors for 《Advanced Programming in the UNIX Environment》(APUE2) Source Code on Linux ### Introduction I believe many friends, like me, who are eager to learn Unix programming, might have been disheartened when they excitedly got their hands on 《Advanced Programming in the UNIX Environment》, only to encounter a slew of errors when trying to compile the first example, `myls`. Today, I'm writing down the solutions, partly for my own record, and partly to help others who are struggling with the same issues to quickly enter the wonderful world of Linux. (Linux systems only) ### Troubleshooting Compilation Errors The compilation errors in the APUE2 source code can be resolved by following these steps: 1. First, you need to `make` the source code once. 2. Edit `Make.defines.linux` located in the `apue.2e` folder, which is generated after extracting the source code. 3. Change `WKDIR=/home/var/apue.2e` to your `apue.2e` directory. For example, if my APUE --- ## Advanced Programming in the Unix Environment: Compilation Methods - The Simplest Way to Compile APUE (Second Edition) - URL: https://intl.sienovo.cn/blog/6796948 - Date: 2011-09-21 - Tags: #Unix, #Programming, #FreeBSD, #Solaris, #Linux, #Include Reposted from [http://www.cnblogs.com/gaojunling/articles/1237611.html](http://www.cnblogs.com/gaojunling/articles/1237611.html) /*********************************************************************** \* Method 0 - The Simplest and Most Practical \* ***********************************************************************/ 1. Enter the `lib` directory in the source code folder:   cd lib 2. Run the make command:   make -f linux.mk 3. Copy the generated `libapue.a` and `apue.h` to your source code directory (e.g., your file directory). 4. Compile your source code using:   gcc -o ls1 ls1.c libapue.a 5. Success /*********************************************************************** \* Method 1 \* ***********************************************************************/ In each example program from *Advanced Programming in the Unix Environment* (using the second edition source code), you'll find this line: #include "apue.h"     This header file was cre --- ## GTK/Glade Program Development (Part 3) - URL: https://intl.sienovo.cn/blog/6796219 - Date: 2011-09-21 - Tags: #ProgramDev, #GTK, #Buffer, #Attributes, #Tree, #Insert Menu Widget In this section, our design is as follows: Clicking the 'Open' submenu under the 'File' menu in the main window will pop up a new window. Using menu widgets is relatively straightforward. Once designed, simply locate the function corresponding to the respective menu in `callbacks.c` and add your code there. Our main menu has two items: 'File' and 'Edit'. Under 'File', there are 'Open' and 'Save'. Under 'Edit', there are 'Copy' and 'Paste'. Creating Menu Widgets: /* Creating menu widgets involves many functions, but fortunately, Glade automatically generates the code. We don't need to worry about it. */ New functions used in this section: None I. Designing the Interface with Glade Steps: 1. Create a new Glade project. 　　　　　2. Place a window (400, 300), a fixed container, and a menu widget in order. 　　　　　3. Select the menu widget, then click the 'Edit Menu' button in the 'Properties' panel to edit the menu. 　　　　　4. When editing the menu, note: Menu labels can use Chines --- ## GTK/Glade Program Development (Part 2) - URL: https://intl.sienovo.cn/blog/6796212 - Date: 2011-09-21 - Tags: #Programming, #Button, #GTK, #Callback, #Signal, #User Spin buttons Common functions: Creating a spin button widget: /* Creating a spin button requires an "adjustment object," so you must also create an adjustment object. Below is the spin button widget automatically generated by Glade, which uses an adjustment object */ GtkObject *spinbutton1_adj; GtkWidget *spinbutton1; spinbutton1_adj = gtk_adjustment_new (1, 0, 100, 1, 10, 10); spinbutton1 = gtk_spin_button_new (GTK_ADJUSTMENT (spinbutton1_adj), 1, 0); New functions introduced in this section: Obtaining the current value of a spin button: Function name: gtk_spin_button_get_value_as_int Usage: gfloat spinvalue1; gint spinvalue2; spinvalue1 = gtk_spin_button_get_value(GTK_SPIN_BUTTON(spinbutton)); spinvalue2 = gtk_spin_button_get_value_as_int(GTK_SPIN_BUTTON(spinbutton)); Function name: sprintf() Usage: sprintf (buf, "%d", spinvalue1); Function name: lookup_widget() Usage: GtkWidget *label1 = lookup_widget (GTK_WIDGET(spinbutton), "lab --- ## gtk/glade Program Development (Part 1) - URL: https://intl.sienovo.cn/blog/6796201 - Date: 2011-09-21 - Tags: #ProgramDev, #RadioButton, #GTK, #Button, #Object, #Callback Reprinted from http://www.linuxforum.net/forum/gshowflat.php?Cat=&Board=kylix&Number=566950&page=0&view=collapsed&sb=4&o=all&fpart=all&vc=1 by [cuigf](http://www.linuxforum.net/forum/showprofile.php?Cat=&User=cuigf&Number=566950&Board=kylix&what=showflat&page=0&view=collapsed&sb=4&o=all&fpart=all&vc=1) I have installed GTK 2.0/Glade 2.10.0, system environment RH9. I plan to provide an introduction to GTK programming over the next month, and I hope for your support. Develop on Windows, then transfer the completed program to Linux. (No modifications to the source code are needed; just recompile and link once.) Required Development Tools: Dev-C++ 4.9.9.2 (for compiling and linking C programs) Glade (for graphical interface design) GTK Development Components Only two software packages are needed: devcpp-4.9.9.2_setup gtk-win32-devel-2.6.8-rc1 (includes Glade and GTK development components) Download URLs: [www.bloodshed.net](http://www.bloodshed.net/) gl --- ## How to Configure Qt (4.3.2) Environment on Linux Operating System - URL: https://intl.sienovo.cn/blog/6795983 - Date: 2011-09-21 - Tags: #Linux, #Qt, #Library, #Path, #Windows, #VirtualMachine **Download the open-source package: qt-x11-opensource-src-4.3.2.tar.gz. Extract: gunzip qt-x11-opensource-src-4.3.2.tar.gz tar xvf qt-x11-opensource-src-4.3.2.tar. Run the script: enter the qt-x11-opensource-src-4.3.2 directory and input ./configure to run the shell script, which tests the current system's essential configuration for software installation.** Download the open-source package: qt-x11-opensource\-src-4.3.2.tar.gz Extract: gunzip qt-x11-opensource-src-4.3.2.tar.gz tar xvf qt-x11-opensource-src-4.3.2.tar Run the script: Enter the qt-x11-opensource-src-4.3.2 folder and input `./configure` to run the shell script program, which tests essential configuration information of the current [system](http://www.stuhack.com/safe/xitong/) for software installation. Compile: gmake Install: gmake install Environment variables: Edit `/etc/profile` using `vi`, and append the following lines at the end of the file: PATH=/usr/local/Trolltech/Qt-4.3.2/bin: --- ## Solution for win7 VMware ifconfig showing only IPv6, and Samba - URL: https://intl.sienovo.cn/blog/6795241 - Date: 2011-09-20 - Tags: #VMware, #Interface, #Windows, #Up, #Terminal, #C In win7 VMware, if ifconfig only shows IPv6 and no IPv4 like in an XP environment, how do you use Samba? Or how do you share files with Windows? Here's a solution. **Problem 1: Only IPv6** ```cpp [root@localhost ~]# ifconfigeth0 Link encap:Ethernet HWaddr 00:0C:29:E1:98:55 inet6 addr: 2001:250:3000:5a06:20c:29ff:fee1:9855/64 Scope:Global inet6 addr: fe80::20c:29ff:fee1:9855/64 Scope:Link UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:412806 errors:5 dropped:38 overruns:0 frame:0 TX packets:38 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:41496217 (39.5 MiB) TX bytes:7915 (7.7 KiB) Interrupt:193 Base address:0x2000 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1/128 Scope:Host UP LOOPBACK RUNNING MTU:16436 Metric:1 RX packets:3217 errors:0 dropped:0 overruns:0 frame:0 --- ## Summary of Type Casting in C Language - URL: https://intl.sienovo.cn/blog/6794185 - Date: 2011-09-20 - Tags: #Language, #C, #Float, #Storage, #Assembly ● The value of a character variable is essentially an 8-bit integer, so its range is generally -128 to 127. A char variable can also be modified with `unsigned`, in which case the range of an `unsigned char` is 0 to 255 (some systems treat `char` as `unsigned char` by default, giving it a range of 0 to 255). ● If the operands on both sides of an operator are of different types, they must first be converted to the same type—lower types are converted to higher types—before the operation proceeds. The conversion rules are illustrated below: ``` double ←── float Higher ↑ long ↑ unsigned ↑ int ←── char, short Lower ``` ● The horizontal arrows indicate required conversions. For example, when two `float` values are used in an operation, even though they are of the same type, they are first promoted to `double` before the operation, and the result is also of type `double`. The vertical arrows indicate conversions when operands are of different types. For instance, when a `long` and an `i --- ## Initialization of C++ Struct and Class Instances - URL: https://intl.sienovo.cn/blog/6793689 - Date: 2011-09-20 - Tags: #C++, #OS, #Struct, #Compiler, #C I. If all data members of a class or struct are public, initialization can be performed using the brace-enclosed form as follows. Note: ① Regardless of the number of values, curly braces must be used for delimitation. ② Data members for which no value is specified will be automatically initialized to their default values by the compiler. ③ This method of object initialization requires all data members to be public. ④ This method of object initialization requires that no constructors be written in the class. ```cpp struct S { // class S has the same effect int x; unsigned short y; }; S testS1={100,123}; S testS2={200};// Data members for which no value is specified are initialized to default values; here, os2.y=0; S TestS[4]={ {100,10}, {200,20}, {300} };// Unspecified values are initialized to default values, e.g., os[2].y, os[3].x, os[3].y. ``` II. If data members are private or protected, or if constructors are provided, initializ --- ## Multithreading: Using Mutex Locks to Handle Mutual Exclusion of Global Variables - URL: https://intl.sienovo.cn/blog/6793407 - Date: 2011-09-20 - Tags: #Multithreading, #Unix, #Signal, #Programming, #Networking, #Linux Multiple threads share certain resources from the process's static data segment, such as global variables defined in the main thread. These are naturally accessible by other threads as well. On Unix and Linux platforms, we use mutex locks to handle mutual exclusion issues related to global variables. Consider a mutex variable, which is specifically associated with a particular variable. Data type: pthread\_mutex\_t Initialization: pthread\_mutex\_t macPIB\_mutex = PTHREAD\_MUTEX\_INITIALIZER; Operations: int pthread\_mutex\_lock(pthread\_mutex\_t \*mutex) // Locking function. If the mutex is already locked, this function blocks the program until the lock is released. int pthread\_mutex\_unlock(pthread\_mutex\_t \*mutex) // Unlocking function Mutex variables are suitable for preventing concurrent access to a shared variable. However, when we need to wait for a certain condition to occur, we prefer to sleep rather than continuously poll. In such cases, we can use condition varia --- ## Discussion on the String Terminator '' in C Language - URL: https://intl.sienovo.cn/blog/6792683 - Date: 2011-09-20 - Tags: #Language, #C, #Storage '\0' is 8-bit 00000000. Since there is no corresponding character in character types, it is written this way. In numeric types, it represents the number 0. When storing numeric types, the most significant bit determines the sign. If all other bits are 0, isn't that just 0? '\0' is an escape character, meaning it tells the program that this is not the character '0', but rather the binary representation of the number 0 directly inserted, because the ASCII code for '0' is not 00000000. Originally, in C language, there are no dedicated string variables. A character array is typically used to store a string. Strings are always terminated by '\0'. Therefore, when storing a string into an array, the terminator '\0' is also stored in the array and serves as the flag for the string's end. With the '\0' flag, there's no need to use the character array's length to determine the string's length. '\0' is the string termination flag. For example, assigning a string to an array: u8 str1[]={"cxj --- ## Socket Communication, TCP Protocol: How a Server Sends Data to a Specific Client by IP and Port with Multiple Clients Connected - URL: https://intl.sienovo.cn/blog/6790901 - Date: 2011-09-19 - Tags: #socket, #server, #TCP ## Socket Communication with TCP Protocol: Sending Data to a Specific Client by IP and Port When working with socket communication using the TCP protocol, understanding how a server sends data to a specific client by IP and port is crucial. In this article, we will delve into the details of how a server obtains the endpoint address of a connected client and how it handles multiple clients connected simultaneously. ### Obtaining the Endpoint Address of a Connected Client When a socket connection is established, the server remains in a waiting state until it receives a connection request from a client. Once the connection is established, the server obtains the endpoint address of the connected peer. This endpoint address is unique for each client and consists of both the IP address and the port number. ### Randomly Assigned Ports when Directly Connecting without bind If a client connects directly to the server without calling the `bind` function, the system assigns a random port to --- ## Does a Parent Thread Continue Executing Its Own Code After Creating a Child Thread? (Compilation) - URL: https://intl.sienovo.cn/blog/6790625 - Date: 2011-09-19 - Tags: #MultiThreading, #Thread 1. A parent thread must terminate after its child threads. This is because child threads belong to the parent thread, and if the parent thread ends, all its child threads will also terminate. 2. If the parent thread ends before the child thread, the child thread will be forced to terminate simultaneously with the parent thread. The `Thread.Join()` method makes the parent thread wait until the child thread finishes. The `Abort()` method results in an irreversible termination of the thread. 3. The initial thread can be referred to as the main thread. If all foreground threads stop, the main thread can terminate, and all background threads will terminate unconditionally. The only difference between background threads and foreground threads is that background threads do not prevent the program from terminating. Once all foreground threads in a process have terminated, the CLR will completely terminate the process by calling the `Abort()` method on any remaining live background threads. --- ## In-Depth Exploration of the Difference Between C/C++ Array Names and Pointers - URL: https://intl.sienovo.cn/blog/6790535 - Date: 2011-09-19 - Tags: #DataStructure, #String, #Platform, #Language, #Work, #C **Introduction** 　　Pointers are a hallmark feature of the C/C++ language, and array names bear such a strong resemblance to pointers that, in many cases, array names can be used as pointers. As a result, many programmers become confused. Even numerous university instructors incorrectly teach students during C language courses: "An array name is a pointer." Fortunately—or unfortunately—my university professor was one of them. To this day, as I carry out C/C++ project development on a daily basis, I still encounter many programmers around me who hold onto the misconception that "an array name is a pointer." 　　This misunderstanding likely originates from a well-known C programming textbook in China. If this article manages to correct the widespread misunderstanding among Chinese programmers regarding array names and pointers, I will be deeply satisfied. Through this writing, I sincerely hope that domestic computer book authors will adopt a mindset of "in-depth exploration" and --- ## Enumerated Types (enum) in C/C++ - URL: https://intl.sienovo.cn/blog/6790256 - Date: 2011-09-19 - Tags: #Compiler, #C If a variable needs to hold several possible values, it can be defined as an enumerated type. The reason it's called 'enumeration' is that it lists all possible states or values that a variable or object might have. Let's illustrate with an example to make it clearer. Imagine a pencil case containing a pen. Before opening it, you don't know what kind of pen it is; it could be a pencil or a fountain pen. Since there are two possibilities, you can define an enumerated type to represent it! ```c enum box{pencil,pen};// Here, you've defined an enumerated type called 'box'. This enum contains two elements, also known as enumerators, which are 'pencil' and 'pen', representing a pencil and a fountain pen, respectively. ``` It's worth noting that if you want to define two variables of the same enumerated type, you can do so in the following two ways: ```c enum box{pencil,pen}; enum box box2;// Or simply 'box box2;' ``` Another way is to define them simultaneously during declaration. --- ## Understanding A::A() : _b(XXX,XXX) in C++ - URL: https://intl.sienovo.cn/blog/6790026 - Date: 2011-09-19 - Tags: #Class, #Compiler, #Variables, #Access, #Integer, #Nested 1) A::A() : \_b(XXX,XXX); The colon denotes member initialization, meaning the values XXX, XXX are passed to initialize the member variable \_b of type B. 2) This is called a member initializer list. 3) \_b is a member variable of class A. During the construction of A, the variable \_b is initialized. You should review the syntax of constructors to better understand this. 4) This is initialization; for example, constants must be initialized this way. 5) A() indicates the constructor of class A, specifying its scope; : \_b(XXX,XXX); refers to initializing the member variable. \=============================================================================================== [C++ Scope Resolution Operator (::) Explained](http://blog.csdn.net/lychee007/article/details/5386039 "C++中双冒号作用域解析符的含义") (Reprinted) [http://blog.csdn.net/lychee007/article/details/5386039](http://blog.csdn.net/lychee007/article/details/5386039) First, here are explanations from various sources — their --- ## GCC / G++ for Compiling C and C++ Source Code - URL: https://intl.sienovo.cn/blog/6789965 - Date: 2011-09-19 - Tags: #GCC, #C, #CPlusPlus, #Compiler, #String, #Assembly ## GCC / G++ for Compiling C and C++ Source Code GCC (GNU Compiler Collection) and G++ are the compilers used for compiling C and C++ source code, respectively. Understanding how these compilers work can significantly enhance your programming efficiency and troubleshooting skills. In this article, we will delve into the compilation process, the various command-line options available, and some common misconceptions surrounding the use of GCC and G++. ### Compilation Steps When GCC or G++ performs compilation, it generally involves four key steps: 1. **Preprocessing**: This step generates `.i` files from the source code. The preprocessor handles directives like `#include` and `#define`. 2. **Compiling**: The preprocessed file is then compiled into assembly language, resulting in `.s` files. 3. **Assembling**: The assembly code is transformed into object code (machine code), producing `.o` files. 4. **Linking**: Finally, the object code is linked together to create an executable progr --- ## Difference Between chmod 4755 and chmod 755 - URL: https://intl.sienovo.cn/blog/6785197 - Date: 2011-09-17 - Tags: #Linux ## Understanding the Difference Between `chmod 4755` and `chmod 755` In Linux, managing file permissions is crucial for maintaining system security and functionality. One of the commands used for this purpose is `chmod`, which allows users to set permissions for files and directories. This article will delve into the differences between `chmod 4755` and `chmod 755`, explaining what each command does and the implications of using them. ### File Permissions in Linux Before we explore the specific commands, it's important to understand how file permissions work in Linux. Permissions are represented by three types of access: read (r), write (w), and execute (x). Each type of permission is assigned a numerical value: - Read (r) = 4 - Write (w) = 2 - Execute (x) = 1 These values can be combined to set permissions for different users: - Read and execute (rx) = 5 (4 + 1) - Read and write (rw) = 6 (4 + 2) - Read, write, and execute (rwx) = 7 (4 + 2 + 1) ### Breakdown of `chmod 755` When --- ## QQ Communication Protocol - URL: https://intl.sienovo.cn/blog/6782666 - Date: 2011-09-16 - Tags: #QQ, #Communication, #Delphi, #Server, #CMD, #HTTPServer ## QQ Communication Protocol The QQ Communication Protocol is an essential framework for understanding how the QQ messaging service operates. This blog post will delve into the structure of the protocol, detailing its components, message types, and how they facilitate communication between users and servers. By the end, readers will have a clearer understanding of the protocol's functionality and its implementation in programming environments. ### Protocol Structure The QQ protocol is structured as follows: - **Message Header (T)**: The initial part of the message that contains metadata. - **Sender (T)**: Identifies the source of the message. - **Receiver (T)**: Identifies the intended recipient of the message. - **Message Type (T)**: Specifies the type of message being sent. - **Message Length (L)**: Indicates the size of the message content. - **Message Content**: The actual data being transmitted. The sender and receiver are represented by specific identifiers within the system --- ## Custom Application Layer Communication Protocol - URL: https://intl.sienovo.cn/blog/6782646 - Date: 2011-09-16 - Tags: #Testing, #NetworkProtocol, #Login, #Primitive, #Language, #String **1. Concept and Elements of Communication Protocols** In the OSI open systems interconnection reference model, data units between peer entities are encapsulated layer by layer at the sender and parsed layer by layer at the receiver. The packet that an N-th layer entity receives from the (N+1)-th layer is called a Service Data Unit (SDU). The N-th layer entity treats the SDU merely as data requiring service from this layer, encapsulating it into a Protocol Data Unit (PDU) that can be understood by the peer entity. This encapsulation process essentially adds Protocol Control Information (PCI)—agreed-upon control information between peer entities—to the SDU. To ensure functional independence across network layers and to facilitate implementation and maintenance, protocols are typically divided into multiple sub-protocols arranged in a hierarchical structure. The collection of these sub-protocols is commonly referred to as a protocol suite. Protocol layering helps break down complex p --- ## Microcontroller Communication Protocol Design - URL: https://intl.sienovo.cn/blog/6782630 - Date: 2011-09-16 - Tags: #Windows, #Character, #API, #Programming, #String, #Input Most modern instruments require operation through host computer software for convenient debugging and ease of use. This inherently involves communication. Based on several devices he has developed, the author has summarized a general approach to writing communication programs, covering both host and slave ends. 　　1. Custom Data Communication Protocol 　　The data protocol discussed here refers to the format of communication data packets built upon the physical layer. The physical layer of communication refers to common methods such as RS232, RS485, infrared, fiber optic, wireless, and so on. At this layer, the low-level software provides two basic operations: sending a byte of data and receiving a byte of data. All data protocols are built upon these two operations. Data in communication is often transmitted in the form of data packets, which we refer to as a data frame. Similar to TCP/IP protocols in network communication, a relatively reliable communication protocol typica --- ## Linux Inter-Process Communication via Message Queues - URL: https://intl.sienovo.cn/blog/6782569 - Date: 2011-09-16 - Tags: #Linux, #System, #Struct, #DataStructure, #Communication, #Null Message Queues: Benefits of using message queues: You can attach specific message types to messages. Message queues are used for inter-process communication on the same computer. Related system functions:        #include        #include        key\_t ftok(const char \*pathname, int proj\_id); This function generates an ID based on a file name. When the system establishes IPC communication (message queues, semaphores, and shared memory), an ID value must be specified.        #include        #include        #include        int msgget(key\_t key, int msgflg); This function creates a new message queue or retrieves an existing one.        #include        #include        #include        int msgsnd(int msqid, const void \*msgp, size\_t msgsz, int msgflg); This funct --- ## Demystifying C Language Pointers - URL: https://intl.sienovo.cn/blog/6782297 - Date: 2011-09-16 - Tags: #C, #Language, #Compiler, #Storage, #Fun, #Float A pointer is a special variable whose stored value is interpreted as an address in memory. To fully understand a pointer, you need to clarify four aspects: the pointer's type, the type it points to, its value (or the memory region it points to), and the memory space occupied by the pointer itself. Let's go through each in detail. First, declare a few pointers as examples: Example One: (1) int\* ptr; (2) char\* ptr; (3) int\*\* ptr; (4) int(\*ptr)\[3\]; (5) int\*(\*ptr)\[4\]; Pointer Type From a syntactic perspective, if you remove the pointer name from its declaration, what remains is the pointer's type — the inherent type of the pointer itself. Let's examine the pointer types in Example One: (1) int\* ptr; // pointer type is int\* (2) char\* ptr; // pointer type is char\* (3) int\*\* ptr; // pointer type is int\*\* (4) int(\*ptr)\[3\]; // pointer type is int(\*)\[3\] (5) int\*(\*ptr)\[4\]; // pointer type is int\*(\*)\[4\] Pretty straightforward, right? The me --- ## The Essence and Application Examples of Pointer Manipulation - URL: https://intl.sienovo.cn/blog/6782136 - Date: 2011-09-16 - Tags: none ## The Essence and Application Examples of Pointer Manipulation Pointer manipulation is a fundamental concept in programming, allowing developers to directly address and modify memory locations. Understanding how to effectively use pointers is crucial for efficient memory management and optimization in various applications. In this article, we will delve into the essence of pointer manipulation and explore several practical application examples. ### What are Pointers? Before diving into the intricacies of pointer manipulation, it's essential to understand the basic concept of pointers. A pointer is a variable that stores the memory address of another variable. This memory address is essentially a unique identifier that points to the location of the variable in memory. By using pointers, developers can indirectly access and modify the value of a variable. ### Pointer Arithmetic and Operations Pointer arithmetic is a fundamental aspect of pointer manipulation. It involves performing --- ## Differences Among memset, memcpy, and strcpy - URL: https://intl.sienovo.cn/blog/6782101 - Date: 2011-09-16 - Tags: #Struct **memset** is used to set all bytes in a specified memory block to a particular character. It is commonly used to initialize strings to `' '` or `'\\0'`. Example: `char a[100]; memset(a, '\\0', sizeof(a));` memset can also conveniently clear a structure-type variable or array. For example: ```c struct sample_struct { char csName[16]; int iSeq; int iType; }; ``` For the variable: `struct sample_struct stTest;` Typically, clearing `stTest` would require: ```c stTest.csName[0] = '\\0'; stTest.iSeq = 0; stTest.iType = 0; ``` With `memset`, this becomes much simpler: `memset(&stTest, 0, sizeof(struct sample_struct));` For an array: ```c struct sample_struct TEST[10]; ``` Then use: `memset(TEST, 0, sizeof(struct sample_struct) * 10);` **memcpy** is used for memory copying. It can copy any data type and allows you to specify the number of bytes to copy. Example: `char a[100], b[50]; memcpy(b, a, sizeof(b));` Note: Using `sizeof(a)` h --- ## The Purpose of STDIN_FILENO and its Difference from stdin - URL: https://intl.sienovo.cn/blog/6781999 - Date: 2011-09-16 - Tags: #File, #API, #Mobile, #Buffer, #Terminal, #Network 1. Purpose of STDIN_FILENO STDIN_FILENO belongs to the system API library, declared as an `int` type. It is an open file descriptor, and its corresponding functions primarily include system calls like `open`, `read`, `write`, `close`. File APIs provided at the operating system level all represent files using file descriptors. STDIN_FILENO is the file descriptor for the standard input device (usually the keyboard). 2. Differences 1) Inconsistent Data Types: `stdin` is of type `FILE*` `STDIN_FILENO` is of type `int` Functions that use `stdin` primarily include `fread`, `fwrite`, `fclose`, etc., most of which start with 'f'. Functions that use `STDIN_FILENO` include `read`, `write`, `close`, etc. 2) `stdin` and similar are `FILE*` types, belonging to standard I/O, which are high-level input/output functions. They are defined in ``. `STDIN_FILENO` and similar are file descriptors, which are non-negative integers, typically defined as 0, 1, 2. They belong to unbuffered I/O, d --- ## Detailed Explanation of msgsnd/msgrcv Functions - URL: https://intl.sienovo.cn/blog/6781342 - Date: 2011-09-16 - Tags: #Struct, #Signal, #Null, #Buffer, #Less \================================ msgrcv() Function \============================ The `msgrcv()` function is used to receive messages from a message queue. Its definition in `linux/msg.h` is as follows: System call: msgrcv() Function prototype: int msgrcv(int msqid, struct msgbuf \*msgp, int msgsz, long mtype, int msgflg) Return value: Number of bytes copied into the message buffer -1 on error: errno = E2BIG (Message length is greater than msgsz, no MSG\_NOERROR) EACCES (No read permission) EFAULT (Address pointed to by msgp is invalid) EIDRM (Queue was removed during retrieval) EINTR (Interrupted by arriving signal) EINVAL (Invalid msgqid, or msgsz less than 0) ENOMSG (IPC\_NOWAIT asserted, and no message exists in the queue to satisfy the request) The first three parameters have the same meaning as their counterparts in the `msgsnd()` function. The fourth parameter, `mtype`, specifies the type of message to retrieve from the queue. The function searche --- ## Socket Functions: read, write, send, and recv - A Summary - URL: https://intl.sienovo.cn/blog/6781266 - Date: 2011-09-16 - Tags: #Socket, #Struct, #Buffer, #Network, #Sockets, #Windows 1. `send` and `recv` are functions for socket-oriented file descriptors. `read` and `write` require file descriptors. `read` and `write` can also operate on socket FDs because Linux treats sockets as a special type of file descriptor. The two are consistent on BSD 4.4, ultimately calling the same kernel handling function, except that `recv` and `send` have additional options (flags). What is the difference between read() and recv()? From Andrew Gierth (andrew@erlenstar.demon.co.uk): read() is equivalent to recv() with a flags parameter of 0. Other values for the flags parameter change the behaviour of recv(). Similarly, write() is equivalent to send() with flags == 0. It is unlikely that send()/recv() would be dropped; perhaps someone with a copy of the POSIX drafts for socket calls can check... Portability note: non-unix systems may not allow read()/write() on sockets, but recv()/send() are usually ok. This is true on Windows and OS/2, for example. ============================= --- ## TCP/IP Socket File Transfer under Linux - URL: https://intl.sienovo.cn/blog/6778704 - Date: 2011-09-15 - Tags: #socket, #linux, #buffer, #server, #stream, #server //////////////////////////////////// // Server code /////////////////////////////////// // This file contains the server code #include // for sockaddr_in #include // for socket #include // for socket #include // for printf #include // for exit #include // for bzero #include // for time_t and time #define HELLO_WORLD_SERVER_PORT 7754 #define LENGTH_OF_LISTEN_QUEUE 20 #define BUFFER_SIZE 1024 int main(int argc, char **argv) { // Set up a socket address structure server_addr, representing the server's internet address and port struct sockaddr_in server_addr; bzero(&server_addr, sizeof(server_addr)); // Set memory block contents to zero server_addr.sin_family = AF_INET; server_addr.sin_addr.s_addr = htons(INADDR_ANY); server_addr.sin_port = htons(HELLO_WORLD_SERVER_PORT); // time_t --- ## Methods to Get System Time in Linux - URL: https://intl.sienovo.cn/blog/6774784 - Date: 2011-09-14 - Tags: #Linux, #Struct, #Language, #C The `localtime` function can be used to obtain the year, month, day, hour, minute, and second values separately. 　　C language implementation methods for obtaining system time in Linux: 　　1. The `localtime` function can be used to obtain the year, month, day, hour, minute, and second values separately. 　　```c 　　#include //C language header file 　　#include //C language I/O 　　void main () 　　{ 　　time_t now; // Instantiate time_t structure 　　struct tm *timenow; // Instantiate tm structure pointer 　　time(&now); 　　// The time function reads the current time (International Standard Time, not Beijing time) and passes the value to now 　　timenow = localtime(&now); 　　// The localtime function converts the time 'now' obtained from time() into the time on your computer (i.e., your configured region) 　　printf(" Local time is %s ",asctime(timenow)); 　　// In the above line, the asctime function converts the time to a string and outputs it via printf() 　　} 　　``` 　　Note: `time_t` --- ## Understanding the Linux sleep Function - URL: https://intl.sienovo.cn/blog/6774530 - Date: 2011-09-14 - Tags: #Linux, #Float ## Understanding the Linux sleep Function In this article, we will explore the `sleep` function in Linux, which is crucial for managing process execution states. You will learn how `sleep` affects process scheduling, the underlying mechanics of timer queues, and a practical code example demonstrating its usage. ### What Does the `sleep` Function Do? The `sleep` function changes a process's execution state to "sleeping." When a process calls `sleep`, it is removed from the system's runnable queue. This means that the scheduler will not select this process for execution, nor will it allocate CPU time slices to it during the specified sleep duration. When a process is put to sleep, it is also added to a timer queue managed by the Linux kernel. The kernel maintains this timer queue to track processes that are waiting to be awakened after their sleep duration has expired. ### The Timer Queue Mechanism The kernel handles a timer queue to manage the timing of sleeping processes. During --- ## Update English Resume: Google, Microsoft - URL: https://intl.sienovo.cn/blog/6773629 - Date: 2011-09-14 - Tags: #Linux, #DataStructures, #Programming, #Makefile, #MobileOS, #Qt Update English Resume Improve the Linux development environment on Windows 7. This includes installing tools like SMB, Source Insight, and Qt 4. Find methods and organizations for publishing papers (Chinese core journals, academic journals, English core academic journals). Publish papers and patents like Wu Bo, aligning with his resume, capabilities, and qualifications. Project goal for late 2011: A mobile operating system and applications. For example, "Design and Implementation of a Smartphone Based on Linux and Qtopia". Of course, this needs to be combined with the actual situation of the R&D center to accelerate progress. I'll have things to do when I get back. I can use Qt to develop QQ chat software. Smartphones, wow, that's interesting! I might even be able to join Tencent's 3G department then. Project Objectives: 1. An excellent project, this is a major goal. My resume no longer lacks this. Project experience! Project representation! 2. Familiarity with kernel programm --- ## My Four Years at QQ Mail - URL: https://intl.sienovo.cn/blog/6770765 - Date: 2011-09-13 - Tags: #QQ, #Product, #Python, #CGI, #Storage, #ProgrammingLanguage It’s been over four years since I started working—time flies. I was fortunate to land a great opportunity right after graduation. Tencent’s Guangzhou R&D Center had just been established in July 2005, primarily focusing on Tencent’s email services. I joined the team in February 2006, and thus witnessed the entire evolution of QQ Mail. Some memories have faded over time, so details and timelines might not be entirely accurate, but I’ll do my best to recall. Writing this series is a way for me to look back and summarize the past four years. I’ll share it from a personal perspective, not aiming for broad insights, but rather in a straightforward storytelling manner. I’m someone with few stories, yet I love telling them. You might have heard the story behind Tencent’s email venture. The initial team was overly confident, believing that placing the email service inside the QQ client and leveraging QQ’s massive user base would naturally lead to success. But the opposite happened. Realizin --- ## Tencent - Guangzhou R&D - Referrals - URL: https://intl.sienovo.cn/blog/6770758 - Date: 2011-09-13 - Tags: #Tencent, #WebAppDev, #JavaScript, #Jobs, #Language, #ArchitectureDesign Hello everyone: Specific job requirements are as follows: System Operations Engineer Location: Guangzhou Responsibilities: 1. Responsible for daily operations, maintenance, and changes of email systems; 2. Manage and optimize systems to improve performance; 3. Manage system equipment. Requirements: 1. 1+ years of experience in LINUX/UNIX system administration; 2. Experience in C/C++ development and shell scripting; 3. Meticulous and highly responsible; 4. Experience in email system operations is a plus. Backend Development Engineer Location: Guangzhou Responsibilities: 1. Responsible for backend service development for email products; 2. Responsible for backend system architecture design, optimization, and implementation; 3. Responsible for analyzing and resolving backend system issues. Requirements: 1. 2+ years of development experience; 2. Familiar with LINUX/UNIX development environments; 3. Proficient in C/C++ development language, familiar with object-oriented development meth --- ## Autumn Is the Time to Sow Again - URL: https://intl.sienovo.cn/blog/6770499 - Date: 2011-09-13 - Tags: #Linux Autumn is a season of harvest, but it's also the perfect time to sow seeds for the second half of the year and for next year. Otherwise, how can you expect a good harvest later? Take Xiao Hu, for example. Last year, he worked hard and published eight papers, but none got accepted. This year, however, he's already had three EI papers accepted. Look at Dr. Wu—constantly sowing, consistently reaping. What about me? An architect. An outstanding code developer. A 6.5k goal. I really need an outstanding Linux project to show for it. My lover, my beloved --- ## My Perspective on Architects - URL: https://intl.sienovo.cn/blog/6770130 - Date: 2011-09-13 - Tags: #Finance, #Documentation, #Telecom, #Tasks, #Programming, #Testing **My Perspective on Architects** **2009-08-06** An architect is the soul of a project team. They determine the technical choices, overall architecture, and module division of the entire system, and may also serve as a communication bridge with leadership. In a sense, the architect largely dictates the success or failure of a project, much like the saying 'a fast train relies on its locomotive to lead the way.' Many excellent architects evolve from excellent developers, but not all excellent developers necessarily become qualified architects. Compared to architects, the tasks undertaken by developers are relatively narrower; their primary goals include writing high-quality code, conducting thorough testing, and producing high-quality documentation. Architects, on the other hand, face a much broader scope. Beyond solid technical skills, they also need strong communication abilities and the capacity to manage the entire system from a macroscopic perspective. Someone once said that pr --- ## Attempting to Translate a Linus Torvalds Post - URL: https://intl.sienovo.cn/blog/6767351 - Date: 2011-09-11 - Tags: #Session, #Timer, #Report, #Reference, #Descriptor, #Allocation From Linus Torvalds <> Date Sun, 4 Sep 2011 16:27:25 -0700 Subject Linux 3.1-rc5 So it's been another week, and it's time for another -rc. However, master.kernel.org is still down, and there really hasn't been a ton of development going on, so I considered just skipping a week. But hey, the whole point (well, \*one\* of the points) of distributed development is that no single place is really any different from any other, so since I did a github account for my divelog thing, why not see how well it holds up to me just putting my whole kernel repo there too? So while kernel.org is down for the count, let's just see how github does: [https://github.com/torvalds/linux.git](https://github.com/torvalds/linux.git) NOTE! One thing to look out for when you see a new random public hosting place usage like that is to verify that yes, it's really the person you think it is. So is it? You can take a few different approaches: (a) Heck, it's open source, I don't care --- ## How to Add Friendly Links to the New CSDN - URL: https://intl.sienovo.cn/blog/6767130 - Date: 2011-09-11 - Tags: #HTML, #SearchEngine, #IBM, #Baidu After much searching, the method for adding friendly links to the new CSDN is finally out! It took a lot of effort to find this; it seems good things are often too deeply hidden in this world, while outdated methods still rank highest in search engines due to high click-through rates! New Version Original Article: [http://blog.csdn.net/zpf644792799/article/details/6705865](http://blog.csdn.net/zpf644792799/article/details/6705865) Old Version Original Article: [http://blog.csdn.net/java2000\_net/article/details/3851431](http://blog.csdn.net/java2000_net/article/details/3851431) Click 'Manage Blog' in the top right corner of your blog homepage, as shown: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/6767130/01_0_1313899055Lcw8.gif) Enter the management page and click 'Manage Columns', as shown: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/6767130/02_0_13138991923djx.gif) Find 'Add Column' at the bottom. ![](https://pub-048dcb96257f476697b113fcb593 --- ## Implementation of Process Scheduling by Chen Lijun - URL: https://intl.sienovo.cn/blog/6766986 - Date: 2011-09-11 - Tags: #Struct, #List, #Signal, #Each, #Null, #C ****5.3.5** Implementation of Process Scheduling** The scheduler in the kernel is essentially a function. For clarity, we have simplified it here, omitting its SMP-related implementation. ```c asmlinkage void schedule(void) { struct task_struct *prev, *next, *p; /* prev represents the process before scheduling, next represents the process after scheduling */ struct list_head *tmp; int this_cpu, c; if (!current->active_mm) BUG(); /* Error if current process's active_mm is NULL */ need_resched_back: prev = current; /* Set prev to current process */ this_cpu = prev->processor; if (in_interrupt()) { /* If schedule() is called within an interrupt handler, it indicates an error */ printk("Scheduling in interrupt\n"); BUG(); } release_kernel_lock(prev, this_cpu); /* Release global kernel lock and enable interrupts on this_cpu */ spin_lock_irq(&runqueue_lo --- ## Memory Space Divisions: Code Segment, Data Segment, Stack, Heap (Collected and Compiled) - URL: https://intl.sienovo.cn/blog/6766567 - Date: 2011-09-10 - Tags: #exe, #Compiler, #Storage, #StorageSystem, #Language, #Buffer 1. Function code is stored in the code segment. If a declared class is never used, it will be optimized away during compilation, and its member functions will not occupy space in the code segment. Global variables or static variables are placed in the data segment. Local variables are placed on the stack. Objects created with `new` are placed on the heap. Memory is divided into 4 sections: stack area, heap area, code area, global variable area. BSS Segment: The BSS segment (Block Started by Symbol) typically refers to a memory region used to store uninitialized global variables in a program. BSS is an abbreviation for Block Started by Symbol. The BSS segment belongs to static memory allocation. 2. Code segment, data segment, and stack are CPU-level logical concepts, while the heap is a language-level logical concept. 3. There is also a constant area, where the content cannot be modified. For example, `char *p = "hello";` the "hello" literal is stored in the constant a --- ## The Clever Use of Function Pointer Arrays - URL: https://intl.sienovo.cn/blog/6764138 - Date: 2011-09-09 - Tags: #function, #buffer, #fun, #Work, #Task, #Language While developing a certain software, I encountered the following problem: an upstream module passes binary data to me, with input parameters `char* buffer` and `int length`. `buffer` is the starting address of the data, and `length` indicates the size of this batch of data. The data's characteristics are: variable length, variable type, with the first byte (`buffer[0]`) identifying the data type. There are 256 (2^8) possible types. My task is to process every possible data type, and my module contains several functions, each requiring similar processing. If following the usual approach, the code would look like this: ```c void MyFuntion( char* buffer, int length ) { 　　　　__int8 nStreamType = buffer[0]; 　　　　switch( nStreamType ) 　　　　{ 　　　　　　　case 0: 　　　　　　　　　　　function1(); 　　　　　　　　　　　break; 　　　　　　　case 1: 　　　　　　　...... 　　　　　　　case 255: 　　　　　　　　　　　function255(); 　　　　　　　　　　　break; 　　　　　} } ``` If I were to continue with this method, every one of my functions would have to perform so ma --- ## Reflections on Debugging POSIX Multithreaded Socket Network Communication - URL: https://intl.sienovo.cn/blog/6763803 - Date: 2011-09-09 - Tags: #Multithreading, #Socket, #Networking, #Testing, #Work, #Linux 1) Capture the most subtle thoughts arising in your mind—whether inspired by Haruki Murakami or LINUX—and clarify them. This is a crucial skill. 2) Be able to clearly describe problems using language and diagrams. 3) Be capable of writing self-testing programs, strengthening test objectives, optimizing test sequences, and outlining a clear testing blueprint—making them practical and effective. 4) Create architectural blueprints (understood as connections, relationships between internal and external modules), providing an overview from a bird's-eye perspective. Detailed implementation plans (easy to execute and test) should follow the principle of simplification. Decorative elements (such as user-friendly interfaces) can be entirely omitted during exploratory development. Break the system into multiple modules. Minimize coupling between modules to reduce complexity. 5) Proceeding with unclear concepts leads to exhausting, patchwork fixes. Abandon and avoid this approac --- ## memset Function Usage - URL: https://intl.sienovo.cn/blog/6763717 - Date: 2011-09-09 - Tags: #Programming ## Understanding the `memset` Function in C In this post, we will explore the `memset()` function, a standard library function in C used for initializing arrays and memory blocks. Understanding how `memset()` operates is crucial for effective memory management in C programming, especially when dealing with arrays and structures. We will look at its working principle, provide examples, and discuss its limitations. ### What is `memset()`? The `memset()` function is designed for byte-level operations. It takes three parameters: a pointer to the memory block, a value to set, and the number of bytes to set. The syntax is as follows: ```c void *memset(void *s, int c, size_t n); ``` - `s`: Pointer to the memory block to be filled. - `c`: Value to be set (converted to an unsigned char). - `n`: Number of bytes to be set to the value. ### How Does `memset()` Work? The core functionality of `memset()` involves assigning the specified value to each byte of the memory block starting from the --- ## Linux Time Slicing and Thread Scheduling Issues – Collection and Summary - URL: https://intl.sienovo.cn/blog/6763492 - Date: 2011-09-09 - Tags: #Linux, #Null, #Struct, #Delay, #Multithreading, #Timer 1. On Linux 2.6, how can you make a thread run once every 1ms? I've tried the following two methods myself, but the results were not satisfactory. According to prototype testing, most intervals are around 1ms, but there are always some intervals lasting several milliseconds, and occasionally even over 10ms. (1) Using `settimer` with an interval of 1000μs; (2) Creating a high-priority thread that includes "the work to be done" and a `usleep` call to achieve the 1ms interval between consecutive thread activations. Therefore, I'd like to ask experts: 1. How can you implement an accurate 1ms timer at the user level, or make a thread execute precisely every 1ms? 2. What is the overhead of thread switching in user space? How long is the time slice each thread gets upon being scheduled? 3. What thread scheduling policies are available? Can they be implemented using pthread? _______________________________________________________________________________________________________ --- ## Linux Process Switching and Return Values of Kernel Threads - URL: https://intl.sienovo.cn/blog/6763073 - Date: 2011-09-09 - Tags: #Linux, #Struct, #Thread, #Embedded, #Assembly, #Null The process in Linux is a fundamental concept. A process has two starting points when transitioning from the run queue to execution: one is label 1 in the `switch_to` macro: `"1:\t"`, and the other is `ret_from_fork`. Almost all processes that are not newly created start from label 1 mentioned above. The `switch_to` macro is a mandatory path for all processes except the kernel itself to go through in order to run. Thus, although the Linux process system and scheduling mechanism are highly complex, the overall structure resembles an hourglass, with the `switch_to` macro representing the narrowest point in the middle. To move from one end to the other, every process must pass through this point. For non-newly-created processes, execution always begins at label 1. Let's first examine how this works: ```c #define switch_to(prev,next,last) do { \ unsigned long esi,edi; \ asm volatile("pushfl\n\t" --- ## The Ten Fears of Programming: Blueprints and Construction Drawings - URL: https://intl.sienovo.cn/blog/6759915 - Date: 2011-09-08 - Tags: #Programming, #DataStructures, #C ## The Ten Fears of Programming: Blueprints and Construction Drawings As programmers, we often face numerous challenges that can make our work more difficult than it needs to be. In this article, we will explore ten common fears that programmers encounter, and provide guidance on how to overcome them. Specifically, we will delve into the importance of creating blueprints and construction drawings to simplify our programming tasks. ### I. Complexity Complexity is a major obstacle that programmers often face. When faced with a complex problem, it can be overwhelming to know where to start. However, by breaking down the problem into smaller, manageable tasks, we can reduce complexity and make it more manageable. ### II. Writing Code Yourself, Not Just Modifying and Adding (Awkward) Writing code from scratch can be intimidating, especially when we are not sure where to start. However, modifying and adding code to existing projects can also be awkward and lead to confusion. To overcome --- ## Mentor Feedback Section from Onboarding Training - URL: https://intl.sienovo.cn/blog/6759901 - Date: 2011-09-08 - Tags: #Linux, #Programming, #Networking, #C **Mentor Feedback Section** **1. Specific guidance and suggestions during the new employee's mentoring period** Since XXX joined the company a month ago, they have been diligent and quick to learn, completing the first month's training plan in under three weeks and generally meeting expectations. During this period, the following issues were observed: 1) Further strengthening of fundamental C programming skills under Linux is needed. Modifying existing programs is only meant to help you quickly understand development procedures and methods. However, in actual future development, there will rarely be ready-made code to reference. Therefore, it's essential to thoroughly understand basic concepts, program architecture, and workflow. Whenever possible, type out each line of code manually based on your own understanding, rather than simply modifying, replacing, and running existing code. 2) It's good to ask questions—having questions means you're making progress. However, for some ques --- ## Linux Inter-thread Communication - URL: https://intl.sienovo.cn/blog/6759382 - Date: 2011-09-08 - Tags: #Linux, #Multithreading, #Thread, #Join, #Signal, #Programming Threads do not require special means for communication because they can share data structures; that is, a global variable can be used by two threads simultaneously. However, it's important to ensure synchronization between threads, typically using mutexes. You can refer to newer UNIX/Linux programming books, which often cover Posix thread programming, such as "Advanced Programming in the UNIX Environment (Second Edition)," "UNIX System Programming," etc. Linux messages belong to IPC (Inter-Process Communication), which is not used by threads. Linux uses `pthread_kill` to send signals to threads. By the way, in Windows, isn't thread communication done using `post...` (are you referring to `PostMessage`?)? Windows uses `PostThreadMessage` for inter-thread communication, but this method is rarely used in practice. Synchronization is more commonly employed. The principles of synchronization in Linux and Windows are the same. However, Linux signals are also very useful. Properly using s --- ## Passing Parameters to pthread_create - URL: https://intl.sienovo.cn/blog/6757525 - Date: 2011-09-07 - Tags: #thread, #struct, #casting, #null, #function, #integer #include #include using namespace std; pthread_t thread; void *fn(void *arg) { int i = *(int *)arg; cout << "i = " << i << endl; return ((void *)0); } int main() { int err1; int i = 10; err1 = pthread_create(&thread, NULL, &fn, &i); pthread_join(thread, NULL); } ———————————————————————————————— Thread creation function: int pthread_create(pthread_t *tid, const pthread_attr_t *attr, void *(*func)(void *), void *arg); The parameter `func` represents a function that takes one void * argument and returns a void *; For the `void *arg` parameter, under gcc 3.2.2, both of the following methods can be compiled successfully. int ssock; int TCPechod(int fd); 1. pthread_create(&th, &ta, (void *(*)(void *))TCPechod, (void *)ssock); 2. pthread_create(&th, &ta, (void *(*)(void *))&TCPechod, (void *)&ssock); **Original post from ChinaUnix blog, please click here to view the or --- ## break: Breaking Out of the Nearest Loop - URL: https://intl.sienovo.cn/blog/6757373 - Date: 2011-09-07 - Tags: none break: Breaks out of the nearest loop (e.g., for, while). If you want to break out of N nested loops, the notorious `goto` statement can be very useful, saving you from using `break` multiple times! --- ## 45 Habits of Highly Effective Programmers: The Path to Becoming a Project Leader - URL: https://intl.sienovo.cn/blog/6756435 - Date: 2011-09-07 - Tags: #ProjectLeadership **The Path to Becoming a Project Leader** Guide and grow Problem-solving expert, excelling in architecture and design --- ## Building a Program from Scratch: Reinventing the Wheel is Excellent Training - URL: https://intl.sienovo.cn/blog/6756033 - Date: 2011-09-07 - Tags: none ## Building a Program from Scratch: Reinventing the Wheel is Excellent Training In the world of software development, there is often a debate about whether to build applications from scratch or to modify existing code. This article emphasizes the importance of developing the ability to create programs independently, regardless of how rudimentary the initial attempts may be. Readers will learn about the benefits of building their own projects and the unique satisfaction that comes from this process. ### Shift Your Mindset The first step toward becoming a proficient developer is to shift your mindset. It's essential to recognize that the ability to build things yourself is crucial. This does not mean that every project needs to be a grand, polished application; even the simplest of creations can provide valuable learning experiences. Each attempt at building something new is a step toward reaching your full potential as a developer. ### The Value of Original Creation When you create --- ## Relationship Between Main Thread and Worker Thread - URL: https://intl.sienovo.cn/blog/6752370 - Date: 2011-09-06 - Tags: #Work ## Relationship Between Main Thread and Worker Thread In multi-threaded programming, understanding the relationship between the main thread and worker threads is crucial for ensuring proper application behavior and resource management. This article outlines the essential interactions between the main thread and worker threads, focusing on how termination signals are communicated and handled. By the end of this post, you will have a clearer understanding of how to manage thread lifecycles effectively. ### 1. Sending Termination Messages Before the main thread concludes its execution, it is important to send a termination message to any active worker threads. This is typically done to ensure that the worker threads can complete their tasks gracefully and release any resources they may be holding. The termination message serves as a notification for the worker thread to prepare for exit, which helps avoid abrupt termination and potential resource leaks. ### 2. Waiting for Worker Threa --- ## Linux Socket Network Programming (Theoretical Analysis + Comprehensive Examples) - URL: https://intl.sienovo.cn/blog/6752089 - Date: 2011-09-06 - Tags: #Socket, #Networking, #Programming, #Linux, #Struct, #Server What is a Socket? The Socket interface is the API for TCP/IP networks. It defines numerous functions or routines that developers can use to build applications over TCP/IP networks. To master Internet-based TCP/IP network programming, one must understand the Socket interface. Socket interfaces were originally designed for Unix operating systems. If you are familiar with Unix I/O operations, understanding Sockets becomes much easier. Network socket data transmission is a special form of I/O, and a socket is essentially a file descriptor. Similar to opening a file, there is a function call `socket()` that returns an integer socket descriptor. Subsequent operations such as connection establishment and data transfer are performed using this descriptor. There are two commonly used socket types: stream sockets (`SOCK_STREAM`) and datagram sockets (`SOCK_DGRAM`). Stream sockets are connection-oriented and used with TCP services; datagram sockets are connectionless and correspond to UDP se --- ## "Thoroughly Master C Pointers" Part 3 -- Pointers and Array Names - URL: https://intl.sienovo.cn/blog/6748656 - Date: 2011-09-05 - Tags: #C **1. Accessing Array Elements via Array Name** Consider the following code: ```c int i,a[]={3,4,5,6,7,3,7,4,4,6}; for (i=0;i<=9;i++) { printf ( “%d”, a[i] ); } ``` Clearly, this displays the values of each element in array `a`. We can also access elements like this: ```c int i,a[]={3,4,5,6,7,3,7,4,4,6}; for (i=0;i<=9;i++) { printf ( “%d”, *(a+i) ); } ``` Its result and effect are exactly the same. **2. Accessing Array Elements via Pointers** ```c int i,*pa,a[]={3,4,5,6,7,3,7,4,4,6}; pa =a ;// Note that array name 'a' is directly assigned to pointer 'pa' for (i=0;i<=9;i++) { printf ( “%d”, pa[i] ); } ``` Clearly, this also displays the values of each element in array `a`. Additionally, similar to using the array name, it can also be done as follows: ```c int i,*pa,a[]={3,4,5,6,7,3,7,4,4,6}; pa =a; for (i=0;i<=9;i++) { printf ( “%d”, *(pa+i) ); } ``` Looking at `pa=a` (assigning the array name to a pointer) and the forms of accessing elements via array name and pointer --- ## The Role of Subnet Masks - URL: https://intl.sienovo.cn/blog/6746773 - Date: 2011-09-04 - Tags: #Networking, #Communication A subnet mask uses the same addressing format as an IP address. The portions of the subnet mask set to 1 correspond to the network and subnet parts of the IP address, while the portions set to 0 correspond to the host part of the IP address. When a subnet mask and an IP address are combined using a bitwise AND operation, the host portion of the IP address is discarded, leaving only the network and subnet addresses. For example, if the destination IP address of an IP packet is 10.2.2.1 and the subnet mask is 255.255.255.0, performing the AND operation yields 10.2.2.0. Network devices then interpret 10.2.2.0 as the network and subnet identifier for that IP address. The subnet mask is the basis for determining whether the IP addresses of any two computers belong to the same subnetwork. The simplest way to understand this is: if two computers perform a bitwise AND operation between their respective IP addresses and subnet mask, and the results are identical, the two computers are on the --- ## Differences between Heap and Stack (A Frequently Reposted Article) - URL: https://intl.sienovo.cn/blog/6746640 - Date: 2011-09-04 - Tags: #DataStructures, #Compiler, #Windows, #Byte, #Storage, #Extension I. Preliminary Knowledge - Program Memory Allocation A program compiled in C/C++ occupies memory divided into the following parts: 1. Stack Area (stack) — Automatically allocated and deallocated by the compiler, used to store function parameters, local variable values, etc. Its operation is similar to a stack in data structures. 2. Heap Area (heap) — Generally allocated and deallocated by the programmer. If the programmer does not deallocate it, it might be reclaimed by the OS when the program ends. Note that it is different from a heap in data structures; its allocation method is more similar to a linked list, haha. 3. Global/Static Area (static) — Global variables and static variables are stored together. Initialized global and static variables are in one area, while uninitialized global and static variables are in an adjacent area. - Released by the system after the program ends. 4. Literal Constant Area — Constant strings are stored here. Released by the system after the program e --- ## Understanding the Protocol Base Struct p_base - URL: https://intl.sienovo.cn/blog/6743720 - Date: 2011-09-02 - Tags: #Struct, #Linux, #Class, #Programming This struct serves as a base class for protocol management, encapsulating two key attributes: - `p_name`: An integer representing the protocol code. - `p_len`: An integer representing the length of the protocol. ### Constructor Explanation The constructor of the `p_base` struct initializes the attributes `p_name` and `p_len` using an initializer list. This is a concise and efficient way to set up member variables when an instance of the struct is created. ### Equivalent Class Representation The `p_base` struct can also be expressed as a class. The equivalent class representation is as follows: --- ## fflush(stdin) and fflush(stdout) - URL: https://intl.sienovo.cn/blog/6743416 - Date: 2011-09-02 - Tags: #Input, #Multithreading, #Platform, #Windows, #Programming, #Networking `fflush(stdin)` is relatively easy to understand: it clears the standard input stream, discarding any excess data that has not yet been processed. For example, consider this small program: ```c++ void main() { int a; char str[10]; cin>>a; cout<>str; cout<>a`, there's still an integer left in the `stdin` buffer that hasn't been read. Subsequently, without waiting for string input, this extra number might be directly stored into `str` and printed. To some extent, this is caused by non-standard operation, but a program should be robust, and programmers should anticipate such non-standard operations. One could prompt the user with "Please enter 1 integer" o --- ## Linux Socket Network Programming: Chat Room (Part 3) – Asynchronous Communication Using select - URL: https://intl.sienovo.cn/blog/6742109 - Date: 2011-09-02 - Tags: #Socket, #Chat, #Linux, #Communication, #Programming, #Networking 1. Server Side ```cpp /*select_server.c 2011.9.2 by yyg*/#include #include #include #include #include #include #include #include #include #include #include #include #include #define MAXBUF 1024 int main(int argc,char **argv){ int sockfd,new_fd; socklen_t len; struct sockaddr_in my_addr,their_addr; unsigned int myport,lisnum; char buf[MAXBUF+1]; fd_set rfds; struct timeval tv; int retval,maxfd = -1; if(argv[1]){ myport = atoi(argv[1]); } else myport = 7838; if(argv[2]){ lisnum = atoi(argv[2]); } else lisnum =2; if((sockfd = socket(PF_INET,SOCK_STREAM,0))== -1){ perror("socket"); exit(1); } bzero(&my_addr,sizeof(my_addr)); my_addr.sin_family = PF_INET; my_addr.sin_port = htons(myport); if(argv[3]) my_addr.sin_addr.s_addr = INADDR_ANY; if(bind(sockfd,(struct sockaddr *)&my_addr,sizeof(struct sockaddr)) == -1){ perror("bind"); --- ## Linux Chat Room: 50 Questions - URL: https://intl.sienovo.cn/blog/6739193 - Date: 2011-09-01 - Tags: #Chat, #Linux, #Socket, #Server, #Sockets, #Thread ====================================        Linux Chat Room: 50 Questions \==================================== 1. Question: How to implement multiple terminals? And listening? 2. What steps does a chat room application typically break down into? 3. Open a Socket, bind it to another port, and continuously listen on this port. 4. Does a server need many Sockets, or one Socket with many ports? Answer: It has many sockets, managed by an array. 5. Server (Socket Array): Basically multi-threaded: one thread listens, and after `Accept`, creates a thread to handle the request. ———————————————————————————————————— Ideas: 1: The server has a Listener thread for listening. 2: The server also has a server socket thread for connecting with clients. 3: When a client connection is detected, a server socket thread is created to connect with that client independently. 4: The server needs a structure to store client information. You can write a class to encapsulate this, such as user IP, etc. —— --- ## Linux Socket Implementation of a Network Chat Room (Part 2): Independent Message Sending and Receiving Using Threads - URL: https://intl.sienovo.cn/blog/6738206 - Date: 2011-09-01 - Tags: #Socket, #Linux, #Chat, #Networking, #Struct, #Null ## 1. Introduction ## 2. Code Implementation ### 1. Server Side ```cpp /*tcpserver.c 2011.9.1 by yyg*/ #include #include #include #include #include #include #include #include #include #define MYPORT 3490 // Define port #define BACKLOG 10 #define MAXDATASIZE 1024 int sockfd, new_fd; pthread_t accthread, recthread; void recmessage(void) { // Function to receive client messages while(1) { int numbytes; char buf[MAXDATASIZE]; if ((numbytes = recv(new_fd, buf, MAXDATASIZE, 0)) == -1) { perror("recv"); exit(1); } buf[numbytes] = '\0'; if (strcmp(buf, "exit") == 0) { // If received message is "exit", terminate communication printf("Client is closed\n"); close(new_fd); close(sockfd); exit(1); } printf("client:%s\n", buf); } /*whil --- ## Inter-Process Communication Series (Part One): Pipe Read/Write Example - URL: https://intl.sienovo.cn/blog/6736411 - Date: 2011-08-31 - Tags: #numbers, #server, #Terminal, #null **I. Pipe Read/Write Considerations** 1. Writing to a pipe is only meaningful when a read end of the pipe exists; otherwise, an error signal SIFPIPE will be received from the kernel. 2. Atomicity of writes is not guaranteed when writing data to a pipe; as soon as there is free space in the pipe buffer, the writing process attempts to write content to it. If the reading process does not read the content from the pipe, the writing process will remain blocked. 3. When parent and child processes run, their execution order is not guaranteed. Therefore, to ensure the parent process closes the read descriptor, `sleep(2)` can be added to the child process. **II. Examples** **1. Unnamed Pipe** ```cpp /*pipe_rw.c*/#include #include #include #include #include int main(){ int pipe_fd[2]; pid_t pid; char buf_r[100]; char* p_wbuf; int r_num; memset(buf_r,0,sizeof(buf_r)); if(pipe(pipe_fd)<0) { printf("pipe create error\n"); return -1; } if(( --- ## Multithreading Programming Series (5): "Producer-Consumer" Experiment — Implementation Using PV Primitives - URL: https://intl.sienovo.cn/blog/6735983 - Date: 2011-08-31 - Tags: #Multithreading, #Programming, #Null, #Thread, #Join, #Product **I. Problem Description** There is a bounded buffer and two threads: producer and consumer. The producer writes products into the buffer, while the consumer removes them. When the buffer is full, the producer must wait before writing; when the buffer is empty, the consumer cannot read and must wait. **II. Example** ```cpp /*product.c*/#include #include #include #include #include #include #include #include #define FIFO "myfifo"#define N 5int lock_var;time_t end_time;char buf_r[100];sem_t mutex,full,avail;int fd;void productor(void *arg);void consumer(void *arg); int main(int argc,char *argv[]){ pthread_t id1,id2; pthread_t mon_th_id; int ret; end_time = time(NULL)+30; /*create namepipe*/ if((mkfifo(FIFO,O_CREAT|O_EXCL)<0) && (errno != EEXIST)) printf("cannot create fifoserver\n"); printf("preparing for reading bytes..."); memset(b --- ## Multithreaded Programming (Part 1): Thread Creation and Termination - URL: https://intl.sienovo.cn/blog/6735232 - Date: 2011-08-31 - Tags: #Multithreading, #Programming, #thread, #null, #join Here, `id1` and `id2` are `pthread_t` variables that will hold the IDs of our two new threads. `NULL` is passed for the attributes, meaning default thread attributes will be used. `thread1` and `thread2` are the respective functions that each thread will execute, and `NULL` is passed as the argument to these functions. ## Thread Execution and Concurrency Once threads are created, the operating system's scheduler manages their execution. Threads run concurrently, meaning their execution can interleave in various ways, depending on the scheduler's algorithm, system load, and thread priorities. It's important to remember that "concurrently" doesn't necessarily mean "in parallel" on a single-core system, but rather that their execution progresses independently. On multi-core systems, threads can indeed run in parallel on different CPU cores. Our example features two thread functions: `thread1` and `thread2`. `thread1` is designed to print a message six times, but with a twist: it explic --- ## Configuring Vim Auto-Indentation, 4-Space Tabs, and Line Numbers - URL: https://intl.sienovo.cn/blog/6734805 - Date: 2011-08-31 - Tags: #Vim, #CentOS Vim, a powerful and highly configurable text editor, is an indispensable tool for developers, system administrators, and anyone working extensively with text files on Linux and Unix-like systems. While its default configuration is functional, customizing Vim to suit your preferences can significantly enhance productivity. This guide will walk you through configuring essential Vim settings: enabling line numbers, setting tab stops to four spaces, and activating auto-indentation. We'll also address a specific troubleshooting scenario encountered on older systems like CentOS 5.3, where the root user's `vi` command might not behave as expected, and provide a robust solution. ## Understanding Vim Configuration Files Vim's behavior is controlled by configuration files, commonly known as `vimrc` files. There are typically two main types: 1. **System-wide `vimrc`:** Located at `/etc/vimrc` (or sometimes `/etc/vim/vimrc` or similar, depending on the distribution). Settings in this file appl --- ## Mutex Thread Control - URL: https://intl.sienovo.cn/blog/6734635 - Date: 2011-08-31 - Tags: #Null, #Join, #Test **I. Introduction** A mutex is a simple locking mechanism used to control access to shared resources. A mutex has only two states: locked and unlocked. A mutex can be thought of as a global variable in some sense. At any given time, only one thread can acquire a specific mutex. The thread that holds the lock can operate on the shared resource. If another thread attempts to lock an already locked mutex, that thread will be suspended until the thread holding the lock releases it. In essence, this lock ensures that shared resources are accessed in an orderly fashion by different threads. Key mutex operations: 1) Initialization: pthread\_mutex\_init 2) Locking: pthread\_mutex\_lock 3) Unlocking: pthread\_mutex\_unlock 4) Attempting to Lock: pthread\_mutex\_trylock 5) Destroying: pthread\_mutex\_destroy ========= Q&A ========= 1. Can there be multiple mutexes? How do they exist? What is their scope? A: **II. Example** ```cpp /*mutex.c*/#include #include #include --- ## Deep Dive into UNIX Programming: Two Implementations of a Simple Chat Room (fcntl and select) - URL: https://intl.sienovo.cn/blog/6732882 - Date: 2011-08-30 - Tags: #Chat, #Unix, #Programming, #Server, #Socket, #Null In today's highly connected world, online chatting has become a daily routine for many internet users. A chat room program is arguably the simplest form of multipoint communication over the internet. There are various ways to implement a chat room, but all rely on what is known as a "multi-user space" for message exchange, featuring a typical multiplexed I/O architecture. From a programmer’s perspective, a simple chat room is essentially about enabling many-to-many communication across multiple I/O endpoints. Its structure is illustrated in Figure 1. To users, this means that whenever one person types a message in the chat room, all others receive it. This "multi-user space" architecture is widely used in other multipoint communication applications, with the core being multiplexed I/O—also known as I/O multiplexing. I/O multiplexing is generally used in the following scenarios:     When a client needs to simultaneously handle interactive input and network communication with a server; --- ## Linux Socket Network Programming: fcntl and select (Handling Multiple Client Connections to a Server) - URL: https://intl.sienovo.cn/blog/6732223 - Date: 2011-08-30 - Tags: #Socket, #Server, #Linux, #Programming, #Network, #Struct **I. Introduction** In practical scenarios, people often encounter situations where **_multiple clients connect to a server_**. Since previously introduced functions like `connect`, `recv`, and `send` are blocking functions, if resources are not fully prepared, the process calling these functions will enter a sleep state, making it impossible to handle I/O multiplexing. This article presents **_two methods for I/O multiplexing: `fcntl()` and `select()`_**. As can be seen, treating sockets as special file descriptors in Linux greatly simplifies user handling. **II. fcntl** The `fcntl()` function has the following characteristics: 1) Non-blocking I/O: `cmd` can be set to `F_SETFL`, and `lock` can be set to `O_NONBLOCK`. 2) Signal-driven I/O: `cmd` can be set to `F_SETFL`, and `lock` can be set to `O_ASYNC`. Example: ```cpp #include #include #include #include #include #include #include #include #include #include #include #include pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER; int lock_var = 0; time_t end_time; void pthread1(void *arg); void pthread2(void *arg); int main(int argc, char *argv[]) { pthread_t id1,id2; pthread_t mon_th_id; int ret; end_time = time(NULL)+10; pthread_mutex_init(&mutex,NULL); ret=pthread_create(&id1,NULL,(void *)pthread1, NULL); if(ret!=0) perror("pthread cread1"); ret=pthread_create(&id2,NULL,(void *)pthread2, NULL); if(ret!=0) perror("pthread cread2"); pthread_join(id1,NULL); pthread_join(id2,NULL); exit(0); } void pthread1(void *arg) { int i; while(time(NULL) < end_time) { if(pthread_mutex_lock(&mutex)!=0) { perror("pthread_mutex_lock"); } else printf("pthread1:pthread1 lock the variable\n"); for(i=0;i<2;i++) { sleep(1); lock_var++; } if(pthread_mutex_unlock(&mutex)!=0) { perror("pthread_mu --- ## Linux Socket Implementation of a Network Chat Room (Part 1): Server and Client Communication - URL: https://intl.sienovo.cn/blog/6731962 - Date: 2011-08-30 - Tags: #Socket, #Server, #Linux, #Chat, #Network, #Struct ```cpp 1.服务器端#include #include #include #include #include #include #include #include #define SERVPORT 3333#define BACKLOG 10#define MAX_CONNECTED_NO 10#define MAXDATASIZE 5 int main(){ struct sockaddr_in server_sockaddr,client_sockaddr; int sin_size,recvbytes; int sockfd,client_fd; char buf[MAXDATASIZE];/* Create socket */ if((sockfd = socket(AF_INET,SOCK_STREAM,0))==-1){ perror("socket"); exit(1); } printf("socket success!,sockfd=%d\n",sockfd);/* Set up server sockaddr_in structure */ server_sockaddr.sin_family=AF_INET; server_sockaddr.sin_port=htons(SERVPORT); server_sockaddr.sin_addr.s_addr=INADDR_ANY; bzero(&(server_sockaddr.sin_zero),8);/* Bind socket and port */ if(bind(sockfd,(struct sockaddr *)&server_sockaddr,sizeof(struct sockaddr))==-1){ perror("bind"); exit(1); } printf("bind success!\n");/* Listen for client requests */ if(listen(sockfd,BACKLOG)==-1){ perror("listen"); exit(1); --- ## Summary of Socket Programming APIs - URL: https://intl.sienovo.cn/blog/6728681 - Date: 2011-08-29 - Tags: #Socket, #Programming, #Server, #Struct, #Stream, #API One, Code Comments 1. ```cpp #include #include #include #include #include #include #include #include #define SERVPORT 3333 #define BACKLOG 10 #define MAX_CONNECTED_NO 10 #define MAXDATASIZE 5 int main(){ struct sockaddr_in server_sockaddr,client_sockaddr; int sin_size,recvbytes; int sockfd,client_fd; char buf[MAXDATASIZE]; if((sockfd = socket(AF_INET,SOCK_STREAM,0))==-1){ perror("socket"); exit(1); } printf("socket success!,sockfd=%d\n",sockfd); server_sockaddr.sin_family=AF_INET; server_sockaddr.sin_port=htons(SERVPORT); server_sockaddr.sin_addr.s_addr=INADDR_ANY; bzero(&(server_sockaddr.sin_zero),8); if(bind(sockfd,(struct sockaddr *)&server_sockaddr,sizeof(struct sockaddr))==-1){ perror("bind"); exit(1); } p --- ## Installing QT - URL: https://intl.sienovo.cn/blog/6728437 - Date: 2011-08-29 - Tags: #QT, #Assignment, #Chat, #Java I. Goals 1. I'm becoming increasingly curious about QT. After all, its dazzling interface is captivating, much like a beautiful girl. 2. Ask Hanbin how to install it, and if there are any specific resources. 3. Ask Xuedong how to install it on the MINI2440. 4. Create a chat application using QT, or alternatively, using Java. I'll start by finding some code online to use as a personal project. 5. Invite Xuedong and Zhaoling to participate, with Hanbin providing guidance. II. How to Install QT --- ## I Have a Dream — Writing a Linux-Themed Book - URL: https://intl.sienovo.cn/blog/6728178 - Date: 2011-08-29 - Tags: #Linux ========================= **Freelance Writer** ========================= I have a dream — writing a Linux-themed book. I have a dream — writing a column that everyone enjoys reading, just like fudan_abc or Chen Lijun. I have a dream — writing a Linux book, then teaching at universities such as South China University of Technology or South China Agricultural University, studying and growing together with fellow students, exchanging ideas — it would be an extraordinary honor and joy. I have a dream — writing books and meeting like-minded people, striving forward together. I have a dream — writing books to revitalize China's Linux industry. I have a dream — writing books to achieve financial freedom (with passive, continuous growth). I have a dream — writing books to realize my life's value. I have a dream... ================================================ How can I write an article of real value—clear, insightful, and inspirational? ========================== --- ## Running Java Programs on Linux - JRE Installation and Configuration - URL: https://intl.sienovo.cn/blog/6728004 - Date: 2011-08-29 - Tags: #Java, #Linux, #Plugins, #Browser, #Firefox, #JDK To run Java programs, you must install the Java Runtime Environment (JRE), which provides the necessary execution environment. You can obtain it by installing either JRE or JDK. If you are only using Java applications and not developing them, downloading just the JRE package is sufficient. To run Java programs, you must [install](http://soft.zdnet.com.cn/files/list-0-0-105247-1-1.htm "安装") the Java Runtime Environment (JRE), which provides the necessary execution environment. You can obtain it by [installing](http://soft.zdnet.com.cn/files/list-0-0-105247-1-1.htm "安装") either JRE or JDK. If you are only using Java applications and not developing them, downloading just the JRE package is sufficient; the JDK package also includes the JRE. This article will use JRE [installation](http://soft.zdnet.com.cn/files/list-0-0-105247-1-1.htm "安装") as an example. The JRE also includes the Java plugin required by web browsers. I. Download JRE; http://ftp.isu.edu.tw Download the appropriate vers --- ## Linux Chat Room Program - URL: https://intl.sienovo.cn/blog/6727973 - Date: 2011-08-29 - Tags: #Linux, #Multithreading, #Server, #Programming, #Java, #Chat \======================================= Objective ======================================= Advanced Programming in Linux Environment (Part 1) Implement a multi-user chat room program using TCP protocol with threading. (2 weeks) The following features must be implemented: 1. A server-side program capable of handling multiple client programs. 2. Support for one-to-one and one-to-many chat. 3. File transfer functionality. 4. File integrity verification. 5. Demonstrate solutions for resolving shared resource conflicts in inter-thread communication. ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/6727973/01_0_13145825558bRb.gif) \=================================================================================== **1. Introduction** 1. Can JAVA GUI applications run on Linux? Java compiles into bytecode, which is platform-independent and executed by the JVM. Therefore, .class files can run anywhere a JVM is available. 2. Can Java programs compiled on Windows ru --- ## Deep Dive into Linux Network Internals: Study Notes - URL: https://intl.sienovo.cn/blog/6725422 - Date: 2011-08-27 - Tags: #Network, #Linux, #Embedded, #Server ## Deep Dive into Linux Network Internals: Study Notes As embedded systems continue to evolve, networking plays an increasingly important role in their development. In this article, we'll delve into the Linux network internals and explore the key concepts and components that make up the Linux networking stack. ### I. Making Networking a New Growth Point for Embedded Systems If you're planning to develop your embedded system in the direction of servers, networking is an essential aspect that cannot be overlooked. In fact, Huagong's team has already demonstrated excellent networking expertise, which makes it easier to collaborate and learn from Dr. Liu. In this section, we'll provide a brief overview of the Linux network internals, focusing on the key components and their interactions. ### II. Linux Network Internals Overview The Linux network stack consists of several key components, including the network device drivers, the network protocol stack, and the socket layer. Each of the --- ## Summary of Array Search Methods - URL: https://intl.sienovo.cn/blog/6722430 - Date: 2011-08-26 - Tags: #Programming, #C **I. Introduction** The following explanation is based on a function that converts zone codes to Unicode in a Chinese character set. 1. ```cpp DWORD Unicode2GBQuWei(WORD wUnicode){ DWORD dwQuNum; DWORD dwWeiNum; DWORD i,dwResult = 0; for(i = 0; i < MAXUNICODENUM; i++) // Simplest and most straightforward search implementation { if(wUnicode == Unicode[i]) { dwResult = 0; if(GBQuWei[i] != DNULL) { dwQuNum = (DWORD)GBQuWei[i]; // Following four lines apply conversion rules dwWeiNum = (DWORD)GBQuWei[i]; dwQuNum = (dwQuNum & 0xff00) >> 8; dwWeiNum = dwWeiNum & 0x00ff; if(dwQuNum < 0x58) { dwDispAddQuWeiChinese(dwQuNum,dwWeiNum); } else { // The required Chin --- ## Summary of Chinese Character Encoding and Programming: How ASCII, Internal Code, Zone-Position Code, GB Code, and Unicode Are Converted - URL: https://intl.sienovo.cn/blog/6722193 - Date: 2011-08-26 - Tags: #Programming, #Transformation, #Character, #Windows, #Language, #Internet **I. How do ASCII, internal code, zone-position code, GB code, and Unicode convert among each other? What are the conversion formulas?** The process in Chinese character systems involves zone-position code, national standard code (GB code), and internal machine code. The conversion relationships are as follows: 1. **Convert zone-position code (decimal) to zone-position code (hexadecimal)**: Convert the zone number and position number separately into hexadecimal. For example, if a character's zone-position code is 5448, convert 54 to hexadecimal 36, and 48 to hexadecimal 30. The resulting hexadecimal code is 3630. 2. **GB Code = Zone-Position Code (hex) + 2020H** Example: 3630H + 2020H = 5050H → This yields the GB2312 national standard code. 3. **Internal Machine Code = GB Code + 8080H** Example: 5050H + 8080H = D0D0H. ASCII uses a single byte with the highest bit set to 0, which distinguishes it from Chinese character encoding. Unicode is a character enco --- ## ARM Resources Free Download - Super Comprehensive, Highly Recommended - URL: https://intl.sienovo.cn/blog/6717180 - Date: 2011-08-25 - Tags: #WinCE, #EmbeddedOS, #Embedded, #Linux, #Windows, #C ## ARM Resources Free Download - Super Comprehensive, Highly Recommended In this blog post, we will explore a collection of valuable resources available for free download related to ARM development boards and programming. These resources include schematics, source codes, and educational materials that can significantly aid engineers and developers working in embedded systems and ARM architecture. ### Free ARM Resources To express gratitude to the community for their support of [www.2beanet.com](http://www.2beanet.com/), a variety of ARM resources have been made available for free. Below is a list of the resources you can access: 1. **S3C2450 Development Board Schematic** A detailed schematic for the S3C2450 development board can be found [here](http://www.2beanet.com/index.php/embedded/arm/126-schematic-for-s3c2450-embedded-board.html). 2. **EP9315 (ARM9) Evaluation Board Schematic (Protel Format)** Download the schematic for the EP9315 evaluation board in Protel format --- ## Adding a Chinese Character Font Library (Part 2) — Methods for Storing and Extracting Chinese Character Patterns - URL: https://intl.sienovo.cn/blog/6717129 - Date: 2011-08-25 - Tags: #Storage, #InputMethod, #Byte, #Disk, #Testing, #2010 **A Chinese character library is like a Xinhua Dictionary!** **I. Introduction** After spending an entire day of precious time, I finally found the root cause: the dot-matrix extraction settings in the Chinese character generation software were incorrect, resulting in garbled or distorted display output. As shown in the figure below: ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/6717129/01_0_1314257074X058.gif) ![](https://pub-048dcb96257f476697b113fcb5939cb9.r2.dev/blog/6717129/02_0_1314257108A24i.gif) By habit, I had selected "horizontal extraction with MSB on the left" in the software. Upon closer inspection, however, I realized my code actually uses "vertical extraction with MSB at the bottom." I initially suspected the extraction mode might be wrong, but convinced myself that even if it were inverted, it would only result in a mirrored or upside-down font—nothing critical. Now I realize how wrong that assumption was. (Use your imagination.) Below is the --- ## 2011 Second Half Goals (Part One): Friends, Easy to Talk To - URL: https://intl.sienovo.cn/blog/6713604 - Date: 2011-08-24 - Tags: #Life, #Travel, #Interview, #Work I want to write a novel, and have favorite authors. Seeking happiness, expanding, acting, just like a job interview, you'll always find the right fit. Travel, the embrace of nature. Shenzhen Bay, rafting, water park, Fenghuang Ancient Town – surely I must go somewhere. It's been too long since I've been home, I miss my parents. Friends, eloquent, witty, easy to talk to (that's right, easy to talk to). \================= Friends, Easy to Talk To \================= This way, on one hand, it can enrich life, and on the other hand, it makes playing ball with others more interesting and allows for greater relaxation when going out. Also, it provides convenience for writing novels and for deep reflection on life. It's also good for providing a moment of ease when interacting with superiors at work. Therefore, it's extremely important. Although decadent, I always have ideas. Creativity, novelty, making people feel it's fun to be with you, and learning when necessary. --- ## LCD Driver (Part 3): Methods for Displaying BMP Images - URL: https://intl.sienovo.cn/blog/6711973 - Date: 2011-08-23 - Tags: #Byte, #Visio, #Baidu, #C, #Storage, #Expansion ====================== Objective ====================== Display a BMP image on an LCD screen. ================================================== **1. Q&A** 1. How are images represented in computers? What kind of encoding is used? Answer: Hexadecimal encoding. 2. How do you load an image? Use a pointer to locate where the image data is stored. The encoded image data is essentially an array. Retrieve pixel data and display it accordingly. Refer to the code examples below. 3. Static vs. Dynamic Display Answer: Static display has been implemented. It's similar to displaying Chinese characters using dot matrices, or how LED segment displays work — you've probably worked with those before. Dynamic display has not yet been implemented. 4. Image as Background and Other Uses Answer: Usage as background, foreground, transparency, solid fill, etc., is still unclear. 5. Where is the BMP image? Has it been converted into encoded data? Answer: Yes, a DOS-based tool can convert a BMP --- ## LCD Driver (Part 2): Adding Chinese Character Font Library - URL: https://intl.sienovo.cn/blog/6711962 - Date: 2011-08-23 - Tags: #Programming, #Sports, #API, #Tools \=================== ======= Goals ================================== 1. Familiarize oneself with the method for writing Unicode Chinese character font libraries. 2. Be able to write Chinese characters at specified positions, including horizontal and vertical alignment. Font size and color can be changed. 3. Requirement: Be able to add and use font libraries from scratch. \================================================================= **I. Problems** **1. What's the deal with Chinese character font library region codes? What about Unicode? How to programmatically retrieve the desired Chinese character.** Answer: 1) The Unicode of a Chinese character is its hexadecimal representation. 2) Unicode encoding uses 2 bytes to represent a character. 3) Unicode [b1][b2] = char For example, GB2312 region code: 94 regions, 94 characters per region. Region code = b1 - 0xbf, position code = b1 - 0xa0, which corresponds to Unicode. Ah = \ub0a1. 0xb0 - 0xbf = 0xf = 16 = region code. 0xa1 --- ## LCD Screen Driver Analysis (Part 1): How to Draw Points and Lines on an LCD Screen - URL: https://intl.sienovo.cn/blog/6710690 - Date: 2011-08-23 - Tags: #Makefile, #Byte, #ChemicalEngineering, #Programming, #Testing, #Work \=============  Objective  ===================== How to draw points and lines on an LCD screen \======================================= **I. Learning Insights** 1. How to write a test program? How to integrate it with a Makefile to compile a program (only include what's necessary—create your own project) 1) `LCDSetColor(WHITE,UNSET);` // Setting color is a fundamental task, including line color, font color, and background color 2) `DispSetPointDirect(6, 10);` // Set position 3) `LCDSetLine()` 2. I need to create a Makefile and a main.c file. The key is the initialization process—understanding the correct initialization sequence. 3. Random trial and error won't work anymore. I need to understand and experiment purposefully. Right now, I want to understand `xadd()` and `yadd()`. 4. Actually, I still don't grasp how it works internally. 5. Finally realized: At the beginning, things shouldn't be too complex—three-dimensional arrays ` Answer: ```cpp Defines MFC extensions and related classes, including: // Classes declared in this file //CObject //CCmdTarget; //CWnd //CButton class CBitmapButton; // Bitmap button (self-draw) class CControlBar; // control bar class CStatusBar; // status bar class CToolBar; // toolbar class CDialogBar; // dialog as --- ## JP Embedded Software Probation Assessment Requirements – Here are the Goals for the Next One and a Half Months - URL: https://intl.sienovo.cn/blog/6707792 - Date: 2011-08-22 - Tags: #Embedded, #LinuxKernel, #Linux, #NetworkProtocols, #Programming, #Server **New Employee** **Department** **Probationary Position** Embedded Software Engineer **Mentor** **Overall Training Objectives for the Probationary Period** 1. Familiarize with the setup of embedded experimental platforms and methods for compiling and debugging programs in a Linux environment. 2. Proficiently master Linux kernel customization and file system customization. 3. Possess advanced programming skills in a Linux environment (processes, threads, file I/O, network protocols). 4. Master the development methods and procedures for simple character device drivers. **First** **Month** **Assessment Item** **Detailed Description** **Assessment Standard** **Completion Status** **Assessment Result** Embedded Development Environment Setup Install virtual machine, cross-compiler, SMB server, configure super terminal, and become familiar with dnw download and burning commands. (1 week) Development environment operates normally, can successfully compile test programs, and --- ## Differences in NOR Flash and NAND Flash Boot Processes on mini2440 - URL: https://intl.sienovo.cn/blog/6707384 - Date: 2011-08-22 - Tags: #Flash, #C, #Storage, #Microsoft -------------------------------------------------------- Goal: Thoroughly read the mini2440 manual -------------------------------------------------------- **I. Debugging Experience** 1. A tip from an old computer scientist: When you encounter strange problems, restarting is one of the simplest solutions, because operating systems themselves have imperfections, whether it's Microsoft Windows or Apple computers. 2. USB-to-serial cable experiencing garbled characters: This indicates unstable functionality and performance of the serial cable. A high-performance one can be purchased to replace it. **II. Q&A** **1. What are NAND and NOR? What are the differences and connections between NAND boot and NOR boot? (Compiled and organized)** Answer: 1) Code can be executed directly from NOR Flash, but not from NAND Flash. In the 2410, if NAND boot mode is selected, the code in NAND is copied to RAM for execution. 2) Before each data read, NAND Flash seems to require writing 0x55, 0xAA, --- ## My Makefile Learning Notes - URL: https://intl.sienovo.cn/blog/6702197 - Date: 2011-08-19 - Tags: #Makefile, #Wildcard, #Expansion, #List, #Filter, #Emacs **1. Terminology Explanation** **1. Automatic Variables** $<: The entire dependency set. Expands to the first dependency file in the dependency list. $@: All files corresponding to the rule's target. Expands to the name of the current rule's target file. Note: $(OBJECTS) represents the collection of all targets. [Clarification needed: what is the essential difference?] $?: $^: Expands to the full list of dependencies (with duplicate filenames removed). @ expands to the name of the current rule's target file. $< expands to the first dependency in the dependency list (e.g., for `foo.o : foo.c foo.h bar.h`, $< represents `foo.c`), while $^ expands to the entire dependency list (with duplicates removed). Using these variables, we can rewrite the above makefile as: ```cpp === makefile start === OBJS = foo.o bar.o CC = gcc CFLAGS = -Wall -O -g myprog : $(OBJS) $(CC) $^ -o $@ // Here, $^ represents the full dependency list, foo.c, bar --- ## Haige, A Month Later - URL: https://intl.sienovo.cn/blog/6701653 - Date: 2011-08-19 - Tags: none Okay, for now, I'll focus on mastering the technology. A month later, I'll decide based on the situation. Why do I feel a bit like Cao Cao now: "I'd rather betray the world than let the world betray me." Is it because of playing Sanguosha? Or... has the world gained another opportunistic villain? What a tragedy! I'll focus for a month and try to master all the technologies in JP first. I need to be as productive, as driven, and as energetic as I was in the first two weeks. I need to quickly familiarize myself with the GPS, USB source code, or the entire source code architecture first. Then it won't be so difficult in the future... If I go to Haige for an inspection within half a month, I'll just say I have something to do at home. The difficult part is social security. Alas, you win some, you lose some. Why do I feel so insecure? --- ## Makefile Example Explained (Fully Annotated) - URL: https://intl.sienovo.cn/blog/6701143 - Date: 2011-08-19 - Tags: #Makefile, #Wildcard \# For 2416 Project \# Written by lx-gzjp-2011-7-19 #\*\*\*\*\*\*\*\*\*\*\* setting \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* CC := gcc OUTDIR := obj OUTBINNAME := go SRC\_DIR := ./ 2416def/ bmp/ lcddriver/ disp/ zklib/ gps/ usb/ timer/ anet/ omc/ #\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* LINK := $(CC) -o LINETHREAD := -lpthread -lm CFLAG := -c -O2 -o SRC\_SUFFIX := .c OBJSUFFIX := .o SRCS := $(foreach n, $(SRC\_DIR), $(wildcard $(n)*$(SRC\_SUFFIX))) OBJECTS := $(patsubst $(SRC\_SUFFIX), $(OUTDIR)/$(OBJ\_SUFFIX), $(notdir $(SRCS))) all : $(OUTDIR) $(OUTDIR)/$(OUTBINNAME) .PHONY : all $(OUTDIR): mkdir $(OUTDIR) @ $(OUTDIR)/$(OUTBINNAME): $(OBJECTS) $(LINK) $@ $(OBJECTS) $(LINETHREAD) @echo "Finished!" @echo "Bin file is $(OUTDIR)/$(OUTBINNAME)!" --- ## Makefile Terminology Glossary - URL: https://intl.sienovo.cn/blog/6700382 - Date: 2011-08-19 - Tags: #Makefile, #Wildcard, #Expansion, #Object, #GCC, #Language **I. Terminology Analysis** **1. Automatic Variables** $<: All dependencies, e.g., fs.c, pipe.c. Expands to the first prerequisite in the dependency list. $@: All files corresponding to the rule's target. Expands to the target filename of the current rule. Note: `$(OBJECTS)` refers to the collection of all targets. $?: $^: Expands to the entire list of prerequisites (removing all duplicate filenames). The `@` expands to the target filename of the current rule, `<` expands to the first prerequisite in the dependency list (e.g., for `foo.o : foo.c foo.h bar.h`, `<` represents `foo.c`), and `^` expands to the entire list of prerequisites (removing all duplicate filenames). Using these variables, we can write the above makefile as: ```cpp === makefile Start === OBJS = foo.o bar.o CC = gcc CFLAGS = -Wall -O -g myprog : $(OBJS) $(CC) $^ -o $@ // Here, $^ represents the entire list of prerequisites, which are foo.c, bar.c (implicit r --- ## Reflections on Linux: Environment Setup - URL: https://intl.sienovo.cn/blog/6698742 - Date: 2011-08-18 - Tags: #linux, #Tools ## Reflections on Linux: Environment Setup When working with Linux, having a solid environment setup is crucial for efficient and effective development. A well-configured environment can make all the difference in productivity, and in this article, we'll explore the importance of setting up a stable and goal-oriented environment. ### Sharpening the Axe: The Importance of Good Tools The phrase "sharpening the axe doesn't delay the woodcutting" is a Chinese idiom that emphasizes the importance of preparation and setup. In the context of Linux development, this means sparing no effort in installing and using good tools. A good toolchain can save you a significant amount of time and effort in the long run, and it's essential to invest time in setting up the right tools from the beginning. ### The Environment Must Be Stable A stable environment is the foundation of any successful development project. Stability enables progress, and it's essential to ensure that your environment is rock --- ## Installation Steps for VMware Tools on Red Hat 9 - URL: https://intl.sienovo.cn/blog/6698719 - Date: 2011-08-18 - Tags: #RedHat, #VMware, #VirtualMachine, #Graphics, #Tools ## Installation Steps for VMware Tools on Red Hat 9 In this guide, we will walk through the installation steps for VMware Tools on Red Hat 9. VMware Tools is a suite of utilities that enhances the performance of the virtual machine's guest operating system and improves management of the VM. By following these steps, you'll ensure that your Red Hat 9 virtual machine is optimized for use within a VMware environment. ### Step-by-Step Installation Process 1. **Install VMware Tools from VMware Workstation** Start by launching VMware Workstation. Navigate to the menu and select **Virtual Machine → Install VMware Tools**. This action will mount the VMware Tools installation CD image to your virtual machine. 2. **Log in to Red Hat 9 as Root** You need to log in to your Red Hat 9 system with root privileges. This is essential because the installation requires administrative access to modify system files. 3. **Mount the CD-ROM** Open a terminal and execute the following comma --- ## Issues with Samba Folder Uploads, Mapping Samba Directories to Windows Drives, and Using Source Insight for Linux Projects - URL: https://intl.sienovo.cn/blog/6698541 - Date: 2011-08-18 - Tags: #Linux, #Windows, #Vim, #RedHat, #Firewall, #Server A friend recently encountered a problem: how to map a Samba directory as a Windows drive, and why his Samba couldn't upload directories. Today, I'm writing down the solutions to these two problems, hoping to help others who encounter similar issues. **Problem 1: How to map?** First, you need to start your Linux system, correctly configure your Samba server, and set the permissions of the shared directory to 777. All directories must be traversable. Then, go back to Windows, right-click 'My Computer' (or 'This PC'), select 'Map network drive', click 'Browse' next to 'Folder', choose your Samba directory, and click 'Finish'. That's it. This way, you won't have to type the Linux IP address in the 'Run' dialog every time you want to access Samba files from Windows. Now the Samba directory is a local directory on your Windows machine, and you can access it normally. **Problem 2: After creating Samba, I found that individual files could be dragged in, but directories could not?** We --- ## Using rz and sx Commands — Downloading Files to Target Board via Serial Terminal - URL: https://intl.sienovo.cn/blog/6698501 - Date: 2011-08-18 - Tags: #Terminal, #Makefile, #Compiler, #Windows, #Linux, #Testing The newly downloaded Linux source code does not include the super terminal commands by default and must be added manually. After adding them, the development board can transfer files from a PC through a serial port. Steps: 1. Download the software rzsz-3.48.tar.gz from [http://freeware.sgi.com/source/rzsz/rzsz-3.48.tar.gz](http://freeware.sgi.com/source/rzsz/rzsz-3.48.tar.gz). 2. Extract: `tar zxvf rzsz-3.48.tar.gz` 3. Install: `cd src` `vi Makefile` Modify `CC=arm-linux-gcc` Save and exit Run `make posix` Note: This software installation differs from standard GNU software — there is no configure step or `make install` process. I'm using an S3C2410 cross-compiler; for different platforms, only the cross-compiler needs to be changed. After running `make posix`, if the compilation succeeds, run the `ls` command and you will see many new files: ``` COPYING gz minirb.c rc rz.c sz undos.doc zmodem.h crc.c m --- ## Yaffs2 File System Porting to mini2440 - URL: https://intl.sienovo.cn/blog/6698000 - Date: 2011-08-18 - Tags: #LinuxKernel, #Bash, #Script, #System, #Makefile, #Compiler ### Yaffs2 File System Porting to mini2440 Most development boards now support the Yaffs2 file system. It is a file system specifically created for embedded devices, especially those using NAND flash as storage. Earlier Yaffs versions only supported small-page (512-byte/page) NAND flash, while Yaffs2 supports large-page NAND flash. The so-called root file system involves creating various directories and files within them. For example, executable programs are stored in `/bin` and `/sbin` directories, configuration files in `/etc`, and library files in `/lib`. Let's begin the file system porting process. ### I. Preparation 1. **Obtaining Yaffs2 Source Code** The latest Yaffs2 source code can be downloaded from http://www.yaffs.net/node/346. If using the git tool, enter the following command in the terminal: ```bash #git clone git://www.aleph1.co.uk/yaffs2 ``` This will download the Yaffs2 source code to the current directory. 2. **Download Busybox-1.13.3** --- ## Error When Booting File System: Warning: unable to open an initial console - URL: https://intl.sienovo.cn/blog/6697968 - Date: 2011-08-18 - Tags: #Bash, #Script, #Command, #C, #Shell, #Null ———————————————————————————————— (1) Error occurs when booting the file system: Warning: unable to open an initial console. ———————————————————————————————— Specific error: ```cpp yaffs: dev is 32505858 name is "mtdblock2"yaffs: passed flags ""yaffs: Attempting MTD mount on 31.2, "mtdblock2"yaffs: auto selecting yaffs2s3c-nand: ECC uncorrectable error detectedblock 109 is badVFS: Mounted root (yaffs filesystem).Freeing init memory: 140KWarning: unable to open an initial console. ``` Root cause investigation: 1) The /dev/console and /dev/null files in the downloaded file system were deleted. Recreate them using: mknod –m 660 console c 5 1 mknod –m 660 null c 1 3 2) Ensure that /dev/console exists on your root file system. 3) Are you sure your rootfs is actually cramfs? If it's jffs2, try adding rootfstype=jffs2 to the kernel command line. 4) After enabling devfs support in the kernel configuration, the warning "unable to open an initial console" disappeared, and the message --- ## Boot Error: Starting kernel ... - URL: https://intl.sienovo.cn/blog/6693781 - Date: 2011-08-17 - Tags: #Flash, #Mobile, #C —————————————— （一）出现如下错误启动信息 —————————————— ```cpp U-Boot 1.3.4 (Jun 30 2011 - 09:01:15) for SMDK2416 CPU: S3C2416@400MHz Fclk = 800MHz, Hclk = 133MHz, Pclk = 66MHz Board: SMDK2416 Mobile DDR DRAM: 64 MB Flash: 1 MB NAND: 128 MB *** Warning - bad CRC or NAND, using default environment In: serial Out: serial Err: serial Hit any key to stop autoboot: 0 SAM2416EDK # dnw Now, Waiting for DNW to transmit data SAM2416EDK # resetOK U-Boot 1.3.4 (Jun 30 2011 - 09:01:15) for SMDK2416 CPU: S3C2416@400MHz Fc --- ## 爱立信-广州-服务器后台开发 - URL: https://intl.sienovo.cn/blog/6693721 - Date: 2011-08-17 - Tags: #Server, #LinuxKernel, #qt, #Programming ## Ericsson - Guangzhou - Server Backend Development As a developer interested in server backend development, you may have come across the Ericsson Guangzhou server development project. In this article, we will explore the skills and knowledge required to work on such a project, including English language proficiency, Linux kernel programming, and application development using QT. ### English Language Proficiency Having a strong command of the English language is essential for any developer working on a project like Ericsson Guangzhou. This includes not only writing English resumes and cover letters but also being able to communicate effectively with colleagues and clients. Proficiency in English speaking and writing is crucial for success in this field. ### Linux Kernel Programming Linux kernel programming is another critical skill required for server backend development. This involves understanding the inner workings of the Linux kernel, including device drivers, system calls, a --- ## Linux System Porting (Most Comprehensive and Detailed Ever, Highly Recommended) - URL: https://intl.sienovo.cn/blog/6692229 - Date: 2011-08-16 - Tags: #Linux, #Flash, #Struct, #DataStructures, #GCC, #Cmd Linux System Porting Table of Contents Part One: Foreword...................................................................................................................................8 1 Hardware Environment.....................................................................................................................8 1.1 Host Hardware Environment.......................................................................................................8 1.2 Target Board Hardware Environment...........................................................................................8 1.3 Tool Introduction.......................................................................................................................8 2 Software Environment......................................................................................................................8 2.1 Host Software Environment........................................................................................... --- ## Feeling One Step Closer to Linus Benedict Torvalds (The Path to the Linux Pantheon) - URL: https://intl.sienovo.cn/blog/6691655 - Date: 2011-08-16 - Tags: #linux ## The Path to the Linux Pantheon: Understanding Linux through Compilation As a Linux enthusiast, you may have felt a sense of accomplishment and pride when you successfully compiled the Linux kernel from source. However, this feeling is not just about the technical achievement, but also about the journey of understanding the inner workings of Linux. In this article, we will explore the path to the Linux pantheon, and how compiling and using the command line can help you gain a deeper understanding of Linux. ### The Importance of Understanding Linux Linus Torvalds, the creator of Linux, has always emphasized the importance of understanding Linux. He believes that knowing how to use Linux is essential, and that compiling and using the command line are a form of usage. By actively seeking to understand Linux, you will gradually gain a deeper appreciation for the operating system and its underlying mechanics. ### Compiling and Using the Command Line Compiling the Linux kernel from so --- ## YAFFS2 Root Filesystem Creation and Installation (Including Issues: [drivers/video/console/vgacon.o] Error 1) - URL: https://intl.sienovo.cn/blog/6690435 - Date: 2011-08-16 - Tags: #Function, #Each —————————————————— （一）Root Filesystem Installation Q&A —————————————————— 1. First, compile into a complete filesystem. 2. Could there be an issue with my kernel? Try rebuilding it (treat it as a review exercise for generating kernel images). 3. Creating the YAFFS2 filesystem. Question 4: After decompression, nothing appears. Answer: —————————————————— （二）Issues Encountered \[drivers/video/console/vgacon.o\] error 1 \[drivers/video/console\] Error 2 \[drivers/video\] Error 2 —————————————————— drivers/video/console/vgacon.c: In function 'vgacon\_startup':... When executing `make uImage` after configuration, the following error appears. Judging from the message, it seems related to VGA support. Here, I resolved it by disabling the VGA-related configuration options. Device Drivers       ----> Graphics support               -----> Console display driver support             -----> VGA text Console (unselecting this option resolves the issue) CC      drive --- ## DNW Installation and Download - URL: https://intl.sienovo.cn/blog/6688483 - Date: 2011-08-15 - Tags: none ## Installing and Downloading DNW: A Step-by-Step Guide DNW (Device Node Wrapper) is a utility used for managing and interacting with devices on embedded systems. However, the installation and download process can be confusing, especially for those who are new to this technology. In this article, we will walk through the process of installing and downloading DNW, focusing on the specific versions for FriendlyARM and smdk2416 boards. ### Pay Attention to the Version Before proceeding with the installation, it is essential to note that there are different versions of DNW available, each designed for specific boards. The two versions mentioned in this article are for FriendlyARM and smdk2416. It is crucial to choose the correct version for your board to avoid any compatibility issues. ### Installing the DNW Driver To install the DNW driver, you will need to use the folder search method to locate the driver files. This method allows you to search for the driver files within a specifie --- ## Kernel Porting (Including LCD Screen, OTG-USB) - URL: https://intl.sienovo.cn/blog/6688258 - Date: 2011-08-15 - Tags: none Kernel porting is a fundamental task for engineers working with embedded Linux systems, especially in specialized domains like edge-AI and industrial computing where hardware configurations are often unique. At Sienovo, we understand the critical need for robust, tailored kernel images that precisely match the capabilities of our industrial computing platforms. This post delves into common challenges encountered during kernel compilation and provides practical steps for integrating essential drivers, such as those for LCD screens, into a custom kernel image. By understanding these procedures, developers can overcome hurdles like PCI compilation errors and successfully bring up custom display interfaces, ensuring their embedded systems perform optimally. ## Kernel Compilation into an Image File The process of compiling a Linux kernel for an embedded system typically involves cross-compilation, where the kernel is built on a host machine (e.g., a desktop PC) for a target architecture ( --- ## How to Install a Cross-Compiler Toolchain (Successfully Compiled) - URL: https://intl.sienovo.cn/blog/6678654 - Date: 2011-08-11 - Tags: #Tools, #Path, #Compiler, #Linux, #C First, copy the file arm-linux-gcc-4.3.2.tgz from the CD directory linux\\ to a local directory such as tmp\\, then navigate into that directory and execute the extraction command: #cd /tmp #tar xvzf arm-linux-gcc-4.3.2.tgz –C / Note: There is a space after –C, and C must be uppercase. It stands for the word "Change", meaning to change the target directory. Executing this command will install arm-linux-gcc into the /usr/local/arm/4.3.2 directory. Second, add the compiler path to the system environment variables by running: #gedit /root/.bashrc Edit the /root/.bashrc file, and add the following line at the end: export PATH=$PATH:/usr/local/arm/4.3.2/bin Save the file and exit, as shown in the figure. Third, log back into the system (no need to reboot—just log out via Start -> Logout) to activate the above settings. Then type the following command in the terminal: arm-linux-gcc –v If you see output similar to the one shown below, the cross-compilation environm --- ## August Programming Manifesto — Pushing Oneself and Finding Joy - URL: https://intl.sienovo.cn/blog/6676495 - Date: 2011-08-10 - Tags: #Programming, #Multithreading, #Networking, #Linux, #NetEase, #Documentation ## August Programming Manifesto — Pushing Oneself and Finding Joy In this blog post, we will explore the key principles outlined in the August Programming Manifesto, focusing on practical programming, the importance of multithreading and networking in Linux applications, and effective strategies for reading source code. These insights aim to enhance your programming skills and foster a deeper understanding of the development process. ### (I) August Manifesto 1. **Focus on Practical Programming** The first principle emphasizes the importance of concentrating your energy on practical programming tasks. This means dedicating time to write code, debug, and solve real-world problems rather than getting lost in theoretical concepts or distractions. 2. **Full Immersion in Programming** The manifesto encourages total immersion in programming activities. This includes being willing to engage in simple tasks, such as executing code or transcribing existing code. The idea is that ev --- ## Linux Compression and Decompression Commands - URL: https://intl.sienovo.cn/blog/6675256 - Date: 2011-08-10 - Tags: #Linux tar \-c: Create a compressed archive \-x: Extract \-t: List contents \-r: Append files to the end of the archive \-u: Update files in the original archive These five options are standalone commands; one of them must be used for either compression or extraction. They can be combined with other options, but only one of these five may be used at a time. The following options are optional and can be used as needed during compression or extraction. \-z: Use gzip compression \-j: Use bzip2 compression \-Z: Use compress compression \-v: Display all process details \-O: Extract files to standard output The following option, -f, is required: \-f: Specify the archive file name. Remember, this option must be the last one in the command line, and only the archive filename should follow it. \# tar -cf all.tar \*.jpg This command packages all .jpg files into an archive named all.tar. -c indicates creating a new archive, and -f specifies the archive filename. \# tar -rf all. --- ## JP Phone Day 1 (2011.8.10) - Environment Setup (What are GPS and Wireless Networks) - URL: https://intl.sienovo.cn/blog/6675028 - Date: 2011-08-10 - Tags: #Network, #MobilePhone, #Socket, #Programming ## Understanding Wireless Networks and GPS on Mobile Devices In this article, we will explore the basics of wireless networks and GPS on mobile devices. We will examine the socket code for wireless networks and provide an overview of the gps.c code. Additionally, we will discuss how to increase the LCD buffer. ### Developing a Habit of Writing and Debugging Code Developing a habit of writing and debugging code is essential for any programmer. It's crucial to create a habit of writing and debugging code at the company to improve your skills. By doing so, you will be able to identify and fix errors quickly, which is a vital skill for any programmer. ### Setting Up a Development Environment A development environment is crucial for any programmer. The company provides a real project development environment, which is a great resource for learning and experimenting with new technologies. It would be great if the company could send you for training or cover the training costs, as this wo --- ## Detailed Comments on the scull Module in Chapter 3 of LDD3 for Linux Driver Development - URL: https://intl.sienovo.cn/blog/6656888 - Date: 2011-08-03 - Tags: #Linux, #Struct, #Module, #REST, #NULL, #Semaphore ```cpp #include #include #include #include /* printk() */ #include /* kmalloc() */ #include /* everything... */ #include /* error codes */ #include /* size_t */ #include /* O_ACCMODE */ #include #include /* cli(), *_flags */ #include /* copy_*_user */ #include "scull.h" /* local definitions */ /* * Our parameters which can be set at load time. */ // Major device number int scull_major = SCULL_MAJOR; // Minor device number int scull_minor = 0; // Number of consecutive device numbers requested int scull_nr_devs = SCULL_NR_DEVS; /* number of bare scull devices */ // Quantum size int scull_quantum = SCULL_QUANTUM; // Quantum set size int scull_qset = SCULL_QSET; module_param(scull_major, int, S_IRUGO); --- ## Linux 0.11 namei.c Comments - URL: https://intl.sienovo.cn/blog/6652042 - Date: 2011-08-01 - Tags: #Linux, #Struct, #Null, #Buffer, #Disk, #Byte The `permission()` function first checks if the i-node has a corresponding device but no links. If so, it returns 0, indicating that the file is deleted and cannot be accessed. Otherwise, it checks if the effective user ID (euid) of the current process matches the user ID of the file. If so, it shifts the file's mode to the left by 6 bits, effectively ignoring the user ID. If the euid does not match the user ID, it checks if the effective group ID (egid) of the current process matches the group ID of the file. If so, it shifts the file's mode to the left by 3 bits, effectively ignoring the group ID. --- ## How to Become an Embedded Engineer (I) — Introduction - URL: https://intl.sienovo.cn/blog/6648879 - Date: 2011-07-31 - Tags: #Embedded, #Life ##### How to Become an Embedded Engineer (I) — Introduction In March 2005, I arrived in Beijing alone. The sky was clear, the breeze gentle, and brilliant sunlight poured down from a vast azure sky, almost delightfully overwhelming. It was here that a young man would begin his journey toward becoming an embedded engineer. Growth always comes at a price—yet behind every hardship lie the joy of success and the bitterness of failure. Every college graduate fresh out of school, like myself, once held the same belief: we were the nation's blossoming flowers, the future of socialism, the great post-80s generation, shouldering the historic mission of achieving the Four Modernizations. But when reality clashes fiercely with ideals, anyone would feel lost. Beautiful dreams often cannot withstand the brutality of real life. After the storm, we pick up the shattered pieces of our beliefs and set off once again. But tell me, where does the path ahead truly lie? I write these words to share wit --- ## Reflecting on My Learning Habits - URL: https://intl.sienovo.cn/blog/6552328 - Date: 2011-06-17 - Tags: #Algorithm, #Task ## Reflections on Learning Habits and Productivity As a developer and technical writer, I often find myself struggling with productivity and the ability to articulate complex ideas. In this article, we'll explore some common pitfalls that can hinder our learning and writing habits, and discuss strategies for overcoming them. ### Why Do We Struggle to Focus? When we consume too much information without adequately processing it, our brains can become overwhelmed and our ability to reason and think critically is impaired. This can lead to feelings of confusion and mental fatigue. ### The Importance of Balancing Visual and Cognitive Input Relying too heavily on visual information can lead to a lack of engagement from our brains, which are wired to process and analyze complex ideas. Conversely, not using our eyes enough can also hinder our ability to learn and think deeply. ### The Role of Communication in Learning Speaking and writing are essential skills for effective communication ---